Dario Binacchi [Sat, 22 Feb 2020 13:05:43 +0000 (14:05 +0100)]
video: omap: add loop exit conditions to the dpll setup
In case of null error, round rate is equal to target rate, so it is
useless to continue to search the DPLL setup parameters to get the
desidered pixel clock rate.
Tero Kristo [Fri, 14 Feb 2020 07:05:10 +0000 (09:05 +0200)]
power: mfd: k3_avs: update am65xx MPU_VDD voltage values
The latest data manual SPRSP08I –NOVEMBER 2017–REVISED DECEMBER 2019[1]
for am65xx SoC states the new MPU nominal voltages to be 1.1V (OPP_NOM),
1.2V (OPP_OD) and 1.24V (OPP_TURBO). Update the nominal voltages in the
K3 AVS driver to reflect this.
Tero Kristo [Fri, 14 Feb 2020 09:18:18 +0000 (11:18 +0200)]
arm: dts: k3-j721e: Add ESM PMIC support for tps659413 based board
The ESM handling on J7 processor board requires routing the
MCU_SAFETY_ERROR signal to the PMIC on the board for critical safety
error handling. The PMIC itself should then reset the board based on
receiving it. Enable the support for the board by adding the esm
node in place.
Tero Kristo [Fri, 14 Feb 2020 09:18:17 +0000 (11:18 +0200)]
arm: dts: k3-k721e: Add Main domain ESM support
Main domain ESM support is needed to configure main domain watchdogs
to generate ESM pin events by default. On J7 processor board these
propagate to the PMIC to generate a reset when watchdog expires.
Tero Kristo [Fri, 14 Feb 2020 09:18:16 +0000 (11:18 +0200)]
misc: pmic_esm: Add support for PMIC ESM driver
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.
Tero Kristo [Fri, 14 Feb 2020 09:18:15 +0000 (11:18 +0200)]
misc: k3_esm: Add support for Texas Instruments K3 ESM driver
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.
Keerthy [Wed, 12 Feb 2020 08:25:10 +0000 (13:55 +0530)]
configs: j721e_evm_r5: Enable R5F remoteproc support
Enable R5F remoteproc support in R5 defconfig so that R5s can
be started in SPL. While at it enable the SPL_FS_EXT4 config
option to load the firmwares from file system.
Lokesh Vutla [Tue, 4 Feb 2020 05:39:50 +0000 (11:09 +0530)]
ARM: mach-k3: sysfw-loader: Use SPI memmapped addr when loading SYSFW
Since ROM configures OSPI controller to be in memory mapped mode in OSPI
boot, R5 SPL can directly pass the memory mapped pointer to ROM. With
this ROM can directly pull the SYSFW image from OSPI.
ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU
Populate address mapping entries in A53 MMU for 4 GB of MMIO space
reserved for providing MMIO access to multiple flash devices through
OSPI/HBMC IPs within FSS.
Descend to drivers/soc directory unconditionally for SPL and U-Boot
builds. Individual drivers can have their own config to check what needs
to be built for SPL. There should be no increase in SPL code size
due to this change.
This is required on K3 SoCs to support DMA in SPL.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Printing the error message in verbose mode fails, since python3
doesn't implicitely convert bytes to strings.
Signed-off-by: Markus Klotzbuecher <mk@mkio.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Commit b237d358b425 ("moveconfig: expand simple expressions") added
support for expanding expressions in configs, but used the unsafe python
built-in "eval". This patch fixes this by replacing eval with the
asteval module.
Signed-off-by: Markus Klotzbuecher <mk@mkio.de> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Commit 856b9cdb53f0 ("powerpc: mpc85xx: delete FSL_SATA for T2080QDS
board.") is to fit support sata DM mode, Now the driver will be reverted,
So revert it.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Commit 1ee494291880 ("ata: fsl_ahci: Add sata DM support for Freescale
powerpc socs") introduced SCSI layer to call AHCI private API in order
to support sata operations, In DM mode, This is not necessary for
non-AHCI sata. So revert it and have already updated the driver itself
to operate sata directly.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Update doc/sphinx/kerneldoc.py from Linux next-20200219 to avoid warnings
like:
doc/sphinx/kerneldoc.py:125: RemovedInSphinx20Warning:
AutodocReporter is now deprecated. Use
sphinx.util.docutils.switch_source_input() instead.
self.state.memo.reporter =
AutodocReporter(result, self.state.memo.reporter)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Masahiro Yamada [Fri, 14 Feb 2020 07:40:27 +0000 (16:40 +0900)]
mmc: sdhci: fix missing cache invalidation after reading by DMA
This driver currently performs cache operation before the DMA start,
but does nothing after the DMA completion.
When reading data by DMA, the cache invalidation is needed also after
finishing the DMA transfer. Otherwise, the CPU might read data from
the cache instead of from the main memory when speculative memory read
or memory prefetch occurs.
Instead of calling the cache operation directly, this commit adds
dma_unmap_single(), which performs cache invalidation internally,
but drivers do not need which operation is being run.
Masahiro Yamada [Fri, 14 Feb 2020 07:40:26 +0000 (16:40 +0900)]
mmc: sdhci: use dma_map_single() instead of flush_cache() before DMA
Currently, sdhci_prepare_dma() calls flush_cache() regardless of the
DMA direction.
Actually, cache invalidation is enough when reading data from the device.
This is correctly handled by dma_map_single(), which mimics the DMA-API
in Linux kernel. Drivers can be agnostic which cache operation occurs
behind the scene.
This commit also sanitizes the difference between the virtual address
and the dma address.
Kever Yang [Wed, 19 Feb 2020 09:51:07 +0000 (17:51 +0800)]
rockchip: rk3399: add target type for evb based board
There are many boards share the board file and device header file with
rk3399 evb, add target type MACRO so that it is fixed instead of default
to the first target in "RK3399 board select".
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Masahiro Yamada [Fri, 14 Feb 2020 07:40:19 +0000 (16:40 +0900)]
dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.
Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.
If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.
Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.
Rasmus Villemoes [Thu, 30 Jan 2020 12:06:45 +0000 (12:06 +0000)]
mmc: fsl_esdhc: actually enable cache snooping on mpc830x
The reference manuals for MPC8308 and MPC8309 both say that the
esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the
System configuration registers. Unfortunately, that doesn't mean that
the registers are just mirrors of each other - any write to esdhcctl
is simply ignored. So to actually enable cache snooping, we
unfortunately have to add a little ifdeffery.
There is, naturally, no description of the bit fields of esdhcctl in
the MPC8309 manual, but comparing the description of esdhcctl from the
LS1021A reference manual to the description of the sdhccr in MPC8309,
one also finds that the fields are bit-reversed, so the bit to set is
0x02000000 rather than 0x00000040 - this is also what board_mmc_init()
uses in the two gdsys/mpc8308/ boards.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Yangbo Lu <yangbo.lu@nxp.com>
Suniel Mahesh [Mon, 3 Feb 2020 13:50:05 +0000 (19:20 +0530)]
board: roc-pc-rk3399: Add support for onboard LED's and push button to indicate power mode
Added support for onboard LED's and push button. When powered board will be
in low power mode(yellow LED), on button press, board enters full power mode
(red LED) and boots u-boot.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Suniel Mahesh [Mon, 3 Feb 2020 13:50:04 +0000 (19:20 +0530)]
rockchip: rk3399: split roc-pc-rk3399 out of evb_rk3399
roc-pc-rk3399 board has one user button & three user LED's. Currently
we don't have any code support for these devices. Since button and LED's are
specific to roc-pc-rk3399 board, split it into its own board file and add code
support here.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Hugh Cole-Baker [Sat, 25 Jan 2020 16:19:36 +0000 (16:19 +0000)]
rockchip: boot_mode: find the saradc device name
adc_channel_single_shot() requires the full device name e.g.
"saradc@ff100000", which differs between Rockchip SoC's, but they all
share the prefix "saradc"; find the ADC device with this name prefix and
use its full name.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Thu, 23 Jan 2020 14:12:19 +0000 (19:42 +0530)]
rockchip: rk3288: Enable pre console buffer
Enable pre console buffer for rk3288 platform.
This would help to capture the console messages prior to
the console being initialised. Enabling this would help
to capture all the console messages on video output source
like HDMI. So we can find the full console messages of
U-Boot proper on HDMI display when enabled it for RK3288
platform boards.
Buffer address used for pre console is 0x0f000000 which is
ram base plus 240MiB. right now the Allwinner SoC is using
similar computation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Wed, 22 Jan 2020 09:31:43 +0000 (10:31 +0100)]
rockchip: px30: sync the main px30 dtsi from mainline
There have been multiple peripherals added to the main px30 dtsi
in the Linux kernel since its addition to u-boot. So to make it easier
to sync board devicetrees, update the core dtsi from Linux.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Mon, 20 Jan 2020 09:17:00 +0000 (09:17 +0000)]
arm: dts: rockchip: rk3399: Move U-Boot specific bits to rk3399-u-boot
There's some bits in the U-Boot rk3399.dtsi that aren't yet in the
upstream Linux dtsi but are needed for early boot. This moves them
to the u-boot.dtsi to make it easier to sync the rest of rk3399.dtsi
with upstream.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Mon, 20 Jan 2020 09:15:26 +0000 (09:15 +0000)]
arm: dts: rockchip: Update EVB/Puma devices to upstream USB/dwc3 conventions
The upstream linux kernel for the Rockchip 3399 SoC use usbdrd3 naming so move
the two remaining devices over to that for their device trees to make it
easier to sync with upstream DTs.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Fri, 17 Jan 2020 20:37:09 +0000 (21:37 +0100)]
rockchip: make the global board_fit_config_name_match __weak
The core Rockchip spl code contains a default board_fit_config_name_match
implementation doing nothing. Individual boards may want to handle this
differently, so add a __weak atribute to make it possible to override
this function in other places.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Tue, 18 Feb 2020 12:08:05 +0000 (07:08 -0500)]
Merge tag 'bugfixes-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c bugfixes for 2020.04
- i2c: designware_i2c: Correct the selection of speed mode Fixes: d96440d1e3 ("i2c: designware_i2c: Add support for fast-plus speed")
Masahiro Yamada [Thu, 23 Jan 2020 05:31:12 +0000 (14:31 +0900)]
mmc: check the return value of mmc_select_mode_and_width()
Since commit 01298da31d92 ("mmc: Change mode when switching to a boot
partition"), errors in mmc_select_mode_and_width() are ignored.
The return value should be checked.
Fixes: 01298da31d92 ("mmc: Change mode when switching to a boot partition") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Masahiro Yamada [Tue, 21 Jan 2020 09:42:05 +0000 (18:42 +0900)]
mmc: sdhci-cadence: send tune request twice to work around errata
Cadence sent out an errata report to their customers of this IP.
This errata is not so severe, but the tune request should be sent
twice to avoid the potential issue.
Quote from the report:
Problem Summary
---------------
The IP6116 SD/eMMC PHY design has a timing issue on receive data path.
This issue may lead to an incorrect values of read/write pointers of
the synchronization FIFO. Such a situation can happen at the SDR104
and HS200 tuning procedure when the PHY is requested to change a phase
of sampling clock when moving to the next tuning iteration.
Workarounds
-----------
The following are valid workarounds to resolve the issue:
1. In eMMC mode, software sends tune request twice instead of once at
each iteration. This means that the clock phase is not changed on
the second request so there is no potential for clock instability.
2. In SD mode, software must not use the hardware tuning and instead
perform an almost identical procedure to eMMC, using the HRS34 Tune
Force register.
Tom Rini [Fri, 14 Feb 2020 12:31:47 +0000 (07:31 -0500)]
Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
projects / u-boot.git / log