Heiko Schocher [Sun, 1 Dec 2019 10:23:19 +0000 (11:23 +0100)]
imx6: aristainetos: add DM_VIDEO support
add DM_VIDEO support and remove now unneeded board
code. As we show a bmp logo on boot, call now
bmp_display() from board code and do not use
cfb_console anymore.
Heiko Schocher [Sun, 1 Dec 2019 10:23:11 +0000 (11:23 +0100)]
imx6: aristainetos: remove aristainetos-v2.c
remove aristainetos-v2.c file, as we now want to
switch to DM/DTS support and have all board specific
code in one file. Goal is to setup differences
through DT.
Heiko Schocher [Sun, 1 Dec 2019 10:23:09 +0000 (11:23 +0100)]
imx6: aristainetos: add device tree from linux
Add device trees from Linux in preparation for driver model
conversions.
device tree files taken from Linux: 71ae5fc87c34: "Merge tag 'linux-kselftest-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest"
Heiko Schocher [Sun, 1 Dec 2019 10:23:07 +0000 (11:23 +0100)]
imx6: aristainetos: remove 2b version
remove 2b version of aristainetos board, as it
is easier to make the DM / DTS port and introduce
the 2b board version again (also some more board
version).
Tom Rini [Fri, 3 Jan 2020 17:00:04 +0000 (12:00 -0500)]
Revert "mmc: davinci: drop struct davinci_mmc_plat"
Adam Ford reports that this change breaks booting on da850-evm and
Bartosz Golaszewski agrees that with the impending release we should
revert the change for now. With that noted:
Lokesh Vutla [Tue, 31 Dec 2019 10:19:55 +0000 (15:49 +0530)]
arm: mach-k3: Enable WA for R5F deadlock
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
cacheable write back/write allocate memory region and later
on software execute barrier operation (DSB or DMB). R5F may
hang at the barrier instruction.
2.When software is performing a mix of load and store operations
within a tight loop and store operations are all writing to
cacheable write back/write allocates memory regions, R5F may
hang at one of the load instruction.
To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.
Lokesh Vutla [Tue, 31 Dec 2019 10:18:48 +0000 (15:48 +0530)]
arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
include/u-boot/crc.h: pull 'uint' definition on musl targets
The build failure was originally reported on arm64-musl
target at https://bugs.gentoo.org/703132. Here is the amd64-musl
variant:
```
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-only_defconfig -j$(nproc)
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-all -j$(nproc)
...
include/u-boot/crc.h:37:44: error: unknown type name 'uint'; did you mean 'int'?
37 | void crc16_ccitt_wd_buf(const uint8_t *in, uint len,
| ^~~~
| int
```
Note: 'uint' is not defined there.
On glibc 'uint' comes from <sys/types.h> and happens to work on most .c files.
The change imports 'uint' declaration from '<compiler.h>'.
Bug: https://bugs.gentoo.org/703132 Signed-off-by: Sergei Trofimovich <slyfox@gentoo.org>
The build failure was originally reported on arm64-musl
target at https://bugs.gentoo.org/703132. Here is the amd64-musl
variant:
```
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-only_defconfig -j$(nproc)
$ LANG=C make CROSS_COMPILE=x86_64-gentoo-linux-musl- tools-all -j$(nproc)
...
In file included from tools/env/../../env/flags.c:7,
from tools/env/env_flags.c:1:
include/env.h:159:1: error: unknown type name 'ulong'; did you mean 'long'?
159 | ulong env_get_ulong(const char *name, int base, ulong default_val);
| ^~~~~
| long
```
Note: 'ulong' is not defined there.
On glibc 'ulong' comes from <sys/types.h>:
```c
/* Old compatibility names for C types. */
typedef unsigned long int ulong;
```
On musl it comes from <sys/types.h> as well but from under different guards:
```c
typedef unsigned long u_long, ulong;
```
The change inlines 'ulong' define similar to 'uint' define.
Bug: https://bugs.gentoo.org/703132 Signed-off-by: Sergei Trofimovich <slyfox@gentoo.org>
Tom Rini [Thu, 2 Jan 2020 15:28:26 +0000 (10:28 -0500)]
Merge tag 'u-boot-rockchip-20191231' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix latest mainline kernel for rk3308
- Update rk3288-evb config to suport OP-TEE
- Fix for firefly-px30 DEBUG_UART channel and make it standalone
- Script make_fit_atf add python3 support
- Fix rk3328 timer with correct COUNTER_FREQUENCY
- Fix rk3328 ATF support with enable spl-fifo-mode
Stephen Warren [Wed, 18 Dec 2019 18:37:21 +0000 (11:37 -0700)]
test_env: don't strip() printenv results
get_env() was originally written to strip() the output of printenv to
isolate the test from any whitespace changes in printenv's output.
However, this throws away any whitespace in the variable value, which can
cause issues when test code expects to see that whitespace. In fact,
printenv never adds any whitespace at all, so there's no need to strip.
The strip causes a practical problem for test_env_echo_exists() if
state_test_env.get_existent_var() happens to choose a U-Boot variable that
contains trailing whitespace. This is true for variable boot_targets.
With Python 2, get_existent_var() never returned boot_targets so this
issue never caused a practical problem.
With Python 3, get_existent_var does sometimes return boot_targets, no
doubt due to Python 3's different dict hash key order implementation,
about 0.5-2% of the time, so this test appears intermittent. With the
strip removed, this intermittency is solved, since the test passes for all
possible U-Boot variables.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Patrik Dahlström [Sat, 21 Dec 2019 16:18:22 +0000 (17:18 +0100)]
omap3_beagle: Change NAND ECC scheme back to OMAP_ECC_HAM1_CODE_HW
The omap3_beagle NAND ECC scheme was changed in 4b37928d357 for unknown
reasons, leading to uncorrectible ecc errors. This commit changes it
back to what it was before.
Adam Ford [Sun, 3 Nov 2019 13:58:40 +0000 (07:58 -0600)]
ARM: imx6q_logic: Cleanup boot sequence check
The board_boot_order() function currenly assumes that the boot source
is MMC/eMMC, but this isn't true for the NAND devices.
This patch cleans up board_boot_order() to check for NAND, SD, ESD,
MMC or EMMC. Anything beyond these are not supported, so it will
default back to the serial downloader if any of those devices are not
available.
Fixes: 9fb50c68daa6 ("ARM: imx6q_logic: Fix MMC2 booting") Signed-off-by: Adam Ford <aford173@gmail.com>
Jagan Teki [Sat, 21 Dec 2019 07:54:30 +0000 (13:24 +0530)]
spi: rk: Limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.
Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.
This change fixed two different read issues,
1. sf read failure when with > 0x10000
2. Boot from SPI flash failed during spi_flash_read call in
common/spl/spl_spi.c
Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.
Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
When compile the curren mainline linux kernel(Linux 5.5-rc3)
with defconfig, the final Image is 29M, it's much
larger than Linux 5.4.
On the current u-boot side on rk3308, the gap between
kernel and fdt is 25M, the fdt will overwrite kernel
Image, so move ftd to a higher memory to give 34M
gab for them.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thomas Hebb [Sat, 21 Dec 2019 02:05:22 +0000 (18:05 -0800)]
rockchip: add description for TPL_ROCKCHIP_COMMON_BOARD
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but
this one doesn't for some reason. Add a description to make the menu
easier to read.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 13 Dec 2019 09:41:17 +0000 (17:41 +0800)]
rockchip: px30-firefly add standalone dts
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot
proper will use the dts setting to do the IOMUX init, and a separate dts
is needed for px30-firefly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jack Mitchell [Tue, 10 Dec 2019 13:07:21 +0000 (13:07 +0000)]
rockchip: make_fit_atf: explicitly use python3
On a distribution with no python2 installed and no
python->python3 symlink the script will fail to execute.
Specify python3 explicitly as it's already a requirement
to build u-boot.
Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Roger Quadros [Wed, 6 Nov 2019 14:21:17 +0000 (16:21 +0200)]
phy: ti-pipe3: improve DPLL stability for SATA & USB
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.
For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.
Roger Quadros [Wed, 6 Nov 2019 14:21:15 +0000 (16:21 +0200)]
phy: ti-pipe3: Use TRM recommended settings for SATA DPLL
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.
Kever Yang [Thu, 5 Dec 2019 10:11:55 +0000 (18:11 +0800)]
rockchip: rk3288-evb: update config to support OPTEE
Upstream kernel and rockchip kernel has default enable PSCI which needs
OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT
option to pack OPTEE with U-Boot proper.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc
sending CMD16 for 'uboot' loadables binary because this step need a
large stack cost(about 0x2d00).
Kever Yang [Thu, 5 Dec 2019 10:11:52 +0000 (18:11 +0800)]
rockchip: fit_spl_optee: get text and optee base from build
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x60000000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface
type cases.
Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
usb: cdns3: ep0: Fix build warnings related to cache ops
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
fw_setenv: avoid writing environment when nothing has changed
In the case where one deletes an already-non-existing variable, or sets
a variable to the value it already has, there is no point in writing the
environment back, thus reducing wear on the underlying storage
device.
In the case of redundant environments, if the two environments
differ (e.g. because one is corrupt), make sure that any call of
fw_setenv causes the two to become synchronized, even if the fw_setenv
call does not change anything in the good copy.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean [Thu, 19 Dec 2019 12:35:37 +0000 (14:35 +0200)]
drivers: net: bcm-sf2: pass -1 to phy_connect()
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in
the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or
is scanning the bus, passing -1 here should keep it functional either way.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Cc: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 18 Dec 2019 06:48:50 +0000 (07:48 +0100)]
net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYs
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:
CC arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Remove __packed attribute from struct sunxi_prcm_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Diego Rondini [Tue, 19 Nov 2019 13:43:33 +0000 (14:43 +0100)]
sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2
Orangepi Zero Plus 2 is an open-source single-board computer, available
in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
here, as the H5 is already supported.
H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~
Use memcpy() and void* pointers to resolve the problem caused by packing
the struct sunxi_cpucfg_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
projects / u-boot.git / log