Sergei Antonov [Wed, 18 Jan 2023 17:52:18 +0000 (20:52 +0300)]
net: ipv6: fix alignment errors on ARM
Commands "ping6" and "tftpboot ... -ipv6" did not work on ARM because
machine code expects 4-byte alignment and some structures from net6.h
are not aligned in memory.
Fix by adding __packed, since it is already used in this file.
Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Viacheslav Mitrofanov <v.v.mitrofanov@yadro.com>
Ehsan Mohandesi [Fri, 13 Jan 2023 17:27:41 +0000 (09:27 -0800)]
net: ipv6: Fixed IPv6 string to address conversion off-by-one error
One extra character was being checked in the IPv6 string which caused the
last character of the address to be neither '\0' nor ':'. This raises an
error condition and causes the function to always return an error. This
issue was resolved by this fix.
Ioana Ciornei [Thu, 5 Jan 2023 15:03:19 +0000 (17:03 +0200)]
drivers: net: fsl-mc: remove explicit cast
Remove all the explicit casts from the void* returned by calloc.
With this we also improve a bit the length of those lines and there is
no need to split the assignment.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ioana Ciornei [Thu, 5 Jan 2023 15:03:17 +0000 (17:03 +0200)]
drivers: net: fsl-mc: do not prefix decimal values with 0x
The fsl-mc driver printed debug information which used the 0x prefix for
decimal values. This only confuses anyone looking through the log.
Because of this, just remove the prefix and use the "DPXY.<id>" notation
which is the standard one for the DPAA2 objects.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Sean Edmond [Thu, 5 Jan 2023 02:16:26 +0000 (18:16 -0800)]
net: tftp: Fix for DATA ACK for block count out of order
In rfc7440, if an ACK is not received by the server or if the
last data block in a window is dropped, the server will timeout and
retransmit the window. In this case, the block count received will be
less than the internal block count. In this case, the client
should not ACK. ACK should only be sent if the received block
count is greater than the expected block count.
Signed-off-by: Sean Edmond <seanedmond@linux.microsoft.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Tim Harvey [Wed, 30 Nov 2022 17:42:51 +0000 (09:42 -0800)]
board: gw_ventana: enable MV88E61XX DSA support
Add MV88E61XX DSA support:
- update dt to provide internal MDIO bus and port handles.
U-Boot requires a more restrictive subset of the dt bindings
required by Linux for the sake of simplifying code
- update defconfig to remove old driver and enable new one
- replace mv88e61xx_hw_reset weak override with board_phy_config support
for register configuration that is outside the scope of the DSA driver
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tim Harvey [Wed, 30 Nov 2022 17:42:50 +0000 (09:42 -0800)]
net: add MV88E6xxx DSA driver
Add a DSA driver for the MV88E6xxx compatible Ethernet switches.
Cc: Marek Behún <marek.behun@nic.cz> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Tim Harvey [Wed, 30 Nov 2022 17:42:49 +0000 (09:42 -0800)]
net: fec: add support for DM_MDIO
Add support for DM_MDIO by registering a UCLASS_MDIO driver and
attempting to use it. This is necessary if wanting to use a DSA
driver for example hanging off of the FEC MAC.
Care is taken to fallback to non DM_MDIO mii bus as several boards define
DM_MDIO without having the proper device-tree configuration necessary
such as an mdio subnode, a phy-mode prop, and either a valid phy-handle
prop or fixed-phy subnode which will cause dm_eth_phy_connect() to fail.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Tim Harvey [Wed, 30 Nov 2022 17:42:47 +0000 (09:42 -0800)]
net: dsa: allow rcv() and xmit() to be optional
Allow rcv() and xmit() dsa driver ops to be optional in case a driver
does not care to mangle a packet as in U-Boot only one network port is
enabled at a time and thus no packet mangling is necessary.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Enable TIMER and TEGRA_TIMER for TEGRA_ARMV7_COMMON and TEGRA210.
Additionally enable SPL_TIMER if build as SPL part and drop
deprecated configs from common header.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
drivers: timer: add driver for ARMv7 based Tegra devices and T210
Add timer support for T20/T30/T114/T124 and T210 based devices.
Driver is based on DM, has device tree support and can be
used on SPL and early boot stage.
Arm64 Tegra (apart T210) according to comment in tegra-common.h use
architected timer.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
Marek Vasut [Thu, 26 Jan 2023 20:10:48 +0000 (21:10 +0100)]
net: ravb: Drop SoC-specific compatible support
The current set of U-Boot upstream R-Car Gen3 DTs all contain generic
"renesas,etheravb-rcar-gen3" compatible strings, drop the SoC specific
compatible string support from U-Boot to reduce size and duplication.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Mon, 23 Jan 2023 00:24:09 +0000 (01:24 +0100)]
configs: draak: Enable I2C support for R-Car D3
Enable I2C support on D3 Draak.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Thu, 26 Jan 2023 20:06:07 +0000 (21:06 +0100)]
clk: renesas: rcar-gen3: Factor out CPG library
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock and RPC clock handling and hook them to the generic Gen3
CPG driver so we have an equal state.
Based on Linux commit [1] and [2] by Wolfram Sang
[1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library")
[2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to
the library")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
- Use u32_encode_bits/GENMASK bitfield ops
Hai Pham [Thu, 26 Jan 2023 20:06:06 +0000 (21:06 +0100)]
clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.
Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
which is now part of common clock types in rcar-gen3-cpg.h instead
Hai Pham [Sun, 29 Jan 2023 01:50:22 +0000 (02:50 +0100)]
clk: renesas: Switch to new SD clock handling
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.
Based on Linux series by Wolfram Sang, commit bb6d3fa98a41 ("clk:
renesas: rcar-gen3: Switch to new SD clock handling") and commit e5f7e81ee430a ("mmc: renesas_sdhi: Parse DT for SDnH")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Add rcar_clk_* prefix to all functions
- Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Use DIV_ROUND_CLOSEST, else if parent clock = 199999992 and
rate = 200000000, the divider would be 0 and table lookup
would fail.
- Turn rcar_clk_get_table_val into signed integer, so it can
return 0 as a valid value and negative values as errors.
- Make the code operate on correct clock and add comment
which explains the reasoning behind it.
- Rebase on changes to
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
Hai Pham [Thu, 26 Jan 2023 20:06:04 +0000 (21:06 +0100)]
clk: renesas: Handle E3/D3 RPCSRC clock
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.
As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.
Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Add D3 tweaks
Hai Pham [Thu, 26 Jan 2023 20:06:03 +0000 (21:06 +0100)]
clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function
Introduce new helper function to handle clock type that uses
clk_div_table struct. Based vaguely on Linux code. Make use
of clk_div_table in RPC clocks handling.
The E3/D3 RPCSRC need to be handled differently and will be addressed in
subsequence patch.
Based on Linux commit db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC
clocks") by Sergei Shtylyov.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Squash patches to avoid adding unused code:
clk: renesas: Make use of clk_div_table in RPC clocks handling
clk: renesas: Introduce rcar_clk_get_rate64_div_table function
- Move the new code to the beginning of clk-rcar-gen3 to avoid
tables mixed with code
- Use rcar_ prefix for get_table_div function
- Get rid of custom macros, use GENMASK. Use custom field_get
implementation as the generic FIELD_GET does not support
constant mask and u32_get_bits requires higher optimization level
- Pass in the register bit mask instead of width/shift combination
- Turn rcar_clk_get_rate64_div_table into s64, as it can return -EINVAL
Hai Pham [Thu, 26 Jan 2023 20:05:55 +0000 (21:05 +0100)]
mmc: renesas-sdhi: R-Car M3 r1.3 also uses 4 tuning taps
Early ES revisions of M3-W SoCs requires 4-tap HS400. Reflect the status
from datasheet.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Thu, 26 Jan 2023 20:02:05 +0000 (21:02 +0100)]
clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg
Drop 'core' parameter from gen3_clk_get_rate64_pll_mul_reg() function
as it is only used in debug print. No functional change except for the
debug print, which is disabled by default.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Thu, 26 Jan 2023 20:02:04 +0000 (21:02 +0100)]
clk: renesas: Use pre-defined offset for RPC clocks
Since commit f7b4e4c0949f ("clk: renesas: Synchronize R-Car Gen3 tables
with Linux 5.12"), the custom macros for RPC clocks were dropped.
Use pre-defined offset for RPC clocks, same as what Linux does, instead
of retrieving it from the macros
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Thu, 26 Jan 2023 20:02:03 +0000 (21:02 +0100)]
clk: renesas: Add and enable CPG reset driver
Add trivial reset driver extension to the CPG clock driver. The change
turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy
driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock
driver as well as generic rcar_rst UCLASS_RESET reset driver to the
CPG DT node. This way, any other drivers which use the 'reset' DT
property can now obtain valid reset handle backed by a reset driver.
The clock tables have been updated to represent the CPG driver and only
implement the generic CPG proxy driver bind call, which binds the clock
and reset drivers.
The DM_RESET is now enabled for all R-Car Gen3 platforms.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Thu, 26 Jan 2023 20:02:02 +0000 (21:02 +0100)]
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
Add support for the R-Car M3-W+ (R8A77961) SoC.
R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for
both SoCs to share a driver.
Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961
CPG/MSSR support")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Thu, 26 Jan 2023 20:02:01 +0000 (21:02 +0100)]
clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_CLK_R8A77961.
Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796
to CLK_R8A77960")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new
clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and
CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Hai Pham [Thu, 26 Jan 2023 20:01:49 +0000 (21:01 +0100)]
clk: renesas: Add dummy SDnH clock
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.
Based on Linux series by Wolfram Sang:
commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"),
commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"),
commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Switch to gen3_clk_get_rate64
Hai Pham [Thu, 26 Jan 2023 20:01:48 +0000 (21:01 +0100)]
pinctrl: renesas: r8a7796: Add R8A77961 PFC support
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960),
which allows for both SoCs to share a driver.
Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add
R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796:
Optimize pinctrl image size for R8A774A1")
Parts picked from
pinctrl: renesas: Synchronize R-Car Gen2/Gen3 tables with Linux 5.18.3
- Add pin groups for the green and high8 subsets of the Video IN pins
- Add MediaLB pins
- Add bias support for various SoCs
- Share more pin group data, to reduce size and ease review
- Miscellaneous cleanups, fixes and improvements.
This contains port of Linux kernel commit 6210905586ae ("pinctrl: renesas: Add shorthand for reserved register fields")
to handle negative entries in GROUP() macros correctly.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This is only a copyright and SPDX identifier update, no
functional change.
The following script has been used for the synchronization:
$ for i in $(cd include/dt-bindings/clock/ ; ls -1 r8a*) ; do cp /linux-2.6/include/dt-bindings/clock/$i include/dt-bindings/clock/ ; done
$ for i in $(cd include/dt-bindings/power/ ; ls -1 r8a*) ; do cp /linux-2.6/include/dt-bindings/power/$i include/dt-bindings/power/ ; done
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Aurelien Jarno [Sat, 7 Jan 2023 22:32:39 +0000 (23:32 +0100)]
board: sifive: unmatched: enable booting on a second NVME device
The HiFive Unmatched board has a M2 slot for NVME and a PCIe slot that
can also be used for NVME. Enable support for a second NVME device, so
that software RAID-1 configurations can be supported at the u-boot
level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Rick Chen [Wed, 4 Jan 2023 02:37:48 +0000 (10:37 +0800)]
riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC
Original OpenSBI (without FW_PIC) will relocate itself
from 0x1000000 to 0x0. After OpenSBI added FW_PIC codes,
it will not relocate any more and always run at 0x1000000.
Hence, it may overlap with Kernel memory region. So it is
necessary to change OpenSBI address from 0x1000000 to 0x0.
More details can refer to commit cb052d771200
("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng@tinylab.org>
Rick Chen [Wed, 4 Jan 2023 01:55:43 +0000 (09:55 +0800)]
riscv: ax25: bypass malloc when spl fit boots from ram
When fit image boots from ram, the payload will
be prepared in the address of SPL_LOAD_FIT_ADDRESS.
In spl fit generic flow, it will malloc another
memory address and copy whole fit image to this
malloc address. But it is un-necessary for booting
from RAM.
This patch improves this flow by declare the
board_spl_fit_buffer_addr() to replace the original one.
The larger image size (eq: Kernel Image 10~20MB), it
can save more booting time.
Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Rick Chen [Tue, 3 Jan 2023 08:17:13 +0000 (16:17 +0800)]
riscv: ae350: Enable CCTL_SUEN
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Mario Kicherer [Wed, 1 Feb 2023 06:16:22 +0000 (14:16 +0800)]
armv7: ls102xa: make QSPI clock selection optional during SoC init
To improve startup times when booting from QSPI flash, the QSPI frequency
can be configured very early in the boot process [1] to reduce loading
times of U-Boot itself. This patch adds an option to disable setting the
frequency to a default value during SoC initialization.
Manoj Sai [Mon, 28 Nov 2022 11:45:31 +0000 (17:15 +0530)]
configs: imx8mp_evk: revert to old ram settings
The 'commit 864ac2cf383e ("board: imx8mp: Add Engicam
i.Core MX8M Plus EDIMM2.2 Starter Kit")' has changed the imx8mp evk ram
settings from 6GB ram to 2GB.
This changeset reverts the above change.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reported-by : Peter Bergin <peter@berginkonsult.se> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Arnaud Ferraris [Thu, 15 Dec 2022 14:51:17 +0000 (15:51 +0100)]
imx8mq_pins: fix configuration for UART4 on ECSPI2 pads
When routing UART4 using the ECSPI2 pads, register
IOMUXC_UART4_RXD_SELECT_INPUT (offset 0x050C) should be changed only
when dealing with RX, as its name suggests.
Ye Li [Tue, 13 Dec 2022 04:08:02 +0000 (05:08 +0100)]
imx8: scu_api: sync sc_rm_is_pad_owned api change
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This
requires u-boot to update API implementation, since it will cause
compatible issue. Otherwise all pad checking will have problem and
cause pad setting not continue.
Due to the compatible issue, the new u-boot only works with new
SCFW (API version: 1.21 and later).
old scfw + old u-boot: API overflow issue
old scfw + new u-boot, or new scfw + old u-boot: API compatible issue
new scfw + new u-boot: Working
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Adam Ford [Sat, 19 Nov 2022 19:30:08 +0000 (13:30 -0600)]
configs: imx8mn_beacon_fspi: Add config for booting from QSPI
The imx8mn-beacon SOM has a QSPI part on it connected to the
FlexSPI controller. Add a defconfig option which supports
booting from the QSPI NOR flash instead of sd/mmc.
projects / u-boot.git / log