Wolfgang Denk [Sat, 11 Feb 2012 21:14:56 +0000 (22:14 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
nand/fsl_elbc: Convert to self-init
nand: Introduce CONFIG_SYS_NAND_SELF_INIT
nand_spl: store ecc data on the stack
mtd/nand: Add ONFI support for FSL NAND controller
nand: make 1-bit software ECC configurable
nand: Sanitize ONFI strings.
nand: Merge changes to BBT from Linux nand driver
nand: Merge changes from Linux nand driver
nand: cleanup whitespace
nand: Add more NAND types from Linux nand driver
nand: Merge BCH code from Linux nand driver
NAND: Remove additional (CONFIG_SYS)_NAND_MAX_CHIPS
NAND: remove NAND_MAX_CHIPS definitions
nand_spl_simple: store ecc data on the stack
Wolfgang Denk [Sat, 11 Feb 2012 21:07:48 +0000 (22:07 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash:
nand/fsl_elbc: Convert to self-init
nand: Introduce CONFIG_SYS_NAND_SELF_INIT
nand_spl: store ecc data on the stack
mtd/nand: Add ONFI support for FSL NAND controller
nand: make 1-bit software ECC configurable
nand: Sanitize ONFI strings.
nand: Merge changes to BBT from Linux nand driver
nand: Merge changes from Linux nand driver
nand: cleanup whitespace
nand: Add more NAND types from Linux nand driver
nand: Merge BCH code from Linux nand driver
NAND: Remove additional (CONFIG_SYS)_NAND_MAX_CHIPS
NAND: remove NAND_MAX_CHIPS definitions
nand_spl_simple: store ecc data on the stack
Wolfgang Denk [Sat, 11 Feb 2012 21:05:13 +0000 (22:05 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
ARM: AM33XX: Add i2c support
ARM: AM33XX: Add AM33XX I2C driver support
ARM: I2C: I2C Multi byte address support
* Fix: watchdog timed out, if flash blank (0xFF) blocks
The current implementation of cfi_flash uses udelay to reset watchdog.
If several blocks are blank (0xff filled) the watchdog timed out.
The reason is, udelay is never called, if flash device is ready to fast.
e.g.
mw.w $(copy_addr) FFFF 10000;cp.b $(copy_addr) 10880000 20000
Scott Wood [Fri, 13 Jan 2012 01:42:58 +0000 (19:42 -0600)]
nand/fsl_elbc: Convert to self-init
This driver doesn't yet make use of the added flexibility (not that that
should stop anyone from converting...), but it will with the in-progress
hack to support 4k-page NAND.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Scott Wood [Fri, 13 Jan 2012 01:07:23 +0000 (19:07 -0600)]
nand: Introduce CONFIG_SYS_NAND_SELF_INIT
This allows a driver to run code between nand_scan_ident() and
nand_scan_tail(), among other things. See the additions to
doc/README.nand for details.
To allow a gradual transition, Boards that don't set
CONFIG_SYS_NAND_SELF_INIT will still be initialized the old way, but
new drivers should not require this, and existing drivers should be
converted when convenient.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing
the fixed address in RAM.
Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Ilya Yanok <yanok@emcraft.com> CC: Scott Wood <scottwood@freescale.com> CC: Tom Rini <tom.rini@gmail.com> CC: Simon Schwarz <simonschwarzcor@googlemail.com> CC: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
While nand_spl is on its way out, in favor of spl, there are still
many boards using it, and conversions are gradual. This allows us
to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now,
which would otherwise be likely to linger unreferenced after a conversion.
It also eliminates a temporary error in the hawkboard_nand build, since
the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but
the spl conversion is pending (and may be merged via a different tree).
Signed-off-by: Scott Wood <scottwood@freescale.com>
Christian Hitz [Wed, 12 Oct 2011 07:32:06 +0000 (09:32 +0200)]
nand: make 1-bit software ECC configurable
The software ECC algorithm is not necessary when hardware ECC
is available and can be left out for a smaller image size.
Enable with CONFIG_MTD_ECC_SOFT.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch synchronizes the nand driver with the Linux 3.0 state.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com> Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: minor fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch merges the BCH ECC algorithm from the 3.0 Linux kernel.
This enables U-Boot to support modern NAND flash chips that
require more than 1-bit of ECC in software.
Signed-off-by: Christian Hitz <christian.hitz@aizo.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
This change follows the change by Wolfgang Grandegger (commit 6c869637fef),
which allows to remove useless NAND_MAX_CHIPS definitions in board config
files.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Wolfgang Grandegger <wg@grandegger.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefano Babic [Thu, 15 Dec 2011 09:55:37 +0000 (10:55 +0100)]
nand_spl_simple: store ecc data on the stack
Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing
the fixed address in RAM.
Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Ilya Yanok <yanok@emcraft.com> CC: Scott Wood <scottwood@freescale.com> CC: Tom Rini <tom.rini@gmail.com> CC: Simon Schwarz <simonschwarzcor@googlemail.com> CC: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
Andreas Müller [Wed, 4 Jan 2012 15:26:25 +0000 (15:26 +0000)]
overo: add SPL support
* implementation based on ti beagleboard/omap3evm
* timing data and i2c workaround for revision 0 boards taken from x-loader
* run-tested with overo revision 0 and 1 / boot from NAND and SDcard
* run-tested with x-loader
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
Andreas Müller [Wed, 4 Jan 2012 15:26:22 +0000 (15:26 +0000)]
drivers/i2c/omap24xx_i2c.c: move all local variables to SRAM
At old overo boards TWL4030 RTC irq is connected to gpio112. Unfortunately
this pin is also used for revision detection. Therefore we need to send
shut-up to TWL4030 to avoid reading wrong revision. In SPL this must
be done before SDRAM is set up because the type of SDRAM is revision dependent.
By this patch it is ensured that all variables used by omap24xx_i2c.c are
located in SRAM.
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
Chandan Nath [Mon, 9 Jan 2012 20:38:59 +0000 (20:38 +0000)]
ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Nikita Kiryanov [Thu, 5 Jan 2012 02:03:22 +0000 (02:03 +0000)]
omap3: make get_board_rev() function weak
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this function
weak.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Nikita Kiryanov [Mon, 2 Jan 2012 04:01:31 +0000 (04:01 +0000)]
cm-t35: various cleanups
Move #ifdef CONFIG_SMC911X out of board_eth_init() function,
simplify the board_mmc_init() function, and enclose handle_mac_address()
in the CONFIG_SMC911X.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Peter Barada [Mon, 19 Dec 2011 19:54:51 +0000 (19:54 +0000)]
ARMV7: Add support For Logic OMAP35x/DM37x modules
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Christian Riesch [Thu, 15 Dec 2011 00:33:21 +0000 (00:33 +0000)]
da850evm: Remove CONFIG_SYS_xxCACHE_OFF defines
This patch removes the defines CONFIG_SYS_ICACHE_OFF,
CONFIG_SYS_DCACHE_OFF, and CONFIG_SYS_L2CACHE_OFF from the board
configuration. These defines are useless since cache is
anyway disabled for the entire architecture since commit cba4b1809f043bf85c806e5a4e342f62bd5ded45.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com>
Christian Riesch [Thu, 15 Dec 2011 06:21:55 +0000 (06:21 +0000)]
arm, davinci: Use a common configuration file for da850evm and da850_am18xxevm
In commit 06194b6b65f701a9d6ef2d9b4123c4afe57d8783 a separate header
file was introduced for the AM1808 EVM, include/configs/da850_am18xxevm.h.
Before this commit, the da850evm.h configuration file was used for both
the AM1808 and the OMAP-L138 EVMs. The only substantial difference
between the da850evm and the da850_am18xxevm configuration is a single
bit in the hardware revision that is passed to the Linux kernel.
This patch removes include/configs/da850_am18xxevm.h. Instead the
include/configs/da850evm.h configuration is used for AM18xx EVMs and
CONFIG_DA850_AM18X_EVM is defined in boards.cfg.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com>
Zach Sadecki [Mon, 9 Jan 2012 10:22:54 +0000 (10:22 +0000)]
mx28: fix clearing of IRQs in power init
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear. Using the correct method to clear the IRQs fixes it.
Signed-off-by: Zach Sadecki <zach@itwatchdogs.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marek.vasut@gmail.com>
Wolfgang Denk [Fri, 13 Jan 2012 19:39:33 +0000 (20:39 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
fsl_lbc: add printout of LCRR and LBCR to local bus regs
sbc8548: Fix up local bus init to be frequency aware
sbc8548: enable support for hardware SPD errata workaround
sbc8548: relocate fixed ddr init code to ddr.c file
sbc8548: Make enabling SPD RAM configuration work
sbc8548: Fix LBC SDRAM initialization settings
sbc8548: enable ability to boot from alternate flash
sbc8548: relocate 64MB user flash to sane boundary
Revert "SBC8548: fix address mask to allow 64M flash"
MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
eXMeritus HWW-1U-1A: Minor environment variable tweaks
Wolfgang Denk [Fri, 13 Jan 2012 19:38:49 +0000 (20:38 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
fsl_lbc: add printout of LCRR and LBCR to local bus regs
sbc8548: Fix up local bus init to be frequency aware
sbc8548: enable support for hardware SPD errata workaround
sbc8548: relocate fixed ddr init code to ddr.c file
sbc8548: Make enabling SPD RAM configuration work
sbc8548: Fix LBC SDRAM initialization settings
sbc8548: enable ability to boot from alternate flash
sbc8548: relocate 64MB user flash to sane boundary
Revert "SBC8548: fix address mask to allow 64M flash"
MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
eXMeritus HWW-1U-1A: Minor environment variable tweaks
Wolfgang Denk [Fri, 13 Jan 2012 19:11:25 +0000 (20:11 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
board/mpl/pati: use the CFI driver for the PATI board
board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
board/mpl/pip405: use the CFI driver for the PIP405 board
board/mpl/common: remove the old legacy flash
ppc4xx: Setup HICB on Io64
Wolfgang Denk [Fri, 13 Jan 2012 19:11:22 +0000 (20:11 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
* 'master' of git://git.denx.de/u-boot-ppc4xx:
board/mpl/pati: use the CFI driver for the PATI board
board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
board/mpl/pip405: use the CFI driver for the PIP405 board
board/mpl/common: remove the old legacy flash
ppc4xx: Setup HICB on Io64
Wolfgang Denk [Fri, 13 Jan 2012 19:10:56 +0000 (20:10 +0100)]
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
mpc8313erdb: fix mtdparts address
powerpc/83xx/km: add support for 8321 based tuge1 board
powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
powerpc/83xx/km: remove obsolete defines for tuda1
powerpc/83xx/km: update SDRAM parameters for km8321 boards
mpc8313erdb: Enable GPIO support on the MPC8313E RDB
mpc83xx: Add a GPIO driver for the MPC83XX family
gpio: Replace ARM gpio.h with the common API in include/asm-generic
gpio: Modify common gpio.h to more closely match Linux
Wolfgang Denk [Fri, 13 Jan 2012 19:07:40 +0000 (20:07 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
mpc8313erdb: fix mtdparts address
powerpc/83xx/km: add support for 8321 based tuge1 board
powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
powerpc/83xx/km: remove obsolete defines for tuda1
powerpc/83xx/km: update SDRAM parameters for km8321 boards
mpc8313erdb: Enable GPIO support on the MPC8313E RDB
mpc83xx: Add a GPIO driver for the MPC83XX family
gpio: Replace ARM gpio.h with the common API in include/asm-generic
gpio: Modify common gpio.h to more closely match Linux
Paul Gortmaker [Sat, 31 Dec 2011 04:53:13 +0000 (23:53 -0500)]
sbc8548: Fix up local bus init to be frequency aware
The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit. Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv. Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.
This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to
Keith Savage for assistance in diagnosing the root cause of this.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Sat, 31 Dec 2011 04:53:12 +0000 (23:53 -0500)]
sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.
After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53. So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.
Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Sat, 31 Dec 2011 04:53:10 +0000 (23:53 -0500)]
sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on
this board. Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.
We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled. We can revisit this dependency as the
hardware workaround becomes available.
Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.
This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.
The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs. But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Sat, 31 Dec 2011 04:53:09 +0000 (23:53 -0500)]
sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size). Set the values
by comparing to the register file for the board used during
JTAG init sequence:
This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.
The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Sat, 31 Dec 2011 04:53:08 +0000 (23:53 -0500)]
sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Sat, 31 Dec 2011 04:53:07 +0000 (23:53 -0500)]
sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM. But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.
This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)
We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.
In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping. Plus we
can toss out a TLB entry.
Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device. The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:
Paul Gortmaker [Fri, 16 Dec 2011 22:31:53 +0000 (17:31 -0500)]
MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
These boards were meaning to deploy this value:
#define LCRR_DBYP 0x80000000
but were missing a zero, and hence toggling a bit that
lands in an area marked as reserved in the 8548 reference
manual.
According to the documentation, LCRR_DBYP should be used as:
PLL bypass. This bit should be set when using low bus
clock frequencies if the PLL is unable to lock. When in
PLL bypass mode, incoming data is captured in the middle
of the bus clock cycle. It is recommended that PLL bypass
mode be used at frequencies of 83 MHz or less.
So the impact would most likely be undefined behaviour for
LBC peripherals on boards that were running below 83MHz LBC.
Looking at the actual u-boot code, the missing DBYP bit was
meant to be deployed as follows:
Between 66 and 133, the DLL is enabled with an
override workaround.
In the future, we'll convert all boards to use the symbolic
DBYP constant to avoid these "count the zeros" problems, but
for now, just fix the impacted boards.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kyle Moffett [Fri, 16 Dec 2011 03:26:52 +0000 (22:26 -0500)]
eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
This EEPROM is hardware-write-protected and used to persist key
information such as the serial number and MAC addresses even if the
primary environment sector in NOR FLASH is overwritten.
During manufacturing, the environment is initialized from Linux and then
the key parameters copied to the EEPROM via U-Boot:
The chip is then locked via hardware for delivery.
When doing a field U-Boot upgrade, the environment is erased and reset
to the defaults to avoid problems with "hwconfig" changes, etc. After
loading the new U-Boot image, the hardware data is reloaded:
projects / u-boot.git / log