Jagan Teki [Mon, 15 Jul 2019 18:28:56 +0000 (23:58 +0530)]
rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:44 +0000 (17:27 +0530)]
rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:40 +0000 (17:27 +0530)]
ram: rk3399: Add lpddr4 set rate support
Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.
The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.
Here is sameple log about LPDDR4-100 init sequence in Rockpro64:
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0
This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:39 +0000 (17:27 +0530)]
ram: rk3399: Add set_rate sdram rk3399 ops
DDR set rate can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.
For this requirement, and for code readability handle
data training via sdram_rk3399_ops with .set_rate and
same will update in future while supporting lpddr4 code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:38 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDDR4-800 timings inc
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:37 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDDR4-400 timings inc
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-400 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:31 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDR4 mr detection
Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.
Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.
So, add code to support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:29 +0000 (17:27 +0530)]
ram: rk3399: Simplify data training first argument
data training is using chan_info as first argument with
channel number as second argument instead of that use
dram_info as first argument so-that we can get the
chan_info at data training definition.
This was the argument handling is meaningful, readable
and it would help to add similar data training for
lpddr4 in future.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:21 +0000 (17:27 +0530)]
ram: rk3399: Add IO settings
Add IO settings for dram ctl and phy.
IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.
Right now, this patch added IO setting for all supported
sdram frequencies.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:01 +0000 (17:27 +0530)]
ram: rk3399: Introduce sys_reg3 for more capacity info
cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:56:49 +0000 (17:26 +0530)]
ram: rk3399: Simply existing dram enc macro
Add simplified and meaningful macro for all setting.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash the similar patches into 1 patch) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:54 +0000 (23:58 +0530)]
ram: rk3399: Add rank detection support
Right now the rk3399 sdram driver assume that the board
has configured with 2 channels, so any possibility to
enable single channel on the same driver will encounter
channel #1 data training failure.
Log:
U-Boot TPL board init
sdram_init: data training failed
rk3399_dmc_init DRAM init failed -5
So, add an algorithm that can capable to compute the active
or configured rank with associated channel like
a) do rank loop to compute the active rank, with associated
channel numbers
b) then, succeed the data training only for configured channel
c) preserve the rank for given channel
d) do channel loop for setting the active channel
e) if given rank is zero or inactive on the specific channel,
clear the timings for the associated channel
f) finally, return error if number of channels is zero
Tested in NanoPI-NEO4 since it support single channel sdram
configuration.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(add PI_READ_GATE_TRAINING for LPDDR3 to support rk3399-evb case) Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:52 +0000 (23:58 +0530)]
ram: rk3399: Compute stride for 2 channels
stride value from sdram timings can be computed dynamically
based on the determined capacity for the given channel.
Right now these stride values are taken as part of sdram timings
via dtsi, but it possible to use same timings dtsi for given
frequency even though the configured board sdram do support
single channel with different size by dynamically detect the
stride value.
Example, NanoPi NEO4 do have DDR3-1866, but with single channel
and 1GB size with dynamic stride detection it is possible to
use existing rk3399-sdram-ddr3-1866.dtsi whose stride,
number of channels and capacity it support is d efferent.
So, add initial support to calculate the stride value for
2 channels sdram, which is available by default on existing
boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:48 +0000 (23:58 +0530)]
ram: rockchip: Add debug sdram driver
Add sdram driver to handle debug across rockchip SoCs.
This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:44 +0000 (23:58 +0530)]
ram: rk3399: Move pwrup_srefresh_exit to dram_info
Add pwrup_srefresh_exit to be part of dram_info so-that
the it can help to support pwrup_srefresh_exit in individual
channels while starting pctl in future.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:42 +0000 (23:58 +0530)]
ram: rk3399: Use rank mask in wdql data training
Add rank_mask based on the rank number, this would keep
the wdql data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:41 +0000 (23:58 +0530)]
ram: rk3399: Use rank mask in ca data training
Add rank_mask based on the rank number, this would keep
the ca data training loop based on the desired rank mask
value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:39 +0000 (23:58 +0530)]
ram: rk3399: Handle data training return types
data trainings calls like ca, wl, rg, rl, wdql have proper
return types with -EIO and the return type missed to handle
in data_training function.
This patch, add proper return type checks along with useful
debug statement on each data training calls.
Incidentally this would help to prevent the sdram initialization
hang for single channel dram and when the code is trying to
initialize second channel with proper return type of relevant
data training call might failed.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:21:10 +0000 (23:51 +0530)]
clk: rockchip: rk3399: Fix check patch warnings and checks
- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements
Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:21:07 +0000 (23:51 +0530)]
ram: rk3399: Move common sdram structures in common header
Move common sdram structures like sdram_cap_info, sdram_base_params
into sdram_common header, this would help to reuse the same
from another controllers like px30.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:20:56 +0000 (23:50 +0530)]
ram: rk3399: Fix code warnings
Fix checkpatch warninigs on sdram_rk3399.c like
- Avoid CamelCase
- Unnecessary parentheses
- Alignment should match open parenthesis
- multiple blank lines
- misspelled
- spaces preferred around that '>>'
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Andy Yan [Thu, 4 Jul 2019 06:52:47 +0000 (14:52 +0800)]
rockchip: dts: rk3399: Add spl-boot-order for Rock PI 4
RK3399 use sdhci for eMMC and DW MMC for SD Card, and
spl will only try to boot from SDMMC if we don't specify
other boot device for spl-boot-order. So add sdhci and sdmmc
for spl-boot-order here.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Mark Kettenis [Sun, 30 Jun 2019 16:01:53 +0000 (18:01 +0200)]
rockchip: clk: rk3399: handle clk_enable requests for USB3
The "simple" OF glue layer for the Designware USB3 core enables
all refernced clocks. These need to be need to be implemented
otherwise the driver fails to probe. A dummy implementation
that simply returns success is sufficient since the RK3399 comes
out of reset with all clock gates open.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Thu, 18 Jul 2019 15:31:37 +0000 (11:31 -0400)]
Merge branch '2019-07-17-master-imports'
- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support.
Removed one of the defconfig(obsoleted) file
and unused CONFIG_MMC_SPI definition to avoid confusion
about if this board using non-DM stuff or not.
uCP1020 is completely DM free board, tested and runs well.
Signed-off-by: Oleksandr Zhadan <oleks@arcturusnetworks.com> Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some storage devices have multiple hw partitions and both address from
zero, for example eMMC.
However currently block cache invalidation only applies to block
write/erase.
This can cause a problem that data of current hw partition is cached
before switching to another hw partition. And the following read
operation of the latter hw partition will get wrong data when reading
from the addresses that have been cached previously.
To solve this problem, invalidate block cache after a successful
select_hwpart operation.
arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi
The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.
This patch reverses these two clocks to solve this issue.
Simon Glass [Wed, 10 Jul 2019 17:04:13 +0000 (11:04 -0600)]
chromium: Update docs to clone vboot_reference directly
We don't need a full checkout of Chrome OS to build U-Boot with
Chromium OS verified boot. Update the instructions accordingly and fix a
typo which joins the output directory and defconfig.
projects / u-boot.git / log