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4 years agoarm: dts: socfpga: arria10: Move to use generic handoff dtsi
Ley Foon Tan [Wed, 8 Jul 2020 08:34:01 +0000 (16:34 +0800)]
arm: dts: socfpga: arria10: Move to use generic handoff dtsi

Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
Dalon Westergreen [Fri, 4 Oct 2019 21:23:48 +0000 (14:23 -0700)]
arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC

Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Dalon Westergreen [Sat, 28 Sep 2019 01:43:24 +0000 (18:43 -0700)]
arm: socfpga: arria10: Add qts-filter for Arria10 socfpga

Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Disable CONFIG_PSCI_RESET
Chee Hong Ang [Fri, 14 Aug 2020 03:07:23 +0000 (11:07 +0800)]
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET

Don't invoke 'SYSTEM_RESET' PSCI function because PSCI
function calls are not supported by u-boot running in EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: mailbox: Add mailbox retry support
Ley Foon Tan [Wed, 12 Aug 2020 01:56:25 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Add mailbox retry support

Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.

Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoarm: socfpga: mailbox: Update mailbox response codes
Ley Foon Tan [Wed, 12 Aug 2020 01:56:24 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Update mailbox response codes

Sync latest mailbox response codes from SDM firmware.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoarm: socfpga: mailbox: Support sending large mailbox command
Chee Hong Ang [Wed, 12 Aug 2020 01:56:23 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Support sending large mailbox command

Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: mailbox: Always read mailbox responses before returning status
Chee Hong Ang [Wed, 12 Aug 2020 01:56:22 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Always read mailbox responses before returning status

Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: mailbox: Refactor mailbox timeout event handling
Chee Hong Ang [Wed, 12 Aug 2020 01:56:21 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Refactor mailbox timeout event handling

Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Document down boot_scratch_cold register usage
Chin Liang See [Mon, 10 Aug 2020 02:55:56 +0000 (10:55 +0800)]
arm: socfpga: soc64: Document down boot_scratch_cold register usage

Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Add timeout waiting for NOC idle ACK
Chee Hong Ang [Mon, 10 Aug 2020 14:59:49 +0000 (22:59 +0800)]
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK

Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoarm: socfpga: agilex: Enable FPGA Full Reconfiguration support
Chee Hong Ang [Fri, 7 Aug 2020 03:50:05 +0000 (11:50 +0800)]
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support

Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agofpga: intel_sdm_mb: Add watchdog reset
Chee Hong Ang [Fri, 7 Aug 2020 03:50:04 +0000 (11:50 +0800)]
fpga: intel_sdm_mb: Add watchdog reset

Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agofpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Chee Hong Ang [Fri, 7 Aug 2020 03:50:03 +0000 (11:50 +0800)]
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: Use DM watchdog timer
Chee Hong Ang [Thu, 6 Aug 2020 04:15:33 +0000 (12:15 +0800)]
arm: socfpga: Use DM watchdog timer

All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Show reset state in SPL
Chee Hong Ang [Wed, 5 Aug 2020 13:15:57 +0000 (21:15 +0800)]
arm: socfpga: soc64: Show reset state in SPL

Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Add SDM triggered warm reset bit mask
Chee Hong Ang [Wed, 5 Aug 2020 13:15:56 +0000 (21:15 +0800)]
arm: socfpga: soc64: Add SDM triggered warm reset bit mask

Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agosysreset: socfpga: agilex: Enable sysreset support
Chee Hong Ang [Wed, 5 Aug 2020 12:11:26 +0000 (20:11 +0800)]
sysreset: socfpga: agilex: Enable sysreset support

Enable sysreset support for Agilex platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agosysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64
Chee Hong Ang [Wed, 5 Aug 2020 12:11:25 +0000 (20:11 +0800)]
sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64

Rename the driver from S10 to SoC64 because Intel Agilex platform
also using the this SYSRESET SoCFPGA driver for S10.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoconfigs: socfpga: soc64: Avoid SPL enter infinite loop during exception
Chin Liang See [Wed, 5 Aug 2020 10:34:33 +0000 (18:34 +0800)]
configs: socfpga: soc64: Avoid SPL enter infinite loop during exception

In current implementation, any exception would trigger a CPU reset.
But a bad written SPL would cause infinite loop where the system
will reload the same SPL instead of loading factory safe image.

Hence this patch is to ensure any exception will cause a hang. At this
moment, watchdog shall be triggered and Remote System Update mechanism
shall load the next production image or factory safe image.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Initialize timer in SPL only
Chee Hong Ang [Fri, 10 Jul 2020 15:53:13 +0000 (23:53 +0800)]
arm: socfpga: soc64: Initialize timer in SPL only

Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Remove PHY interface setup from misc arch init
Chee Hong Ang [Fri, 10 Jul 2020 15:52:32 +0000 (23:52 +0800)]
arm: socfpga: soc64: Remove PHY interface setup from misc arch init

'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoclk: agilex: Additional membus writes for HPS PLL
Chee Hong Ang [Fri, 10 Jul 2020 12:55:23 +0000 (20:55 +0800)]
clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoclk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Chee Hong Ang [Fri, 10 Jul 2020 12:55:22 +0000 (20:55 +0800)]
clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoclk: agilex: Add clock enable support
Ley Foon Tan [Fri, 10 Jul 2020 12:55:21 +0000 (20:55 +0800)]
clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoclk: agilex: Add NAND clock support
Ley Foon Tan [Fri, 10 Jul 2020 12:55:20 +0000 (20:55 +0800)]
clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash
Tom Rini [Thu, 8 Oct 2020 14:20:53 +0000 (10:20 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash

- Fix devicetree address determination seen on QEMU ARM64
- Use DMA for reads is available

4 years agocfi_flash: Fix devicetree address determination
Andre Przywara [Wed, 23 Sep 2020 23:22:04 +0000 (00:22 +0100)]
cfi_flash: Fix devicetree address determination

The cfi-flash driver uses an open-coded version of the generic
algorithm to decode and translate multiple frames of a "reg" property.

This starts off the wrong foot by using the address-cells and size-cells
properties of *this* very node, and not of the parent. This somewhat
happened to work back when we were using a wrong default size of 2,
but broke about a year ago with commit 0ba41ce1b781 ("libfdt: return
correct value if #size-cells property is not present").

Instead of fixing the reinvented wheel, just use the generic function
that does all of this properly.

This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding
a wrong flash base address:
DRAM:  1 GiB
Flash: "Synchronous Abort" handler, esr 0x96000044
elr: 00000000000211dc lr : 00000000000211b0 (reloc)
elr: 000000007ff5e1dc lr : 000000007ff5e1b0
x0 : 00000000000000f0 x1 : 000000007ff5e1d8
x2 : 000000007edfbc48 x3 : 0000000000000000
x4 : 0000000000000000 x5 : 00000000000000f0
x6 : 000000007edfbc2c x7 : 0000000000000000
x8 : 000000007ffd8d70 x9 : 000000000000000c
x10: 0400000000000003 x11: 0000000000000055
     ^^^^^^^^^^^^^^^^

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agomtd: cfi_mtd: Use DMA for reads
Vignesh Raghavendra [Thu, 17 Sep 2020 11:23:08 +0000 (16:53 +0530)]
mtd: cfi_mtd: Use DMA for reads

When possible use DMA for reading from CFI flash, this provides upto 5x
improvement in read performance with high speed CFI compliant flashes
like HyperFlash.

Code will gracefully fallback to CPU copy when DMA is unavailable.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agodma: Reduce error level when DMA channel type does not exist
Vignesh Raghavendra [Thu, 17 Sep 2020 11:23:07 +0000 (16:53 +0530)]
dma: Reduce error level when DMA channel type does not exist

Caller would need gracefully handle failures of dma_get_device(),
therefore reduce pr_err() to pr_debug() when DMA device is not found.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agoMerge tag 'mips-pull-2020-10-07' of https://gitlab.denx.de/u-boot/custodians/u-boot...
Tom Rini [Wed, 7 Oct 2020 21:25:25 +0000 (17:25 -0400)]
Merge tag 'mips-pull-2020-10-07' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- mips: octeon: add support for DDR4 memory controller
- mips: octeon: add support for DWC3 USB
- mips: octeon: add support for booting Linux

4 years agomips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LEN
Stefan Roese [Thu, 20 Aug 2020 05:22:04 +0000 (07:22 +0200)]
mips: octeon: octeon_common.h: Increase CONFIG_SYS_BOOTM_LEN

Increase CONFIG_SYS_BOOTM_LEN to 64MiB for Linux kernel booting.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add bootoctlinux command
Aaron Williams [Thu, 20 Aug 2020 05:22:03 +0000 (07:22 +0200)]
mips: octeon: Add bootoctlinux command

Octeon needs a platform specific cmd to boot the Linux kernel, as
specific parameters need to be passed and special handling for the
multiple cores (SMP) is needed.

Co-developed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
[use gd->ram_base instead of gd->bd->bi_memstart]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 years agomips: octeon: Add bootmem support
Aaron Williams [Thu, 20 Aug 2020 05:22:02 +0000 (07:22 +0200)]
mips: octeon: Add bootmem support

This is needed for Linux booting, as the memory infos need to be passed
in this bootmem format to the Linux kernel.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add coremask support
Aaron Williams [Thu, 20 Aug 2020 05:22:01 +0000 (07:22 +0200)]
mips: octeon: Add coremask support

This patch adds the coremask handling functions.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add header cvmx-bootinfo.h
Aaron Williams [Thu, 20 Aug 2020 05:22:00 +0000 (07:22 +0200)]
mips: octeon: Add header cvmx-bootinfo.h

Add header to handle bootinfo support, needed for Octeon Linux kernel
booting.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add header cvmx-fuse.h
Aaron Williams [Thu, 20 Aug 2020 05:21:59 +0000 (07:21 +0200)]
mips: octeon: Add header cvmx-fuse.h

Add header to handle Octeon fuse access.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add header octeon-feature.h
Aaron Williams [Thu, 20 Aug 2020 05:21:58 +0000 (07:21 +0200)]
mips: octeon: Add header octeon-feature.h

This header includes the Octeon feature detection used in many Octeon
drivers.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add header cvmx-regs.h
Aaron Williams [Thu, 20 Aug 2020 05:21:57 +0000 (07:21 +0200)]
mips: octeon: Add header cvmx-regs.h

This header includes common register defines and accessor functions.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux booting
Stefan Roese [Thu, 20 Aug 2020 05:21:56 +0000 (07:21 +0200)]
mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux booting

This patch adds the necessary lowlevel init code, to enable SMP Linux
booting. This code will be used with the platform specific Octeon Linux
boot command "bootoctlinux", which starts a configurable number of cores
into Linux.

Additionally some erratas and lowlevel register initializations are
copied from the original Cavium / Marvell U-Boot source code, enabling
booting into the Linux kernel.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: octeon-model.h: Enable inclusion from assembler files
Stefan Roese [Thu, 20 Aug 2020 05:21:55 +0000 (07:21 +0200)]
mips: octeon: octeon-model.h: Enable inclusion from assembler files

Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header
from assembler files.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: octeon_ebb7304_defconfig: Enable USB support
Stefan Roese [Mon, 24 Aug 2020 11:04:43 +0000 (13:04 +0200)]
mips: octeon: octeon_ebb7304_defconfig: Enable USB support

This patch enables USB support with some helpful commands, like fs
support.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add USB DT nodes
Stefan Roese [Mon, 24 Aug 2020 11:04:42 +0000 (13:04 +0200)]
mips: octeon: Add USB DT nodes

Add the USB device tree nodes to the Octeon dts/dtsi files.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agomips: octeon: cache.c: Flush all pending writes in flush_dcache_range()
Stefan Roese [Mon, 24 Aug 2020 11:04:41 +0000 (13:04 +0200)]
mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()

As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add mangle-port.h
Stefan Roese [Mon, 24 Aug 2020 11:04:40 +0000 (13:04 +0200)]
mips: octeon: Add mangle-port.h

Import platform specific mangle-port.h header, allowing a area specific
swapping, which is needed on Octeon for USB & PCI areas.

Imported from Linux v5.7.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: cpu.c: Add table for selective swapping
Stefan Roese [Mon, 24 Aug 2020 11:04:39 +0000 (13:04 +0200)]
mips: octeon: cpu.c: Add table for selective swapping

Import octeon_should_swizzle_table[] which is needed for the area
specific swapping. It will be used by the platform specific
mangle-port.h header.

Imported from Linux v5.7.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agousb: xhci: octeon: Add DWC3 glue layer for Octeon
Stefan Roese [Mon, 24 Aug 2020 11:04:38 +0000 (13:04 +0200)]
usb: xhci: octeon: Add DWC3 glue layer for Octeon

This patch adds the glue layer for the MIPS Octeon SoCs. It's ported
mainly from the Linux code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
4 years agousb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses
Stefan Roese [Mon, 24 Aug 2020 11:04:37 +0000 (13:04 +0200)]
usb: xhci: xhci_bulk_tx: Don't "BUG" when comparing addresses

Octeon uses mapped addresses for virtual and physical memory. It's not
that easy to calculate the resulting addresses here. So let's remove
this BUG_ON() completely, as it's not really helpful.

Please also note, that BUG_ON() is not recommended any more in the Linux
kernel.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
4 years agousb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()
Stefan Roese [Mon, 24 Aug 2020 11:04:36 +0000 (13:04 +0200)]
usb: xhci: xhci-dwc3.c: Use dev_remap_addr() instead of dev_get_addr()

On MIPS platforms, mapping of the base address is needed. This patch
switches from dev_get_addr() to dev_remap_addr() to get the mapped base
address of the xHCI controller.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
4 years agomips: octeon: octeon_ebb7304: Add DDR4 support
Stefan Roese [Wed, 2 Sep 2020 06:29:10 +0000 (08:29 +0200)]
mips: octeon: octeon_ebb7304: Add DDR4 support

This patch adds the board specific configuration (struct) for the
Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium /
Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in
the board defconfig for its usage.

Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB).

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: dram.c: Add RAM driver support
Stefan Roese [Wed, 2 Sep 2020 06:29:09 +0000 (08:29 +0200)]
mips: octeon: dram.c: Add RAM driver support

This patch adds the initialization call for the Octeon RAM driver to
the Octeon platforms code. So if enabled via Kconfig, the DDR driver
will be called and the RAM will be configured and used. If the RAM
driver is not enabled, the L2 cache is still used as RAM.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agoram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
Aaron Williams [Wed, 2 Sep 2020 06:29:08 +0000 (08:29 +0200)]
ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agoram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)
Aaron Williams [Wed, 2 Sep 2020 06:29:07 +0000 (08:29 +0200)]
ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 2 includes the very complex Octeon 3 DDR4 configuration

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agoram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)
Aaron Williams [Wed, 2 Sep 2020 06:29:06 +0000 (08:29 +0200)]
ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add octeon_ddr.h header
Aaron Williams [Wed, 2 Sep 2020 06:29:05 +0000 (08:29 +0200)]
mips: octeon: Add octeon_ddr.h header

This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon Add cvmx/cvmx-lmcx-defs.h header
Aaron Williams [Wed, 2 Sep 2020 06:29:04 +0000 (08:29 +0200)]
mips: octeon Add cvmx/cvmx-lmcx-defs.h header

This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: Add octeon-model.h header
Aaron Williams [Wed, 2 Sep 2020 06:29:03 +0000 (08:29 +0200)]
mips: octeon: Add octeon-model.h header

This header is used by the upcoming DDR driver and potentially by other
drivers ported from the 2013 Cavium / Marvell U-Boot repository.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agomips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT node
Stefan Roese [Wed, 2 Sep 2020 06:29:02 +0000 (08:29 +0200)]
mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT node

This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi
file. It also adds the L2C DT node, as this is referenced by the DDR
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
4 years agoMerge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dm
Tom Rini [Tue, 6 Oct 2020 17:59:01 +0000 (13:59 -0400)]
Merge tag 'dm-pull-6oct20' of git://git.denx.de/u-boot-dm

bloblist enhancement for alignment
Update ofnode/dev_read phandle function
sandbox keyboard enhancements and fixes

4 years agosandbox: avoid duplicate backslash input
Heinrich Schuchardt [Tue, 29 Sep 2020 01:56:20 +0000 (03:56 +0200)]
sandbox: avoid duplicate backslash input

When using SDL for input the SDL key codes are first converted to Linux key
codes and then to matrix entries of the cross wired keyboard.

We must not map any key code to two different places on the keyboard. So
comment out one backslash position.

Update the rest of the file from Linux 5.7.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agosandbox: add missing SDL key scan codes
Heinrich Schuchardt [Mon, 28 Sep 2020 23:41:18 +0000 (01:41 +0200)]
sandbox: add missing SDL key scan codes

Add missing SDL key scan codes, e.g.

* shift, ctrl, meta, alt
* brace/bracket

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agotest: dm: add test for phandle access functions
Patrick Delaunay [Fri, 25 Sep 2020 07:41:16 +0000 (09:41 +0200)]
test: dm: add test for phandle access functions

Add unitary test for phandle access functions
- ofnode_count_phandle_with_args
- ofnode_parse_phandle_with_args
- dev_count_phandle_with_args
- dev_read_phandle_with_args

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agofdtdec: correct test on return of fdt_node_offset_by_phandle
Patrick Delaunay [Fri, 25 Sep 2020 07:41:15 +0000 (09:41 +0200)]
fdtdec: correct test on return of fdt_node_offset_by_phandle

The result of fdt_node_offset_by_phandle is negative for error,
so this patch corrects the check of this result in
fdtdec_parse_phandle_with_args.

This patch allows to have the same behavior with or without OF_LIVE
for the function dev_read_phandle_with_args with cell_name = NULL and
with invalid phandle.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodm: add cells_count parameter in *_count_phandle_with_args
Patrick Delaunay [Fri, 25 Sep 2020 07:41:14 +0000 (09:41 +0200)]
dm: add cells_count parameter in *_count_phandle_with_args

The cell_count argument is required when cells_name is NULL.

This patch adds this parameter in live tree API
- of_count_phandle_with_args
- ofnode_count_phandle_with_args
- dev_count_phandle_with_args

This parameter solves issue when these API is used to count
the number of element of a cell without cell name. This parameter
allow to force the size cell.

For example:
  count = dev_count_phandle_with_args(dev, "array", NULL, 3);

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodm: update test on of_offset in ofnode_valid
Patrick Delaunay [Thu, 24 Sep 2020 15:26:20 +0000 (17:26 +0200)]
dm: update test on of_offset in ofnode_valid

Update the test for node.of_offset because an invalid offset is not
always set to -1 because the return value of the libfdt functions are:
+ an error with a value < 0
+ a valid offset with value >=0

For example, in ofnode_get_by_phandle() function, we have:
node.of_offset = fdt_node_offset_by_phandle(gd->fdt_blob, phandle);
and this function can return -FDT_ERR_BADPHANDLE (-6).

Without this patch, the added test dm_test_ofnode_get_by_phandle failed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodm: ofnode: Fix compile breakage with OF_CHECKS enabled
Stefan Roese [Wed, 23 Sep 2020 06:23:27 +0000 (08:23 +0200)]
dm: ofnode: Fix compile breakage with OF_CHECKS enabled

Include missing log.h and change _ofnode_to_np() to ofnode_to_np() so
that compiling with OF_CHECKS enabled does not break.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agobloblist: Fix up a few comments
Simon Glass [Sun, 20 Sep 2020 00:49:30 +0000 (18:49 -0600)]
bloblist: Fix up a few comments

Adjust a few comments to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agobloblist: Allow custom alignment for blobs
Simon Glass [Sun, 20 Sep 2020 00:49:29 +0000 (18:49 -0600)]
bloblist: Allow custom alignment for blobs

Some blobs need a larger alignment than the default. For example, ACPI
tables often start at a 4KB boundary. Add support for this.

Update the size of the test blob to allow these larger records.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agobloblist: Tidy up the data alignment
Simon Glass [Sun, 20 Sep 2020 00:49:28 +0000 (18:49 -0600)]
bloblist: Tidy up the data alignment

The intention which bloblists is that each blob's data is aligned in
memory. At present it is only the headers that are aligned.

Update the code to correct this and add a little more documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agobloblist: Compare addresses rather than pointers in tests
Simon Glass [Sun, 20 Sep 2020 00:49:27 +0000 (18:49 -0600)]
bloblist: Compare addresses rather than pointers in tests

When running these tests on sandbox any failures result in very large or
long pointer values which are a pain to work with. Map them to an address
so it is easier to diagnose failures.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agobloblist: Add a command
Simon Glass [Sun, 20 Sep 2020 00:49:26 +0000 (18:49 -0600)]
bloblist: Add a command

It is helpful to be able to see basic statistics about the bloblist and
also to list its contents. Add a 'bloblist' command to handle this.

Put the display functions in the bloblist modules rather than in the
command code itself. That allows showing a list from SPL, where commands
are not available.

Also make bloblist_first/next_blob() static as they are not used outside
this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agodoc/arch/sandbox.rst: reformat command line options
Heinrich Schuchardt [Sat, 19 Sep 2020 18:05:47 +0000 (20:05 +0200)]
doc/arch/sandbox.rst: reformat command line options

Reformat the command line options chapter so that the command line options
clearly stand out.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoMAINTAINERS: assign doc/arch/sandbox.rst
Heinrich Schuchardt [Sat, 19 Sep 2020 18:04:57 +0000 (20:04 +0200)]
MAINTAINERS: assign doc/arch/sandbox.rst

Add doc/arch/sandbox.rst to the scope of SANDBOX.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoMerge tag 'efi-2021-01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Tue, 6 Oct 2020 12:36:38 +0000 (08:36 -0400)]
Merge tag 'efi-2021-01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-01-rc1

The following bugs in the UEFI system are resolved:

* illegal free in EFI_LOAD_FILE2_PROTOCOL implementation
* incorrect documentation of EFI_LOAD_FILE2_PROTOCOL implementation
* output of CRC32 as decimal instead hexadecimal in unit test
* use EfiReservedMemoryType for no-map reserved memory
* avoid unnecessary resets in UEFI unit tests
* call EFI bootmgr even without having /EFI/boot

4 years agoMerge tag 'u-boot-amlogic-20201005' of https://gitlab.denx.de/u-boot/custodians/u...
Tom Rini [Tue, 6 Oct 2020 12:36:10 +0000 (08:36 -0400)]
Merge tag 'u-boot-amlogic-20201005' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver

4 years agoefi_loader: consider no-map property of reserved memory
Heinrich Schuchardt [Thu, 27 Aug 2020 10:52:20 +0000 (12:52 +0200)]
efi_loader: consider no-map property of reserved memory

The device tree may contain a /reserved-memory node. The no-map property
of the sub-nodes signals if the memory may be accessed by the UEFI payload
or not.

In the EBBR specification (https://github.com/arm-software/ebbr) the
modeling of the reserved memory has been clarified.

If a reserved memory node in the device tree has the no-map property map,
create a EfiReservedMemoryType memory map entry else use
EfiBootServicesData.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: QEMU CONFIG_EFI_GRUB_ARM32_WORKAROUND=n
Heinrich Schuchardt [Thu, 17 Sep 2020 17:09:23 +0000 (19:09 +0200)]
efi_loader: QEMU CONFIG_EFI_GRUB_ARM32_WORKAROUND=n

CONFIG_EFI_GRUB_ARM32 is only needed for architectures with caches that are
not managed via CP15 (or for some outdated buggy versions of GRUB). It
makes more sense to disable the setting per architecture than per defconfig.

Move QEMU's CONFIG_EFI_GRUB_ARM32_WORKAROUND=n from defconfig to Kconfig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi: Fix typo in documentation
Sean Anderson [Mon, 28 Sep 2020 16:08:37 +0000 (12:08 -0400)]
efi: Fix typo in documentation

There is an extra space.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agodistro_bootcmd: call EFI bootmgr even without having /EFI/boot
Michael Walle [Tue, 29 Sep 2020 06:54:48 +0000 (08:54 +0200)]
distro_bootcmd: call EFI bootmgr even without having /EFI/boot

Currently, the EFI bootmgr is only called if there is a EFI binary
inside the path for removable media is found, i.e. /EFI/boot/. This
doesn't make sense. It is the duty of the bootmgr to find out the
path and name of the EFI binary to boot. It should be called even
if there is no /EFI/boot directory.

Thus, call the bootmgr before we try to boot the EFI binary inside
the removable media path.

Also remove the ${fdtcontroladdr} parameter because the fallback is
handled in cmd/bootefi.c and that already takes care of correct settings
if the board has ACPI and thus no device tree at all.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_selftest: avoid unnecessary reset
Heinrich Schuchardt [Wed, 30 Sep 2020 19:52:09 +0000 (21:52 +0200)]
efi_selftest: avoid unnecessary reset

When we do not execute a test requiring ExitBootServices do not reset the
system after testing.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_selftest: print CRC32 of initrd as hexadecimal
Heinrich Schuchardt [Sat, 3 Oct 2020 11:43:45 +0000 (13:43 +0200)]
efi_selftest: print CRC32 of initrd as hexadecimal

Print the CRC32 loaded via the EFI_LOAD_FILE2_PROTOCOL as a hexadecimal
number.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
4 years agoefi_selftest: enable printing hexadecimal numbers
Heinrich Schuchardt [Sat, 3 Oct 2020 11:12:03 +0000 (13:12 +0200)]
efi_selftest: enable printing hexadecimal numbers

Add code to use %x in efi_st_print().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: illegal free in EFI_LOAD_FILE2_PROTOCOL
Heinrich Schuchardt [Sat, 3 Oct 2020 10:50:52 +0000 (12:50 +0200)]
efi_loader: illegal free in EFI_LOAD_FILE2_PROTOCOL

strsep() changes the address that its first argument points to.
We cannot use the changed address as argument of free().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
4 years agoefi_loader: description EFI_LOAD_FILE2_PROTOCOL
Heinrich Schuchardt [Sat, 3 Oct 2020 10:44:31 +0000 (12:44 +0200)]
efi_loader: description EFI_LOAD_FILE2_PROTOCOL

U-Boot offers a EFI_LOAD_FILE2_PROTOCOL which the Linux EFI stub can use to
load an initial RAM disk. Update the function comments of the
implementation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
4 years agoconfigs: Resync with savedefconfig
Tom Rini [Mon, 5 Oct 2020 17:11:41 +0000 (13:11 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoMerge branch 'next'
Tom Rini [Mon, 5 Oct 2020 17:05:46 +0000 (13:05 -0400)]
Merge branch 'next'

Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agopwm: Add driver for Amlogic Meson PWM controller
Neil Armstrong [Thu, 1 Oct 2020 08:04:56 +0000 (10:04 +0200)]
pwm: Add driver for Amlogic Meson PWM controller

This adds the driver for the PWM controller found in the Amlogic SoCs.

This PWM is only a set of Gates, Dividers and Counters:
PWM output is achieved by calculating a clock that permits calculating
two periods (low and high). The counter then has to be set to switch after
N cycles for the first half period.
The hardware has no "polarity" setting. This driver reverses the period
cycles (the low length is inverted with the high length) for
PWM_POLARITY_INVERSED.

Disabling the PWM stops the output immediately (without waiting for the
current period to complete first).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agopinctrl: meson-axg: add missing GPIOA_18
Neil Armstrong [Fri, 2 Oct 2020 07:32:12 +0000 (09:32 +0200)]
pinctrl: meson-axg: add missing GPIOA_18

Add the missing GPIOA_18 from the missing EE gpio list.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agopinctrl: meson-axg-pmx: fix gpio request
Neil Armstrong [Fri, 2 Oct 2020 07:31:46 +0000 (09:31 +0200)]
pinctrl: meson-axg-pmx: fix gpio request

The AXG pmx driver gpio request offset needs the pin base to have the
correct pin number.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
4 years agoboard: amlogic: vim3: add support for dynamic PCIe enable
Neil Armstrong [Mon, 21 Sep 2020 07:34:15 +0000 (09:34 +0200)]
board: amlogic: vim3: add support for dynamic PCIe enable

The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
an USB3.0 Type A connector and a M.2 Key M slot.
The PHY driving these differential lines is shared between
the USB3.0 controller and the PCIe Controller, thus only
a single controller can use it.

This adds this dynamic switching right before booting Linux
and the configuration steps in the boards documentation.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed warning by replacing min() by min_t()]

4 years agoconfigs: vim3: use the vim3 board support
Neil Armstrong [Mon, 21 Sep 2020 07:34:14 +0000 (09:34 +0200)]
configs: vim3: use the vim3 board support

Use the newly added VIM3 board support instead of the generic W400.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoboard: amlogic: add a vim3 specific board support
Neil Armstrong [Mon, 21 Sep 2020 07:34:13 +0000 (09:34 +0200)]
board: amlogic: add a vim3 specific board support

The VIM3 will need a specific code to enable PCIe if enabled in the MCU,
thus add a specific board support for VIM3 & VIM3L.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1
Neil Armstrong [Mon, 21 Sep 2020 07:34:12 +0000 (09:34 +0200)]
ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1

This imports the G12A & SM1 SoC and boards DT changes from the Linux
commit 9123e3a74ec7 ("Linux 5.9-rc1").

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoconfigs: s400: enable USB
Neil Armstrong [Thu, 10 Sep 2020 08:48:19 +0000 (10:48 +0200)]
configs: s400: enable USB

Enable USB Host & Gadget on the Amlogic S400 board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoARM: dts: meson-axg: add USB nodes for S400
Neil Armstrong [Thu, 10 Sep 2020 08:48:18 +0000 (10:48 +0200)]
ARM: dts: meson-axg: add USB nodes for S400

Add the correcly architectured USB Glue node for Meson AXG and the
S400 board in -u-boot.dtsi until support in upstream Linux then
backported.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoarm: meson-axg: add board_usb_init()/cleanup() for USB gadget
Neil Armstrong [Thu, 10 Sep 2020 08:48:17 +0000 (10:48 +0200)]
arm: meson-axg: add board_usb_init()/cleanup() for USB gadget

Add the board_usb_init()/cleanup() for USB gadget for AXG based
on the code for the G12A architecture.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agophy: meson-gxl-usb: depend on Meson AXG aswell
Neil Armstrong [Thu, 10 Sep 2020 08:48:16 +0000 (10:48 +0200)]
phy: meson-gxl-usb: depend on Meson AXG aswell

Enable build of meson-gxl-usb PHY for the AXG architecture aswell.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agophy: meson-gxl: remove invalid USB3 PHY driver
Neil Armstrong [Thu, 10 Sep 2020 08:48:15 +0000 (10:48 +0200)]
phy: meson-gxl: remove invalid USB3 PHY driver

The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).

Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agoARM: mach-meson: use new DWC3 glue for GXL & GXM
Neil Armstrong [Thu, 10 Sep 2020 08:48:14 +0000 (10:48 +0200)]
ARM: mach-meson: use new DWC3 glue for GXL & GXM

Use the new Amlogic GXL/GXM USB Glue instead of the set of USB3 PHY
and Simple DWC3 wrapper.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
4 years agousb: dwc3: add Amlogic GXL & GXL DWC3 Glue
Neil Armstrong [Thu, 10 Sep 2020 08:48:13 +0000 (10:48 +0200)]
usb: dwc3: add Amlogic GXL & GXL DWC3 Glue

The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).

But with the G12A family, the USB complex was correctly understood and
implemented correctly.

This adds a proper driver for the glue, based on the G12A one, but with
enough changes to require a different driver in U-Boot.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>