Michal Simek [Thu, 3 Jun 2021 08:47:04 +0000 (10:47 +0200)]
arm64: zynqmp: Remove gpio from aliases list
It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zhengxun [Fri, 11 Jun 2021 15:10:48 +0000 (15:10 +0000)]
clk: zynq: Add clock wizard driver
The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
Limited by U-Boot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency.
Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 7 Jun 2021 10:37:32 +0000 (12:37 +0200)]
arm64: zynqmp: Add support for 64bit addresses in its
Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also
generate u-boot.its with 64bit load/entry addresses to also support
different configurations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Srinivas Neeli [Mon, 8 Mar 2021 08:35:19 +0000 (14:05 +0530)]
arm64: zynqmp: rtc: Update rtc calibration value
As per the design specification
"The 16-bit Seconds Calibration Value represents the number of
Oscillator Ticks that are required to measure the largest time
period that is less than or equal to 1 second.
For an oscillator that is 32.768 KHz, this value will be 0x7FFF."
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 31 May 2021 09:06:59 +0000 (11:06 +0200)]
zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure
There is need to pass entry about secure OS when bl32_entry is defined.
Currently only 64bit support is added but /fit-images node have been
extended to also record if this is 32bit or 64bit secure OS. When this is
tested the code will be update to support this configuration too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 31 May 2021 09:13:45 +0000 (11:13 +0200)]
zynqmp: Generate u-boot.its also with TEE dynamically
The first change is to trying to find out TF-A load address based on
reading elf file. Expectation is that bl31.bin is in the same folder as
bl31.elf. It brings new flexibility to place TF-A to any address (DDR
included).
And also enable TEE generation also with TEE configuration.
Expecation is the same as above that tee.bin and tee.elf are in the same
folder.
User has to just define link to BL31/BL32 binary files and the rest should
be handled by the script.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 31 May 2021 09:03:19 +0000 (11:03 +0200)]
zynqmp: Do not place u-boot to reserved memory location
TF-A and SecureOS can allocate the part of DDR for self but U-Boot is not
handling this configuration that the part of memory is reserved and
shouldn't be used by U-Boot. That's why read all reserved memory locations
and don't use it.
The code was taken from commit 4a1b975dac02 ("board: stm32mp1: reserve
memory for OP-TEE in device tree") and commit 1419e5b5167e ("stm32mp:
update MMU config before the relocation") which is used by stm32 and does
the job properly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
The SMMU is disabled in device tree so this change has no impact.
The benefit is that this way it is in sync with xen.dtsi. Xen enables
the SMMU and makes use of it.
Michal Simek [Mon, 11 May 2020 08:14:34 +0000 (10:14 +0200)]
arm64: zynqmp: Disable CCI by default
There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 19 May 2021 13:16:19 +0000 (15:16 +0200)]
arm64: zynqmp: Handle MMC seq number based on boot device
K26 has EMMC and SD and default 0 is not working when system is booting out
of SD which is controller 1. Add controller autodetection via
mmc_get_env_dev(). The same code is used for distro_boot selection done in
board_late_init(). bootseq variable can't be reused because this is called
so late.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 26 Nov 2020 13:25:01 +0000 (14:25 +0100)]
ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."
Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml
Similar change has been done for Xilinx ZynqMP SoC.
Michal Simek [Mon, 5 Oct 2020 07:35:40 +0000 (09:35 +0200)]
arm64: zynqmp: Add support for SVD devices
SVDs are using different name which can't be handled via zynqmp_devices
structure. That's why introduce zynqmp_detect_svd_name() which checks ID
code for these devices and show proper name for them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 13 May 2021 11:58:58 +0000 (13:58 +0200)]
arm64: zynqmp: Enable EFI secure boot
Enabling EFI secure boot which is required for EBBR specification.
Enabling this will fix
"RT.SetVariable - Create one Time Base Auth Variable, the expect return
status should be EFI_SUCCESS"
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Fix application loading on R5 core1
From U-Boot, loading application on RPU core 0 is fine but loading on
core 1 is not handled properly. Lock-step mode needs both the R5 cores
to be initialized and it is working fine. Whereas in SPLIT mode individual
R5 cores needs to be initialized as they need to execute differenet
applications. Handle both these lock-step and split modes by propagating
mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions
and by adding conditions in those functions.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 26 Nov 2020 13:25:03 +0000 (14:25 +0100)]
ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to
json-schema") converted binding to yaml and some missing required
properties started to be reported. Align binding based on it.
The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml
Michal Simek [Thu, 26 Nov 2020 13:25:04 +0000 (14:25 +0100)]
ARM: zynq: Convert at25 binding to new description on zc770-xm013
The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding
document to yaml") converted binding to yaml and 3 deprecated properties
pop up.
The patch is fixing these warnings:
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
>From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml
Use the ZDMA channel 0 to initialize the DRAM banks. This avoid
spurious ECC errors that can occur when accessing unitialized memory.
The feature is enabled by setting the option
CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data:
SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize
SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex)
SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize
SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex)
Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
cmd: pxe_utils: sysboot: fix crash if either board or soc are not set.
If the environment does not have "soc" or "board" set, and fdtdir
option is specified in extlinux.conf, the bootloader will crash whilst
dereferencing a null pointer. Add a guard against null soc or
board. Fixes a crash of qemu-riscv64_smode configuration, which does
not have CONFIG_SYS_SOC defined.
Signed-off-by: Dimitri John Ledkov <xnox@ubuntu.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
In u-boot device trees both prefixes are used. Until recently the only
user of the ethernet alias was the sandbox test device tree. This
changed with commit fc054d563bfb ("net: Introduce DSA class for Ethernet
switches"). There, the MAC addresses are inherited based on the devices
sequence IDs which is in turn given by the device tree.
Before there are more users in u-boot and both worlds will differ even
more, rename the alias prefix to "ethernet" to match the linux ones.
Also adapt the test cases and rename any old aliases in the u-boot
device trees.
Cc: David Wu <david.wu@rock-chips.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michael Walle [Wed, 24 Feb 2021 16:30:44 +0000 (17:30 +0100)]
net: use a more deterministic approach to get the active ethernet device
If the environment variable "ethact" is not set, the first device in the
uclass is returned. This depends on the probing order of the ethernet
devices. Moreover it is not not configurable at all.
Try to return the ethernet device with sequence id 0 first which then
can be configured by the aliases in a device tree. Fall back to the old
mechanism in case of an error.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Daniil Stas [Sun, 30 May 2021 13:34:09 +0000 (13:34 +0000)]
net: dwc_eth_qos: Revert some changes of commit 3a97da12ee7b
Revert some changes of commit 3a97da12ee7b ("net: dwc_eth_qos: add dwc
eqos for imx support") that were probably added by mistake.
One of these changes can lead to received data corruption (enabling
FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings
for some platforms. And another makes some writes at unknown memory
location.
Fixes: 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support") Signed-off-by: Daniil Stas <daniil.stas@posteo.net> Cc: Ye Li <ye.li@nxp.com> Cc: Fugang Duan <fugang.duan@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Tim Harvey [Fri, 16 Apr 2021 20:25:09 +0000 (13:25 -0700)]
net: e1000: do not attempt to set hwaddr for i210 without FLASH
commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM")
adds support for storing hwaddr in EEPROM however i210 devices do not
support this and thus results in errors such as:
Warning: e1000#0 failed to set MAC address'
Check if a flash device is present and if not return -ENOSYS indicating
this is not supported.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Priyanka Jain [Thu, 17 Jun 2021 07:22:46 +0000 (12:52 +0530)]
board: freescale: t1028xrdb: Add MAINTAINER for revD
Add Priyanka Jain as MAINTAINER for
T2080RDB_revD_defconfig,
T2080RDB_revD_NAND_defconfig,
T2080RDB_revD_SDCARD_defconfig and
T2080RDB_revD_SPIFLASH_defconfig
Ran Wang [Wed, 16 Jun 2021 12:23:19 +0000 (17:53 +0530)]
armv8: Update erratum number to align with doc
Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.
Fixes 0cfa00cdb94 (“armv8: Add workaround for USB erratum A-050106”) Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Camelia Groza [Fri, 11 Jun 2021 12:28:08 +0000 (15:28 +0300)]
board: freescale: t208xrdb: add a config option for rev D dts fixups
Under DM, we rely on u-boot's device tree to provide the correct PHY
addresses. The board_fix_fdt callback is intended to be used for
device tree fixups before relocation. Unfortunately, this isn't an
option when booting from flash since the device tree isn't writable
before relocation.
This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a
board revision D or up is the target. The config option is used to set
the correct Aquantia PHY address in the board's u-boot device tree.
Defconfig files with the option enable explicitly are added for
convenience.
Camelia Groza [Wed, 16 Jun 2021 12:17:31 +0000 (17:47 +0530)]
board: freescale: t208xrdb: add Linux fdt fix-ups for rev D
The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C (0x8 instead of 0x1).
Fix-up the Linux device tree to update the PHY address for the second
Aquantia PHY on boards revisions D and up. Also rename the PHY node to
reflect the changes.
Camelia Groza [Fri, 11 Jun 2021 12:28:05 +0000 (15:28 +0300)]
board: freescale: t208xrdb: remove the legacy non-DM_ETH code
Both DM_ETH and DM_PCI are enabled for the T2080RDB board. Remove the
board_eth_init() callback and the non-DM_ETH code paths since they are not
needed anymore.
A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.
This patch corrects the system counter clock to
8.333MHz = 66.667MHz / 8.
In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.
This patch uses available hwconfig option for updating ls102x device
disable configuration.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.
For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.
Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This is most probably a typo, and in older u-uboot versions is same as
'saveenv', in the newer uboot versions there is a separate 'save' command
that is different from 'saveenv'.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
km/ls102xa: add support for u-boot POST memory test
From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.
On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
board/km: add support for expu1 design based on nxp
The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.
The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.
Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
[Fixed new line error at EOF] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
net: tsec: add option to set device max-speed via dts
Current tsec adapter sets adapter gigabit capabilities by default, and in
reality this must not always be the case.
It is possible that tsec adapter is used for 100Mbps connection, and in
this case setting 1000Mbps capabilities can lead to some side effects such
longer autoneg process.
In our ls102x designs this problem leads to long autoneg times (> 4 sec)
in case board rgmii link is 100Mbps capable only.
Limiting the rgmii link capabilities provides faster and smoother
link establishment.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
During the mainlining of the board this was by mistake set to sector size.
Our user space env scripts are expecting envsize of 0x4000, and setting
this differently will break our cross-platform compatibility.
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Yangbo Lu [Thu, 3 Jun 2021 02:51:17 +0000 (10:51 +0800)]
mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
For eSDHC, power supply is through peripheral circuit.
Some eSDHC versions have value 0 of the bit but that
does not reflect the truth. 3.3V is common for SD/MMC,
and is supported for all boards with eSDHC in current
u-boot. So, make 3.3V is supported in default in code.
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if
future board does not support 3.3V.
This is also a fix-up for one previous patch, which converted
to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
that is not a Kconfig option.
Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Biwen Li [Fri, 21 May 2021 07:15:06 +0000 (15:15 +0800)]
configs: ls2088aqds: fix synchronous exception
IFC NOR flash base address of ls2088a is 0x580000000,
and offset of env crc is 0x500000, so fix the macro
CONFIG_ENV_ADDR to fix synchronous exception(access illegal address)
armv8: ls1012a: Pass PPFE firmware to Linux through FDT
Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)
Bin Meng [Tue, 15 Jun 2021 05:45:57 +0000 (13:45 +0800)]
riscv: andes_plic: Fix riscv_get_ipi() mask
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com>
Bin Meng [Fri, 4 Jun 2021 05:51:13 +0000 (13:51 +0800)]
riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.
Let's add all the required "u-boot,dm-spl" for SPL config.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Fri, 4 Jun 2021 05:51:12 +0000 (13:51 +0800)]
riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
projects / u-boot.git / log