armv8/ls1088a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Stephen Warren [Tue, 9 Jan 2018 19:52:14 +0000 (12:52 -0700)]
Makefile: ensure DTB doesn't overflow into initial stack
With CONFIG_SYS_INIT_SP_BSS_OFFSET enabled, the initial (pre-relocation)
stack is placed some distance after bss_start. The control DTB is appended
to the U-Boot binary at bss_start. If the DTB is too large, or the SP BSS
offset too small, then the initial stack could corrupt the DTB. Enhance
the Makefile to check whether this is likely to occur.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Tue, 9 Jan 2018 00:41:24 +0000 (17:41 -0700)]
ARM: Tegra186: calculate load addresses at boot
In the presence of potentially fragemented memory, we cannot hard-code
addresses into environment variables such as kernel_addr_r. Instead, we
must calculate those addresses at run-time based on available memory
locations. Implement the code to perform such runtime calculation, based
on requirements described in environment variables, to allow the user
full control over the allocation.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 4 Jan 2018 18:07:14 +0000 (11:07 -0700)]
ARM: Tegra186: don't map memory not in RAM banks
Tegra186 currently restricts its DRAM usage to entries in the /memory node
in the DTB passed to it. However, the MMU configuration always maps the
entire first 2GB of RAM. This could allow the CPU to speculatively access
RAM that isn't part of the in-use banks. This patch switches to runtime
construction of the table that's used to construct the MMU translation
tables, and thus prevents access to RAM that's not part of a valid bank.
Note: This patch is intended to prevent access to RAM regions which U-Boot
does not need to access, with the primary purpose of avoiding theoretical
speculative access to physical regions for which the HW will throw errors
(e.g. carve-outs that the CPU has no permission to access at a bus level,
bad ECC pages, etc.). In particular, this patch is not deliberately
related to the speculation-related security issues that were recently
announced. The apparent similarity is a coincidence.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:32:35 +0000 (14:32 -0700)]
ARM: tegra: p2771-000: increase max DRAM bank count
On this platform, there may be up to 1024 unusable chunks of memory.
Increase CONFIG_NR_DRAM_BANKS so that U-Boot can remember all the banks
required to represent such fragmented memory.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:32:34 +0000 (14:32 -0700)]
ARM: Tegra186: search for best RAM bank
In the future, the list of DRAM regions passed to U-Boot in the DTB may
be quite long and fragmented. Due to this, U-Boot must search through the
regions to find the best region to relocate into, rather than relying on
the current assumption that the top of bank 0 is a reasonable relocation
target. This change implements such searching.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Fri, 5 Jan 2018 20:04:54 +0000 (13:04 -0700)]
ARM: bootm: don't assume sp is in DRAM bank 0
arch_lmb_reserve() currently assumes that the stack pointer is within DRAM
bank 0. This is not necessarily true. Enhance the code to search through
DRAM banks until the bank that does contain SP is found, and then reserve
the tail of that bank.
Fixes: 2d1916e48bd8 ("ARM: add flat device tree support") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 3 Jan 2018 21:31:51 +0000 (14:31 -0700)]
ARMv8: add optional Linux kernel image header
Allow placing a Linux kernel image header at the start of the U-Boot
binary. This is useful since the image header reports the amount of memory
(BSS and similar) that U-Boot needs to use, but that isn't part of the
binary size. This can be used by the code that loads U-Boot into memory to
determine where to load U-Boot, based on other users of memory.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:37 +0000 (18:30 -0700)]
ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSET
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place
the stack/... 512KiB from the end of the U-Boot binary. This should be
plenty to accommodate the current DTBs (max 64 KiB), early malloc region
(6KiB), stack usage, and plenty of slack, while still not placing it too
far away from the U-Boot binary.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:36 +0000 (18:30 -0700)]
ARMv8: Allow dynamic early stack pointer
U-Boot typically uses a hard-coded value for the stack pointer before
relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate
the initial SP at run-time. This is useful to avoid hard-coding addresses
into U-Boot, so that can be loaded and executed at arbitrary addresses and
thus avoid using arbitrary addresses at runtime. This option's value is
the offset added to &_bss_start in order to calculate the stack pointer.
This offset should be large enough so that the early malloc region, global
data (gd), and early stack usage do not overlap any appended DTB.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Dec 2017 01:30:34 +0000 (18:30 -0700)]
ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPL
64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE
when building. Fix the binman .dts file so that it doesn't use undefined
values.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peng Fan [Tue, 2 Jan 2018 08:51:22 +0000 (16:51 +0800)]
mmc: fsl_esdhc: Fix eMMC 1.8v setting issue
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.
Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Fri, 22 Dec 2017 17:27:14 +0000 (12:27 -0500)]
power: Rearrange code to guard power command with CONFIG_SPL_BUILD guard
In order to discard this code when unused in SPL we need to guard the
command with a check for CONFIG_SPL_BUILD and we rearrange the code
slightly to make this cleaner.
Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Rick Chen [Tue, 26 Dec 2017 05:55:58 +0000 (13:55 +0800)]
riscv: Modify generic codes to support RISC-V
Support common commands bdinfo and image format,
also modify common generic flow for RISC-V.
Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
RISC-V # fatload mmc 0:1 0x600000 hello_world_ae250_32.bin
reading hello_world_ae250_32.bin
1252 bytes read in 23 ms (52.7 KiB/s)
RISC-V # go 0x600000
Example expects ABI version 9
Actual U-Boot ABI version 9
Hello World
argc = 1
argv[0] = "0x600000"
argv[1] = "$B@"
Hit any key to exit ...
RISC-V #
Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
Rick Chen [Tue, 26 Dec 2017 05:55:48 +0000 (13:55 +0800)]
riscv: cpu: Add nx25 to support RISC-V
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch
Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.
Detail verification message please see doc/README.ae250.
Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
mmc: compile out erase and write mmc commands if write operations are not enabled
Also remove erase_grp_size and write_bl_len from struct mmc as they are
not used anymore. On ARM, removing them saves about 100 bytes of code
space in SPL.
mmc: add a Kconfig option to enable the support for MMC write operations
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL
mmc: atmel: when sending a data command, use the provided block size
struct mmc_data contains the block size to use for the data transfer.
Use this information instead of using the default value or the block length
information stored in struct mmc.
Tom Rini [Sun, 17 Dec 2017 04:01:22 +0000 (23:01 -0500)]
am335x_hs_evm: Trim options in SPL to reduce binary size
The am335x_hs_evm runs into size constraint problems at times with
various toolchains as changes come in due to the config have a large
number of options in SPL (to showcase what is possible) while also
having rather constrained binary limits. Gain some of this room back by
lowering the loglevel, disabling HW partition support and switching over
to the tiny FIT image support.
Cc: Andrew F. Davis <afd@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
---
I'd really appreciate a run-time test of this patch if at all possible
as I'm a little worried about TINY_FIT being incompatible with all of
the security options. Thanks!
The SDcard initialization procedure does a few more things than it did earlier:
* switch the bus width even for 1-bit bus width
* check that speed has been properly set (in resp[4] of SD_CMD_SWITCH_FUNC)
Update the SD simulator to handle those requests gracefully.
configs: omapl138_lcdk: decrease the loglevel to reduce the size of the SPL
The changes in the MMC stack have increased its footprint up to the point
were its breaks the generation of the SPL for this platform.
Fix this by reducing the loglevel.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Peter Howard <phoward@gme.net.au>
configs: openrd: removed support for eMMC hardware partitioning
builds are broken because the size of the binary exceeds the limit.
Make some space by removing support for hardware partitioning as those
boards don't have any eMMC.
Supporting USH and HS200 increases the code size as it brings in IO voltage
control, tuning and fatter data structures.
Use Kconfig configuration to select which of those features should be
built in.
Not using this function reduces the size of the binary. It's replaces by
a standard malloc() and the alignment requirement is handled by an
intermediate buffer on the stack.
Also make sure that the allocated buffer is freed in case of error.
mmc: dump card and host capabilities if debug is enabled
This is a useful information while debugging the initialization process or
performance issues.
Also dump this information with the other mmc info if the verbose option
is selected
dm: mmc: Add a library function to parse generic dt binding
Add a new function to parse host controller dt node and
set mmc_config. This function can be used by mmc controller
drivers to set the generic mmc_config.
This function can be extended to set other UHS mode caps
once UHS mode support is added.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc: add a library function to send tuning command
HS200/SDR104 requires tuning command to be sent to the card.
Add a simple function to send tuning command and to read and
compare the received data with the tuning block pattern.
This function can be used by platform driver to perform DLL
tuning.
This patch is similar to
commit 996903de92f0 ("mmc: core: add core-level function for
sending tuning commands") added in linux kernel.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc: use the right voltage level for MMC DDR and HS200 modes
HS200 only supports 1.2v and 1.8v signal voltages. DDR52 supports 3.3v/1.8v
or 1.2v signal voltages.
Select the lowest voltage available when using those modes.
With certain SD cards like Kingston 8GB/16GB UHS card, it is seen that
MMC_CMD_ALL_SEND_CID cmd fails on first attempt, but succeeds
subsequently. Therefore, retry MMC_CMD_ALL_SEND_CID cmd a few time
as done in Linux kernel.
Similarly, it is seen that MMC_CMD_SET_BLOCKLEN may fail on first
attempt, therefore retry this cmd a few times as done in kernel.
To make it clear that those are optionnal workarounds, a new Kconfig
option 'MMC_QUIRKS' is added (enabled by default).
Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc: Change mode when switching to a boot partition
Boot partitions do not support HS200. Changing to a lower performance mode
is required to access them.
mmc_select_mode_and_width() and sd_select_mode_and_width() are modified to
make it easier to call them outside of the initialization context.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
mmc: disable UHS modes if Vcc cannot be switched on and off
If a power cycle cannot be done on Vcc, it is safer not to try the UHS
modes because we wouldn't be able to recover from an error occurring
during the UHS initialization.
Add UHS modes to the list of supported modes, get the UHS capabilites of
the SDcard and implement the procedure to switch the voltage (UHS modes
use 1v8 IO lines)
During the voltage switch procedure, DAT0 is used by the card to signal
when it's ready. The optional card_busy() callback can be used to get this
information from the host driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
There is no point in having the mmc clock enabled during
power off. Disable the mmc clock. This is similar to how it's
programmed in Linux Kernel.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
mmc clock has to be disabled in certain cases like during
the voltage switch sequence. Modify mmc_set_clock function
to take disable as an argument that signifies if the
clock has to be enabled or disabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc/sd specification requires vdd to be disabled for 1 ms
and then enabled again during power cycle. Add a
function in mmc core to perform power cycle and set
the io signal to it's initial state.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
mmc: Add a new callback function to perform the 74 clocks cycle sequence
Add a new callback function *send_init_stream* which start a sequence of
at least 74 clock cycles.
The mmc core uses *mmc_send_init_stream* in order to invoke the callback
function. This will be used during power cycle where the specification
requires such a sequence after power up.
mmc: Enable signal voltage to be selected from mmc core
Add a new function *mmc_set_signal_voltage* in mmc core
which can be used during mmc initialization to select the
signal voltage. Platform driver should use the set_ios
callback function to select the signal voltage.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
set_ios callback has a return value of 'int' but the mmc_set_ios()
function ignore this. Modify mmc_set_ios() and the callers of mmc_set_ios() to
to return the error status.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
mmc: refactor MMC startup to make it easier to support new modes
The MMC startup process currently handles 4 modes. To make it easier to
add support for more modes, let's make the process more generic and use a
list of the modes to try.
The major functional change is that when a mode fails we try the next one.
Not all modes are tried, only those supported by the card and the host.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
mmc: refactor SD startup to make it easier to support new modes
The SDcard startup process currently handles only 2 modes. To make it
easier to add support for more modes, let's make the process more generic
and use a list of the modes to try.
The major functional change is that when a mode fails we try the next one.
Not all modes are tried, only those supported by the card and the host.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
No functionnal change here. The function is really big and can be split.
The part related to bus configuration are put in 2 separate functions: one
for MMC and one for SD.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
mmc: sdhci: don't clear SDHCI_INT_STATUS register during CMD_INHIBIT
Fixes emmc initialization regression on the db410c platform.
Clearing this register while SDHCI_PRESENT_STATE reports
SDHCI_CMD_INHIBIT leads to undefined behaviour on the db410c.
When commit 7dde50 was merged (mmc: sdhci: Wait for SDHCI_INT_DATA_END
when transferring), SDHCI transfers transitioned to wait for bit
SDHCI_INT_DATA_END before flagging transfers done.
Without this patch, the db410 platform fails to initialize its eMMC
due to all of its transfers timing out (SDHCI_INT_DATA_END is never
raised after all the blocks have been transferred).
Felix Brack [Wed, 11 Oct 2017 15:05:28 +0000 (17:05 +0200)]
mmc: sanitize includes for DM i2c
This patch fixes some warnings when building boards that do not define
DM_I2C_COMPAT i.e. boards that entirely rely on the new i2c layer. Signed-off-by: Felix Brack <fb@ltec.ch>
Suniel Mahesh [Thu, 5 Oct 2017 06:02:00 +0000 (11:32 +0530)]
drivers: mmc: Change buffer type in ALLOC_CACHE_ALIGN_BUFFER macro
__be32_to_cpu() accepts argument of type __be32. This patch changes
type of the buffer in ALLOC_CACHE_ALIGN_BUFFER macro to __be32, which
is then passed to __be32_to_cpu().
This prevents sparse build warnings.
drivers/mmc/mmc.c: warning: cast to restricted __be32
board/BuR: provide real clock-frequency instead a divider
Actual am335x-fb implementation takes now a real clock frequency instead
a divider. So this component doesn't need to know anymore some base
frequency of the LCDC, we simply provide the pixel-clock frequency.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.
The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).
This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Anatolij Gustschin <agust@denx.de>
projects / u-boot.git / log