Chris Webb [Fri, 19 Jul 2019 13:23:55 +0000 (14:23 +0100)]
rockchip: TPL banner should depend on CONFIG_TPL_BANNER_PRINT
The generic code in common/spl/spl.c allows TPL/SPL banners to be
silenced by unsetting CONFIG_TPL_BANNER_PRINT or CONFIG_SPL_BANNER_PRINT
respectively. However, arch/arm/mach-rockchip/tpl.c prints this banner
unconditionally.
Fix the rockchip-specific tpl.c so that the TPL banner depends on
CONFIG_TPL_BANNER_PRINT in the same way as the generic code.
Signed-off-by: <chris@arachsys.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Chris Webb [Fri, 19 Jul 2019 13:23:11 +0000 (14:23 +0100)]
rockchip: Fix TPL build without CONFIG_TPL_SERIAL_SUPPORT
If CONFIG_DEBUG_UART is set but CONFIG_TPL_SERIAL_SUPPORT is not, the
serial output should be available in SPL and full U-Boot, but not built
in TPL. However, the rockchip tpl.c instead fails to compile with
undefined references to the debug UART.
Instead, initialise the debug UART and print the TPL banner only if both
CONFIG_DEBUG_UART and CONFIG_TPL_SERIAL_SUPPORT are set.
Signed-off-by: <chris@arachsys.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Tom Rini [Sun, 21 Jul 2019 19:40:21 +0000 (15:40 -0400)]
Merge tag 'rockchip-for-v2019.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rk3399 lpddr4 support
- rk3399-rock960 board support improvement
- Eliminate pyelftools dependency by make_fit_atf.py
- clean up rockchip dts to use -u-boot.dtsi
- use ARM arch/generic timer instead of rk_timer
- clean up Kconfig options for board support
Chris Webb [Tue, 16 Jul 2019 19:53:26 +0000 (20:53 +0100)]
rockchip: Remove obsolete references to pyelftools
make_fit_atf.py no longer requires pyelftools, and nothing else in the
rockchip build requires it either, so remove references to installing it
from the documentation.
Signed-off-by: Chris Webb <chris@arachsys.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.
Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.
Signed-off-by: Chris Webb <chris@arachsys.com> Reviewed-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:59 +0000 (22:05 +0800)]
rockchip: rk3399: use common secure_timer_init() for spl/tpl
SPL/TPL share the same secure_timer_init(), update to use
one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE
as base address and rename to function name to rockchip_stimer_init().
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:55 +0000 (22:05 +0800)]
rockchip: add common tpl board file
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
of SoCs to avoid copy-pase for different SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:27 +0000 (22:00 +0800)]
rockchip: rk3128: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:26 +0000 (22:00 +0800)]
rockchip: rk3288: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:25 +0000 (22:00 +0800)]
rockchip: rk3036: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track the boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:23 +0000 (22:00 +0800)]
rockchip: rk322x: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:43 +0000 (21:58 +0800)]
rockchip: rk3288: add arch_cpu_init in spl
Add arch_cpu_init() in SPL for soc related init, and
move configure_l2ctlr() into it.
The arch_cpu_init() only need to run once, so no need
to run in TPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:20 +0000 (22:14 +0800)]
rockchip: Kconfig: move ROCKCHIP_BOOT_MODE_REG to soc Kconfig
Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value,
move it to SoC's own Kconfig, and add address for rk3128 and
rk3328 so that all SoCs have available address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:45 +0000 (17:27 +0530)]
rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:56 +0000 (23:58 +0530)]
rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:44 +0000 (17:27 +0530)]
rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:40 +0000 (17:27 +0530)]
ram: rk3399: Add lpddr4 set rate support
Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.
The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.
Here is sameple log about LPDDR4-100 init sequence in Rockpro64:
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0
This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:39 +0000 (17:27 +0530)]
ram: rk3399: Add set_rate sdram rk3399 ops
DDR set rate can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.
For this requirement, and for code readability handle
data training via sdram_rk3399_ops with .set_rate and
same will update in future while supporting lpddr4 code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:38 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDDR4-800 timings inc
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:37 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDDR4-400 timings inc
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-400 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:31 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDR4 mr detection
Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.
Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.
So, add code to support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:29 +0000 (17:27 +0530)]
ram: rk3399: Simplify data training first argument
data training is using chan_info as first argument with
channel number as second argument instead of that use
dram_info as first argument so-that we can get the
chan_info at data training definition.
This was the argument handling is meaningful, readable
and it would help to add similar data training for
lpddr4 in future.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:21 +0000 (17:27 +0530)]
ram: rk3399: Add IO settings
Add IO settings for dram ctl and phy.
IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.
Right now, this patch added IO setting for all supported
sdram frequencies.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
projects / u-boot.git / log