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2 years agoimx8mm-cl-iot-gate-optee: add CONFIG_SPL_MMC and CONFIG_SPL_SERIAL
Ying-Chun Liu (PaulLiu) [Mon, 15 Nov 2021 09:44:07 +0000 (17:44 +0800)]
imx8mm-cl-iot-gate-optee: add CONFIG_SPL_MMC and CONFIG_SPL_SERIAL

Previously these two options are called CONFIG_SPL_MMC_SUPPORT
and CONFIG_SPL_SERIAL_SUPPORT. During the transition they are
removed by accident. Thus adding them back.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agospi: mxc_spi: remove redundant code in spi_xchg_single()
Haolin Li [Sat, 6 Nov 2021 10:03:34 +0000 (03:03 -0700)]
spi: mxc_spi: remove redundant code in spi_xchg_single()

The value of cnt is overwritten without being used.

Signed-off-by: Haolin Li <li.haolin@qq.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agoarm: imx8m: imx8mm-cl-iot-gate: detect extension board
Ying-Chun Liu (PaulLiu) [Fri, 5 Nov 2021 09:13:25 +0000 (17:13 +0800)]
arm: imx8m: imx8mm-cl-iot-gate: detect extension board

Extension boards can be added to Compulab's iot-gate-imx8mm.
We implement extension board manager for detecting the extension
boards.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2 years agoarm: dts: imx8mm-cl-iot-gate: add Compulab's ied overlays
Ying-Chun Liu (PaulLiu) [Fri, 5 Nov 2021 09:13:24 +0000 (17:13 +0800)]
arm: dts: imx8mm-cl-iot-gate: add Compulab's ied overlays

add the following overlays:
 - IED extension board
 - CAN/TPM/ADC extension board on IED board.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2 years agoimx8ulp: ddr: Fix DDR frequency request issue
Ye Li [Fri, 29 Oct 2021 01:46:34 +0000 (09:46 +0800)]
imx8ulp: ddr: Fix DDR frequency request issue

After acking the requested frequency, should wait the ack bit clear
by DDR controller and check the DFS interrupt for next request polling.
Otherwise, the next polling of request bit will get previous value
that DDR controller have not cleared it, so a wrong request frequency
is used.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp:ddr: saving the dram config timing data into sram
Jacky Bai [Fri, 29 Oct 2021 01:46:33 +0000 (09:46 +0800)]
imx8ulp:ddr: saving the dram config timing data into sram

On i.MX8ULP, The dram config timing need to be saved into sram for
ddr retention when APD enter PD mode, so add this support on i.MX8ULP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: implement to obtain the SoC current temperature
Alice Guo [Fri, 29 Oct 2021 01:46:32 +0000 (09:46 +0800)]
imx8ulp: implement to obtain the SoC current temperature

Obatin the SoC current temperature in print_cpuinfo().

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: clock: Handle the DDRLOCKED when setting DDR clock
Ye Li [Fri, 29 Oct 2021 01:46:30 +0000 (09:46 +0800)]
imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock

The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: clock: Support to enable/disable the ADC1 clock
Alice Guo [Fri, 29 Oct 2021 01:46:29 +0000 (09:46 +0800)]
imx8ulp: clock: Support to enable/disable the ADC1 clock

This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: Update ethernet mac to get from fuse
Ye Li [Fri, 29 Oct 2021 01:46:28 +0000 (09:46 +0800)]
imx8ulp: Update ethernet mac to get from fuse

Get the MAC address from fuse bank5 word 3 and 4. It has
MSB first at lowest address, so have a reverse order with other
iMX used in mac.c

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: clock: Support to reset DCNano and MIPI DSI
Ye Li [Fri, 29 Oct 2021 01:46:27 +0000 (09:46 +0800)]
imx8ulp: clock: Support to reset DCNano and MIPI DSI

When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: clock: Reset DDR controller before clock enable
Ye Li [Fri, 29 Oct 2021 01:46:26 +0000 (09:46 +0800)]
imx8ulp: clock: Reset DDR controller before clock enable

The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: Workaround LPOSC_TRIM fuse load issue
Ye Li [Fri, 29 Oct 2021 01:46:25 +0000 (09:46 +0800)]
imx8ulp: Workaround LPOSC_TRIM fuse load issue

8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.

A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: Remove freescale name from CPU revision
Ye Li [Fri, 29 Oct 2021 01:46:24 +0000 (09:46 +0800)]
imx8ulp: Remove freescale name from CPU revision

Remove the freescale vendor name from CPU revision print to align
with other i.MX platforms

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: Fix DCNANO QoS setting
Ye Li [Fri, 29 Oct 2021 01:46:23 +0000 (09:46 +0800)]
imx8ulp: Fix DCNANO QoS setting

The setting does not have effect because we should set it after
power on the PS16 for NIC AV.

So move it after upower_init which has powered on all PS

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: Set DCNANO read QoS on NIC_LPAV to highest
Ye Li [Fri, 29 Oct 2021 01:46:22 +0000 (09:46 +0800)]
imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest

To avoid DCNANO underrun issue on high loading test, set its
read Qos on NIC_LPAV to highest

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display
Ye Li [Fri, 29 Oct 2021 01:46:21 +0000 (09:46 +0800)]
imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display

The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and
backlight. However the LPI2C0 and TPM0 are M33 resources, in this
patch we simply access them, but this is a temporary solution.
We will modify it when M33 FW changes to set MIPI DSI panel as default
path and enable backlight after reset.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: rdc: allow A35 access flexspi0 mem
Ye Li [Fri, 29 Oct 2021 01:46:20 +0000 (09:46 +0800)]
imx8ulp: rdc: allow A35 access flexspi0 mem

For singel boot, set flexspi0 mem to be accessed by A35

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: clock: Add MIPI DSI clock and DCNano clock
Ye Li [Fri, 29 Oct 2021 01:46:19 +0000 (09:46 +0800)]
imx8ulp: clock: Add MIPI DSI clock and DCNano clock

Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: clock: Support LPAV clocks in cgc and pcc
Ye Li [Fri, 29 Oct 2021 01:46:18 +0000 (09:46 +0800)]
imx8ulp: clock: Support LPAV clocks in cgc and pcc

Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: assign PXP/HIFI4/EPDC to APD domain
Peng Fan [Fri, 29 Oct 2021 01:46:17 +0000 (09:46 +0800)]
imx8ulp: assign PXP/HIFI4/EPDC to APD domain

Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not
able to receive interrupts from the modules.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoarm: imx8ulp: Allocate LPAV resources to AP domain
Ye Li [Fri, 29 Oct 2021 01:46:16 +0000 (09:46 +0800)]
arm: imx8ulp: Allocate LPAV resources to AP domain

When single boot, assign AP domain as the master domain of the LPAV.
Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI
eDMA channel and eDMA request to APD

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoimx8ulp: soc: Check the DBD_EN fuse before setting RDC
Ye Li [Fri, 29 Oct 2021 01:46:15 +0000 (09:46 +0800)]
imx8ulp: soc: Check the DBD_EN fuse before setting RDC

S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC
is allowed by all masters.

Current S400 has issue if the XRDC has released to A35, then A35 reset
will fail in ROM due to S400 fails to get XRDC.
So temp work around is checking the DBD_EN, if it is not fused, we
don't need to call release XRDC or TRDC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2 years agoARM: imx8m: support env in fat and ext4
Ricardo Salveti [Wed, 20 Oct 2021 19:16:26 +0000 (16:16 -0300)]
ARM: imx8m: support env in fat and ext4

Change boot device logic to also allow environment stored in fat and in
ext4 when booting from SD or from eMMC.

As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location
to use IS_ENABLED instead for all modes, returning NOWHERE when no valid
mode is found.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agoimx: nandbcb: Fix printf format in write_fcb
Pali Rohár [Wed, 20 Oct 2021 09:13:15 +0000 (11:13 +0200)]
imx: nandbcb: Fix printf format in write_fcb

Correct printf format for unsigned long long is %llx and not %llxx.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agomxs: power: Change sequence of enabling DCDC switches
Lukasz Majewski [Wed, 13 Oct 2021 13:40:12 +0000 (15:40 +0200)]
mxs: power: Change sequence of enabling DCDC switches

The imx28 uses following voltage supplies hierarchy:

VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM
     \-----> VDDD

One shall first enable DCDC on the parent source (VDDIO) and then
follow with its children.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agoimx8mm-venice-gw7902: fix M2_RST# gpio pinmux
Tim Harvey [Wed, 6 Oct 2021 20:13:23 +0000 (13:13 -0700)]
imx8mm-venice-gw7902: fix M2_RST# gpio pinmux

Fix the invalid gw7902 M2_RST# gpio pinmux.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agomx7ulp_com: add support for SPL
Ricardo Salveti [Sun, 12 Sep 2021 14:32:57 +0000 (17:32 +0300)]
mx7ulp_com: add support for SPL

Add EA iMX7ULP COM board support for building SPL.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2 years agomx7ulp: select soc features
Oleksandr Suvorov [Sun, 12 Sep 2021 14:32:55 +0000 (17:32 +0300)]
mx7ulp: select soc features

Force selecting features present in SoC i.MX7ULP.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2 years agoarm: imx: imx8mq: add support to get values for more clocks
Heiko Thiery [Thu, 9 Sep 2021 12:59:18 +0000 (14:59 +0200)]
arm: imx: imx8mq: add support to get values for more clocks

Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK,
MXC_UART_CLK and MXC_QSPI_CLK.

At least for the I2C clock the missing support leads to a wrong
configured I2C frequency. The expected value is 100kHz but the resulting
value is about 1MHz.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2 years agocolibri-imx7: improve env badblock management
Francesco Dolcini [Wed, 1 Sep 2021 07:48:03 +0000 (09:48 +0200)]
colibri-imx7: improve env badblock management

Use the complete 512kb (4 blocks) nand partition reserved for u-boot
environment instead of just the first block, this allows the module
to have a working environment even if 3 blocks are bad.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2 years agoMerge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Tom Rini [Fri, 4 Feb 2022 04:20:20 +0000 (23:20 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

This is the promised second part of the sunxi PR for 2022.04, albeit
technially outside of the merge window. We were working on this full
steam since the beginning of the year, and it deserves to be merged,
I think.
The main attraction is support for the F1C100s SoC, which sports a
venerable ARM926 core. Support for this SoC and the LicheePi Nano board
has been in Linux for years, and U-Boot patches were posted mid last
year already.
The new SoC using ARMv5 also means that the bulk of the new code should
not touch any existing boards, although we did some refactorings first,
of course, which actually cleans up some existing sunxi code.

Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1,
OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards,
including F1C100s and F1C200s devices.

2 years agoconfigs: sunxi: Add support for Lichee Pi Nano
Icenowy Zheng [Sat, 29 Jan 2022 15:23:09 +0000 (10:23 -0500)]
configs: sunxi: Add support for Lichee Pi Nano

The Lichee Pi Nano is a board based on the F1C100s.
Add defconfigs for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoARM: dts: suniv: Add device tree files and bindings for F1C100s
Icenowy Zheng [Sat, 29 Jan 2022 15:23:08 +0000 (10:23 -0500)]
ARM: dts: suniv: Add device tree files and bindings for F1C100s

Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
dt-bindings/dts are synced with 5.16.0

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agomach-sunxi: Add support for SUNIV architecture
Icenowy Zheng [Sat, 29 Jan 2022 15:23:07 +0000 (10:23 -0500)]
mach-sunxi: Add support for SUNIV architecture

Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoconfigs: sunxi: Add common SUNIV header
Icenowy Zheng [Sat, 29 Jan 2022 15:23:06 +0000 (10:23 -0500)]
configs: sunxi: Add common SUNIV header

Adds support for SUNIV and the F1C100s.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: board: Add support for SUNIV
Icenowy Zheng [Sat, 29 Jan 2022 15:23:05 +0000 (10:23 -0500)]
sunxi: board: Add support for SUNIV

Generic Timer Extension is not available on SUNIV.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: Add F1C100s DRAM initial support
Icenowy Zheng [Sat, 29 Jan 2022 15:23:04 +0000 (10:23 -0500)]
sunxi: Add F1C100s DRAM initial support

Add support for F1C100s internal dram controller.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoARM: sunxi: Add clock and uart to sunxi headers
Icenowy Zheng [Sat, 29 Jan 2022 15:23:03 +0000 (10:23 -0500)]
ARM: sunxi: Add clock and uart to sunxi headers

This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoarm: arm926ej-s: Add sunxi code
Icenowy Zheng [Sat, 29 Jan 2022 15:23:02 +0000 (10:23 -0500)]
arm: arm926ej-s: Add sunxi code

Some Allwinner SoCs use ARM926EJ-S core.

Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agomach-sunxi: Move timer code to mach folder
Jesse Taube [Sat, 29 Jan 2022 15:23:01 +0000 (10:23 -0500)]
mach-sunxi: Move timer code to mach folder

Both armv7 and arm926ejs use this timer code so move it to mach-sunxi.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoarm: arm926ej-s: start.S: port save_boot_params support from armv7 code
Icenowy Zheng [Sat, 29 Jan 2022 15:23:00 +0000 (10:23 -0500)]
arm: arm926ej-s: start.S: port save_boot_params support from armv7 code

The ARMv7 start code has support for saving some boot params at the
entry point, which is used by some SoCs to return to BROM.

Port this to ARM926EJ-S start code.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi-common.h: remove pointless #ifdefs
Andre Przywara [Sun, 23 Jan 2022 00:30:29 +0000 (00:30 +0000)]
sunxi-common.h: remove pointless #ifdefs

Remove some pointless #ifdefs from this file, as there are quite too
many of them already.

Some definitions don't really hurt to have in any case, so remove the
pointless CONFIG_MMC guard around CONFIG_MMC_SUNXI_SLOT.

The BOARD_SIZE_LIMIT applies regardless of ARM64 or not (now), so remove
that guard as well. The maximum number of MMC devices does not depend on
CONFIG_ENV_IS_IN_MMC, so move that out to simplify the file.

Last but not least CONFIG_SPL_BOARD_LOAD_IMAGE serves no real purpose
anymore: it's unconditionally defined for all sunxi boards, and protects
nothing applicable outside of sunxi code anymore. Just remove it.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoarmv8: remove no longer needed lowlevel_init.S
Andre Przywara [Sun, 23 Jan 2022 00:31:06 +0000 (00:31 +0000)]
armv8: remove no longer needed lowlevel_init.S

When we added Allwinner SoC support to ARMv8, we needed to pull in an
implementation of lowlevel_init() calling the C function s_init(), as
sunxi required it as this time.

The last few patches got rid of this bogus requirement, and as sunxi was
still the only user, we can now remove this lowlevel_init.S from ARMv8
altogether.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2 years agosunxi: move early "SRAM setup" into separate file
Andre Przywara [Sun, 23 Jan 2022 00:28:43 +0000 (00:28 +0000)]
sunxi: move early "SRAM setup" into separate file

Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied
from the original BSP U-Boot. The comment speaks of this being required
before DRAM access gets enabled, but there is no indication that this
would actually be required that early.

Move this out of s_init(), into board_init_f(). Since this actually only
affects a very few older SoCs, the actual code goes into the cpu/armv7
directory, to move it out of the way for all other SoCs.

This also uses the opportunity to convert some #ifdefs over to the fancy
IS_ENABLED() macros used in actual C code.

We keep the s_init() stub around for now, since armv8's lowlevel_init
still relies on it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2 years agosunxi: move Cortex SMPEN setting into start.S
Andre Przywara [Sun, 23 Jan 2022 00:27:19 +0000 (00:27 +0000)]
sunxi: move Cortex SMPEN setting into start.S

According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.

This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).

In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.

This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agosunxi: move non-essential code out of s_init()
Andre Przywara [Sat, 22 Jan 2022 10:05:12 +0000 (10:05 +0000)]
sunxi: move non-essential code out of s_init()

So far all Allwinner based boards were doing some not-so-lowlevel-setup
in lowlevel's s_init() routine.
This includes the initial clock, timer and pinmux setup, among other
things. This is clearly out of the "absolute bare minimum to get started"
scope that lowlevel_init.S suggests for this function.

Since we have an SPL, which is called right after s_init(), move those
calls to our board_init_f() function. As we overwrite this only for
the SPL, this has the added benefit of not doing this setup *again*
shortly afterwards, when running U-Boot proper.

This makes gpio_init() to be called from the SPL only, so pull this code
into a CONFIG_SPL_BUILD protected part to avoid build warnings.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoMerge branch '2022-02-03-assorted-fixes'
Tom Rini [Thu, 3 Feb 2022 20:55:02 +0000 (15:55 -0500)]
Merge branch '2022-02-03-assorted-fixes'

- Update CI image to have libgnutls available.
- Assorted ARM and SPL bugfixes

2 years agotreewide: Use 16-bit Unicode strings
Simon Glass [Sun, 23 Jan 2022 19:55:14 +0000 (12:55 -0700)]
treewide: Use 16-bit Unicode strings

At present we use wide characters for Unicode but this is not necessary.
Change the code to use the 'u' literal instead. This helps to fix build
warnings for sandbox on the Raspberry Pi.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2 years agoefi: Use 16-bit unicode strings
Simon Glass [Sun, 23 Jan 2022 19:55:12 +0000 (12:55 -0700)]
efi: Use 16-bit unicode strings

At present we use wide characters for unicode but this is not necessary.
Change the code to use the 'u' literal instead. This helps to fix build
warnings for sandbox on rpi.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2 years agoscripts/checkpatch.pl: Resync with v5.16
Simon Glass [Sun, 23 Jan 2022 19:55:11 +0000 (12:55 -0700)]
scripts/checkpatch.pl: Resync with v5.16

This resyncs us with the version found in v5.16 of the Linux kernel with
the following exceptions:
- Keep our u-boot specific tests / code area.
- Change the location of checkpatch.rst
- Drop the "use strscpy" test as we don't have that, but do have strlcpy
  and want that used now.
- Keep debug/printf in the list for $logFunctions

This also syncs the spdxcheck.py tool and all the associated
documentation.
S
Signed-off-by: Simon Glass <sjg@chromium.org>
2 years agoarmv8: start.S: remove CONFIG_SYS_RESET_SCTRL code
Andre Przywara [Mon, 24 Jan 2022 17:17:40 +0000 (17:17 +0000)]
armv8: start.S: remove CONFIG_SYS_RESET_SCTRL code

There is some code that tries to "reset" the SCTLR_ELx register early in
the boot process. The idea seems to be to guarantee some sane settings
that U-Boot actually relies on, for instance running in little-endian
mode, with the MMU off initially.
However the current code has multiple problems:
- For a start, no platform or config defines the symbol that would
  enable that code.
- The code itself really only works if the bits that it tries to clear
  are already cleared:
  - If we run in big-endian mode initially, any previous loads would have
    been wrong already. That applies to the (optional) relocation code,
    but more prominently to the mask that it uses to clear those bits:
    "ldr x1, =0xfdfffffa" looks innocent, but actually involves a memory
    access to the literal pool, using the current endianness.
  - If we run with the MMU enabled, we are probably doomed already. We
    *could* hope that we are running with an identity mapping, but would
    need to do some cache maintenance to avoid losing dirty cache lines.
- The idea of doing a read-modify-write of SCTLR is somewhat
  questionable to begin with, because as the owner of the current
  exception level we should initialise all bits of this register with a
  certain fixed value.
- The code is unnecessarily complicated, and the function name is
  misspelled.

While those problems *could* admittedly be fixed, the point that is does
not seem to be used at all at the moment tells me we should just remove
this code, and be it to not give a bad example.

If people care, I could introduce some proper SCTLR initialisation code.
We are about to work this out for the boot-wrapper[1] as we speak, but
apparently we got away without doing this in U-Boot ever since, so it
might not be worth the potential trouble.

[1] https://lore.kernel.org/linux-arm-kernel/20220114105653.3003399-7-mark.rutland@arm.com/

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2 years agoscripts: Makefile: also clean subdir dtc
Philippe Reynes [Tue, 25 Jan 2022 10:32:20 +0000 (11:32 +0100)]
scripts: Makefile: also clean subdir dtc

Since commit 93b196532254 ("Makefile: Only build dtc if needed"),
the sub directory scripts/dtc is never cleaned.
Adds the directory dtc to subdir to always clean it.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agonet: ti: am65-cpsw: Cleanup resources before jump to kernel
Vignesh Raghavendra [Fri, 28 Jan 2022 05:51:19 +0000 (11:21 +0530)]
net: ti: am65-cpsw: Cleanup resources before jump to kernel

In case fastboot over Ethernet, am65_cpsw_stop() is not called unless
DM_FLAG_OS_PREPARE is set. Without call to am65_cpsw_stop(), DMA
resources are not released thus leading to failures in kernel.
Fix this by adding DM_FLAG_OS_PREPARE flag to am65_cpsw_nuss_port
driver.

Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoarm: pdu001: Exend the list of maintained files
Felix Brack [Fri, 28 Jan 2022 13:36:12 +0000 (14:36 +0100)]
arm: pdu001: Exend the list of maintained files

Add the PDU001 board specific DT files to MAINTAINERS. This should
help for better tracking of changes to these files.

Signed-off-by: Felix Brack <fb@ltec.ch>
2 years agoarmv8: spl: Fix build with LINUX_KERNEL_IMAGE_HEADER
Alper Nebi Yasak [Sat, 29 Jan 2022 15:27:03 +0000 (18:27 +0300)]
armv8: spl: Fix build with LINUX_KERNEL_IMAGE_HEADER

Setting LINUX_KERNEL_IMAGE_HEADER=y attempts to include an ARM64 Linux
kernel image header at the start of both U-Boot proper and SPL binaries.
However, some definitions that the image header uses are not included by
the SPL linker script, resulting in a build error. Include them the way
they are included in U-Boot proper's linker script to fix the error.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2 years agospl: ymodem: Fix buffer overflow during Image copy
Vignesh Raghavendra [Mon, 31 Jan 2022 04:19:19 +0000 (09:49 +0530)]
spl: ymodem: Fix buffer overflow during Image copy

ymodem_read_fit() driver will end copying up to BUF_SIZE boundary even
when requested size of copy operation is less than that.
For example, if offset = 0, size = 1440B, ymodem_read_fit() ends up
copying 2KB from offset = 0, to destination buffer addr

This causes data corruption when malloc'd buffer is passed during UART
boot since commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer
for loading images")

With this, UART boot works again on K3 (AM654, J7, AM64) family of
devices.

Fixes: 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2 years agoDockfile, CI: Update to latest focal tag and build
Tom Rini [Thu, 3 Feb 2022 13:38:34 +0000 (08:38 -0500)]
Dockfile, CI: Update to latest focal tag and build

- Latest focal tag
- Add libgnutls to image

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoDockerfile: Add libgnutls package for building mkeficapsule command
AKASHI Takahiro [Tue, 1 Feb 2022 01:32:36 +0000 (10:32 +0900)]
Dockerfile: Add libgnutls package for building mkeficapsule command

For adding signing feature for capsule authentication to the host tool,
mkeficapsule, we will link gnutls library for crypto operation.
Since we need this command to complete the capsule authentication test
on sandbox in CI loop, necessary packages must be installed on the host.

See my patch, "tools: mkeficapsule: add firmware image signing."

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Tom Rini [Wed, 2 Feb 2022 14:16:49 +0000 (09:16 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Update and fixes for ls1088a, FMAN, ls1046ardb, ls1043ardb
sync ls1028ardb u-boot and Linux device-tree

2 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash
Tom Rini [Tue, 1 Feb 2022 15:54:52 +0000 (10:54 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash

- cfi_mtd: populate mtd->dev with flash_info->dev (Patrice)

2 years agomtd: cfi_mtd: populate mtd->dev with flash_info->dev
Patrice Chotard [Fri, 3 Dec 2021 09:27:44 +0000 (10:27 +0100)]
mtd: cfi_mtd: populate mtd->dev with flash_info->dev

Populate mtd->dev with flash_info->dev which allows to get
full mtd information using the "mtd list" command.
Before, "mtd list" command returns :

List of MTD devices:
* nor0
  - type: NOR flash
  - block size: 0x40000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "nor0"

After this patch we get for example:

List of MTD devices:
* nor0
  - device: flash@0
  - parent: spi@40430000
  - driver: cfi_flash
  - path: /soc/spi@40430000/flash@0
  - type: NOR flash
  - block size: 0x40000 bytes
  - min I/O: 0x1 bytes
  - 0x000000000000-0x000004000000 : "nor0"

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: ls1046ardb: force PCI device enumeration
Martin Schiller [Wed, 17 Nov 2021 11:59:20 +0000 (12:59 +0100)]
board: ls1046ardb: force PCI device enumeration

Commit 045ecf899252 ("configs: enable DM_ETH support for LS1046ARDB")
resulted in the PCI bus no longer being implicitly enumerated.

However, this is necessary for the fdt pcie fixups to work.

Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb:
transition to DM_ETH"), pci_init() is now called in the board_init()
routine when CONFIG_DM_ETH is active.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
CC: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoboard: ls1088a: update ifc node name to be memory-controller
Jianpeng Bu [Mon, 31 Jan 2022 13:12:36 +0000 (18:42 +0530)]
board: ls1088a: update ifc node name to be memory-controller

IFC-NOR and QSPI are muxed on SoC.
So disable IFC node in dts if QSPI is enabled or disable QSPI node in dts
in case QSPI is not enabled.
"ifc/nor" will be changed to "memory-controller/nor" in linux. So need to
modify "ifc/nor" to "memory-controller/nor" in fdt_path_offset().

Signed-off-by: Jianpeng Bu <jianpeng.bu@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs: fsl: add missing FMAN/QE_FW_ADDR defines
Camelia Groza [Thu, 13 Jan 2022 13:43:14 +0000 (15:43 +0200)]
configs: fsl: add missing FMAN/QE_FW_ADDR defines

The initial patch had typos that caused four defconfigs to miss the
symbol transition to Kconfig. CONFIG_SYS_QE_FW_ADDR and
CONFIG_SYS_FMAN_FW_ADDR are currently initialized to 0 by default
on these builds, which prevents the firmware from loading.

Add the correct symbols to these defconfigs.

Fixes: a97a071d10d2b ("configs: fsl: migrate FMAN/QE specific defines to Kconfig")
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-qds: declare in-band autoneg for Ethernet ports
Vladimir Oltean [Mon, 3 Jan 2022 12:47:37 +0000 (14:47 +0200)]
arm: dts: ls1028a-qds: declare in-band autoneg for Ethernet ports

The commit in the Fixes: tag below broke traffic through switch ports
where the SERDES protocol requires in-band autoneg and this requirement
isn't described in the device tree: SGMII, QSGMII, USXGMII (with
2500Base-X, in-band autoneg isn't supported).

The LS1028A-QDS boards are not yet ready for syncing their device trees
with Linux, since Ethernet is missing there (but has been submitted):
https://lore.kernel.org/lkml/20211112223457.10599-11-leoyang.li@nxp.com/

When agreement is reached for the Ethernet support in Linux, there will
be a sync for these boards as well. For now, just enable in-band autoneg
to fix the breakage.

Fixes: e3789a726269 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-rdb: sync device tree with Linux
Vladimir Oltean [Mon, 3 Jan 2022 12:47:36 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: sync device tree with Linux

Allow device trees to be reused between Linux and U-Boot.
The source for these device trees is linux-next as of commit
bd8a9cd624c6 ("arm64: dts: ls1028a-rdb: update copyright"), which was
chosen because some changes needed to be done to the Linux DTs too,
before they could be shared:
https://lore.kernel.org/linux-arm-kernel/20211202141528.2450169-5-vladimir.oltean@nxp.com/T/#m6f63c92e75fa79a01144b2c2c6dc4776e7971395

There are two more commits on the RDB device tree which haven't been
picked up yet, because they have dependencies on the SoC device tree:

dd3d936a1b17 ("arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source")
b2e2d3e02fb6 ("arm64: dts: ls1028a-rdb: enable pwm0")

These will be picked up on the next resync.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agoarm: dts: ls1028a-rdb: enable PCIe controllers from U-Boot dtsi
Vladimir Oltean [Mon, 3 Jan 2022 12:47:35 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: enable PCIe controllers from U-Boot dtsi

Reuse the scheme implemented by the Kontron SL28 boards in
commit d08011d7f9b4
("arm: dts: ls1028a: disable the PCIe controller by default")
and move the 'status = "okay"' lines for the PCIe controllers
inside a separate U-Boot dtsi for the LS1028A-RDB board. This way, the
existing Linux device tree can simply be dropped in.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-rdb: disable I2C buses 1 through 7
Vladimir Oltean [Mon, 3 Jan 2022 12:47:34 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: disable I2C buses 1 through 7

There is no I2C peripheral on these buses on the reference design board,
and the Linux device tree does not enable them either.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-rdb: disable DSPI nodes
Vladimir Oltean [Mon, 3 Jan 2022 12:47:33 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: disable DSPI nodes

There is no SPI peripheral on the LS1028A-RDB, therefore no reason to
enable these nodes in the U-Boot device tree (and Linux does not enable
them either).

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-rdb: sync Ethernet device tree nodes with Linux
Vladimir Oltean [Mon, 3 Jan 2022 12:47:32 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: sync Ethernet device tree nodes with Linux

In a bit of a blunder, the blamed commit in the Fixes: tag below made
the mscc_felix switch driver look at the 'managed = "in-band-status"'
device tree property, forgetting that the U-Boot device tree had not
been updated to include that property, whereas the Linux one does.

The switch is therefore described in the device tree as not requiring
in-band autoneg, but the PHY driver for VSC8514 (drivers/net/phy/mscc.c)
still enables that feature. This results in a mismatch => no traffic.

This patch is a copy-paste of the Ethernet device tree nodes from Linux,
which resolves that issue. The device tree update also renames the
Ethernet PHY labels.

Fixes: e3789a726269 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-rdb: sort nodes alphabetically
Vladimir Oltean [Mon, 3 Jan 2022 12:47:31 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: sort nodes alphabetically

The nodes in the NXP LS1028A-RDB device tree are out of order, regroup
them alphabetically to have a simple delta when the Linux device tree is
brought in.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agortc: pcf2127: remove U-Boot specific compatible string
Vladimir Oltean [Mon, 3 Jan 2022 12:47:30 +0000 (14:47 +0200)]
rtc: pcf2127: remove U-Boot specific compatible string

Now that all in-tree boards have been converted to the compatible
strings from Linux, delete the support for the ad-hoc "pcf2127-rtc" one.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: lx2160a-rdb: use Linux compatible string for RTC
Vladimir Oltean [Mon, 3 Jan 2022 12:47:29 +0000 (14:47 +0200)]
arm: dts: lx2160a-rdb: use Linux compatible string for RTC

During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LX2160A-RDB to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agoarm: dts: ls1028a-rdb: use Linux compatible string for RTC
Vladimir Oltean [Mon, 3 Jan 2022 12:47:28 +0000 (14:47 +0200)]
arm: dts: ls1028a-rdb: use Linux compatible string for RTC

During this board's sync with Linux device trees, it was observed that
it doesn't use the same compatible string for the RTC node as in U-Boot.
This change makes the RTC compatible strings match, for a smoother sync.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm: dts: ls1028a-qds: use Linux compatible string for RTC
Vladimir Oltean [Mon, 3 Jan 2022 12:47:27 +0000 (14:47 +0200)]
arm: dts: ls1028a-qds: use Linux compatible string for RTC

The LS1028A-QDS board won't be synced with the Linux device trees right
now, since those are currently still in progress (Ethernet is missing).

However, while we're at converting the RDB, it can be observed that the
same RTC is present on the two boards, and the wrong compatible string
is used in both places. This change updates the RTC from the QDS to use
the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agoarm: dts: lx2160a-qds: use Linux compatible string for RTC
Vladimir Oltean [Mon, 3 Jan 2022 12:47:26 +0000 (14:47 +0200)]
arm: dts: lx2160a-qds: use Linux compatible string for RTC

During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LX2160A-QDS to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agoarm: dts: ls1088a-rdb: use Linux compatible string for RTC
Vladimir Oltean [Mon, 3 Jan 2022 12:47:25 +0000 (14:47 +0200)]
arm: dts: ls1088a-rdb: use Linux compatible string for RTC

During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LS1088A-RDB to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agoarm: dts: ls1088a-qds: use Linux compatible string for RTC
Vladimir Oltean [Mon, 3 Jan 2022 12:47:24 +0000 (14:47 +0200)]
arm: dts: ls1088a-qds: use Linux compatible string for RTC

During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LS1088A-QDS to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agortc: pcf2127: sync with Linux compatible strings
Vladimir Oltean [Mon, 3 Jan 2022 12:47:23 +0000 (14:47 +0200)]
rtc: pcf2127: sync with Linux compatible strings

Allow this driver to be used by boards which inherit their device trees
from Linux. Compatibility is temporarily retained with the old
compatible string which is U-Boot specific, and will be removed after a
few changes.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoi2c: muxes: pca954x: add PCA9847 variant
Vladimir Oltean [Mon, 3 Jan 2022 12:47:22 +0000 (14:47 +0200)]
i2c: muxes: pca954x: add PCA9847 variant

This seems to be very similar to the already existing PCA9547, save for
the fact that it supports 0.8V and doesn't support 5V. In fact, it is so
similar to the PCA9547 that the NXP LS1028A-RDB board has been driving
this chip using a "nxp,pca9547" compatible string.

Create a new compatible for the PCA9847 (which is the same as in Linux)
and define the same operating parameters for it as for PCA9547.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2 years agopci: layerscape: update the searching compatible of LX2160A PCIe
Hou Zhiqiang [Tue, 7 Dec 2021 10:13:12 +0000 (18:13 +0800)]
pci: layerscape: update the searching compatible of LX2160A PCIe

The current fixup of LX2160A PCIe nodes is based on non-production
rev1 silicon, and in Linux the nodes have been updated for rev2
silicon, so update the searching compatible string to match the
kernel changes. And for compatibility with the rev1 nodes, move
forward the board specific fixup.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoboard: ls1043ardb: force PCI device enumeration
Martin Schiller [Tue, 23 Nov 2021 06:28:00 +0000 (07:28 +0100)]
board: ls1043ardb: force PCI device enumeration

Commit eb1986804d1d ("configs: enable DM_ETH support for LS1043ARDB")
resulted in the PCI bus no longer being implicitly enumerated.

However, this is necessary for the fdt pcie fixups to work.

Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb:
transition to DM_ETH"), pci_init() is now called in the board_init()
routine when CONFIG_DM_ETH is active.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Camelia Groza <camelia.groza@nxp.com>
Acked-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm/ls102xa: use unused scratchrw4 address for post word
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:13:35 +0000 (13:13 +0000)]
km/ls102xa: use unused scratchrw4 address for post word

The SCRATCHRW4 is only used in secure boot scenario that is unsupported by
our design, so this address can be stolen for storing POST status.
The SCRATCHRW4 is initialized to zero at core rest.

Using a DDR address was unfortunate choice, the DDR at boot time has a
random contend and it happens that sometimes is matching POST magic number.
This behavior can lead to undefined POST behavior and u-boot ending in
failbootcmd command.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs/expu1/seli8: limit autoboot stop to space key
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:12:45 +0000 (13:12 +0000)]
configs/expu1/seli8: limit autoboot stop to space key

Make it in a same way as on the other FOXMC products, this also helps to
avoid unwanted stop caused by some terminal servers that are sending junk
on the serial line.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoarm/expu1/seli8: adapt dts NOR partition table to the latest used
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:11:17 +0000 (13:11 +0000)]
arm/expu1/seli8: adapt dts NOR partition table to the latest used

Even not used by u-boot, this has to be inline with the hw and kernel dts.
U-boot partition table is defined by MTDPARTS_DEFAULT Kconfig.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs/expu1: add u-boot update defconfig
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:10:00 +0000 (13:10 +0000)]
configs/expu1: add u-boot update defconfig

This patch adds default defconfig for u-boot update version, the u-boot
update defconfig is a copy of the default (factory) defconfig with:
- adapted text base and environment addresses
- explicit flag that this is a field updated u-boot version

At the time of implementation this version is only used to verify the
update procedure, in future depend on the needs this defconfig can be
extended with additional options.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs/expu1: enable field fail-safe u-boot update
Aleksandar Gerasimovski [Fri, 10 Dec 2021 10:09:18 +0000 (11:09 +0100)]
configs/expu1: enable field fail-safe u-boot update

Field fail-safe u-boot update for pg-wcom-ls102x designs is introduced
with patch: 81fb05e.

This patch enables already added support by:
 - Defining default u-boot build as bootpackage (factory) image.
 - Defining u-boot update image location according to the EXPU1 NOR layout.
 - Extending mtd partitions according defined EXPU1 NOR layout.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs: expu1: enable ver envvar for version_string
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:08:11 +0000 (13:08 +0000)]
configs: expu1: enable ver envvar for version_string

This is used by out ESW for reading u-boot build version.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs: seli8: enable ver envvar for version_string
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:07:20 +0000 (13:07 +0000)]
configs: seli8: enable ver envvar for version_string

This is used by out ESW for reading u-boot build version.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm/ls102xa: fix device disable configuration
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:06:31 +0000 (13:06 +0000)]
km/ls102xa: fix device disable configuration

This was probably broken when mainlining, CONFIG_FSL_DEVICE_DISABLE is
not Kconfig but whitelisted.

It's fine to be without flag as this is always enabled for abec1020
(pg-wcom-ls102xa.h)

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs/seli8: add u-boot update defconfig
Aleksandar Gerasimovski [Tue, 16 Nov 2021 13:05:42 +0000 (13:05 +0000)]
configs/seli8: add u-boot update defconfig

This patch adds default defconfig for u-boot update version, the u-boot
update defconfig is a copy of the default (factory) defconfig with:
- adapted text base and environment addresses
- explicit flag that this is a field updated u-boot version

At the time of implementation this version is only used to verify the
update procedure, in future depend on the needs this defconfig can be
extended with additional options.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agoconfigs/seli8: enable field fail-safe u-boot update
Aleksandar Gerasimovski [Fri, 10 Dec 2021 10:09:01 +0000 (11:09 +0100)]
configs/seli8: enable field fail-safe u-boot update

Field fail-safe u-boot update for pg-wcom-ls102x designs is introduced
with patch 81fb05e.

This patch enables already added support by:
 - Defining default u-boot build as bootpackage (factory) image.
 - Defining u-boot update image location according to the SELI8 NOR layout.
 - Extending mtd partitions according defined SELI8 NOR layout.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm/ls102xa: add support for field fail-safe u-boot update
Aleksandar Gerasimovski [Fri, 10 Dec 2021 10:08:44 +0000 (11:08 +0100)]
km/ls102xa: add support for field fail-safe u-boot update

Field fail-safe u-boot update procedure for pg-wcom boards is defined and
implemented by patch: 59b3403.
This patch invokes the update procedure for pg-wcom-ls102x designs during
early misc_init_f execution.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm: common: implement field fail-safe u-boot update
Aleksandar Gerasimovski [Fri, 10 Dec 2021 10:07:53 +0000 (11:07 +0100)]
km: common: implement field fail-safe u-boot update

This patch provides possibility for field fail-safe u-boot updates.
The implementation can be used on all pg-wcom boards that are booting from
parallel NOR flash.

When used in a board design, provided check_for_uboot_update function will
start new u-boot at defined location if updateduboot envvar is set to yes.
With this implementation it is expected that factory programmed u-boot
will always stay as it is, and optionally new u-boot can be safely
programmed by embedded software when the unit is rolled out on the field.

It is expected check_for_uboot_update to be called early in execution
before relocation (*_f) once SoC is basically initialized and environment
can be read, with this possibilities to not be able to fix a u-boot bug by
a u-boot update are reduced to minimum.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm: qrio: add access functions for ebootcount
Aleksandar Gerasimovski [Tue, 16 Nov 2021 12:53:28 +0000 (12:53 +0000)]
km: qrio: add access functions for ebootcount

The EBOOTCNT is a reserved persistent static memory area in QRIO,
and similar to BOOTCNT is intended to be used as boot counter location.

Comparable to BOOTCNT that is reserved for u-boot main bootcount
infrastructure, EBOOTCNT is intended to be used for pg-wcom board
specific purposes (e.g implementing early boot counter for fail-safe
u-boot update).

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm/ls102xa: dbg phy prst depends on piggy presence
Aleksandar Gerasimovski [Tue, 16 Nov 2021 12:51:47 +0000 (12:51 +0000)]
km/ls102xa: dbg phy prst depends on piggy presence

The PHY for the debug interface was placed on the board for the
pg_wcom_ls102x. Hence only when a piggy is plugged, a RJ45 jack
including magnetics is connected to the MDI of the PHY. Without a
piggy the MDI lines are left floating and it does not make sense to
have an active debug PHY.
In case of expu1 an active PHY without a piggy even led to increased
jitter for syncE.

This patch only deactivates the prst line of the debug PHY when a piggy
is detected persent.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm: qrio: add function to read PGY_PRES pin status
Aleksandar Gerasimovski [Tue, 16 Nov 2021 12:50:54 +0000 (12:50 +0000)]
km: qrio: add function to read PGY_PRES pin status

It is necessary to read the status of the PGY_PRES pin
so that u-boot can react accordingly.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachienergy.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm/ls102xa: use qrio selftest_pin for reading selftest
Aleksandar Gerasimovski [Tue, 16 Nov 2021 12:49:46 +0000 (12:49 +0000)]
km/ls102xa: use qrio selftest_pin for reading selftest

QRIO library now supports direct read of the test pin status.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2 years agokm: qrio: add function to read SLFTEST pin status
Aleksandar Gerasimovski [Tue, 16 Nov 2021 12:48:46 +0000 (12:48 +0000)]
km: qrio: add function to read SLFTEST pin status

There is a request from HW designers to use this QRIO pin for detecting
DIC26_SELFTEST status instead of a GPIO pin.
This pin is typically used during production for executing POST tests and
starting test ESW bank.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>