Many users of PCI config read routines tend to ignore the function
ret value, and are only concerned about the contents of *val. Based
on this, pci_hose_read_config_{byte,word}_via_dword should initialize
the *val on dword read error.
Without this fix, for example, we'll go on scanning bus with vendor or
header_type uninitialized. This brings many unnecessary config trials.
Tony Li [Fri, 17 Aug 2007 02:35:59 +0000 (10:35 +0800)]
mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support
The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.
Andy Fleming [Thu, 16 Aug 2007 21:35:02 +0000 (16:35 -0500)]
Add CONFIG_HAS_ETH0 to all boards with TSEC
The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether
to update TSEC1's device-tree node, so we need to add it
to all the boards with TSECs. Do this for 83xx and 86xx, too,
since they will eventually do something similar.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Thu, 16 Aug 2007 20:05:04 +0000 (15:05 -0500)]
Update MPC8544 DS PCI memory map
The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.
So make it use far less IO & memory space and have it use the shared LAW. This
free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed
by each bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 16 Aug 2007 16:01:21 +0000 (11:01 -0500)]
Fix up some fdt issues on 8544DS
It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Niklaus Giger [Thu, 16 Aug 2007 13:16:03 +0000 (15:16 +0200)]
PPC4xx:HCU4/5 cleanup
Minor cleanups to confirm to the u-boot coding style.
Some german expressions -> english.
HCU5 enforces a unique IP adress for a given slot in the rack.
Andy Fleming [Thu, 16 Aug 2007 01:03:44 +0000 (20:03 -0500)]
Don't wait for disconnected TSECs
The TSEC driver's PHY code waits a long time for autonegotiation to
complete, even if the link is down. The PHY knows the link is
down or up before autonegotiation completes, so we can short-circuit
the process if the link is down.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Thu, 16 Aug 2007 01:03:25 +0000 (20:03 -0500)]
Define tsec flag values in config files
The tsec_info structure and array has a "flags" field for each
ethernet controller. This field is the only reason there are
settings. Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Wed, 15 Aug 2007 20:46:46 +0000 (15:46 -0500)]
mpc885ads: Don't define CONFIG_BZIP2.
bzip2 requires a significant chunk of malloc space, and there isn't
enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area
and a downloaded image at 0x400000.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefan Roese [Fri, 22 Jun 2007 15:32:28 +0000 (17:32 +0200)]
ppc7xx: Update CPCI750 board
This small CPCI750 update extends the board specific command
"show_config" to display the Marvell strapping registers and
extends the PCI IDE controller.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
Kim Phillips [Thu, 16 Aug 2007 03:30:19 +0000 (22:30 -0500)]
mpc83xx: remaining 8360 libfdt fixes
PCI clocks and QE frequencies weren't being updated, and the core clock
was being updated incorrectly. This patch also adds a /memory node if
it doesn't already exist prior to update.
plus some cosmetic trimming to single line comments.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Jerry Van Baren [Wed, 15 Aug 2007 15:13:15 +0000 (11:13 -0400)]
Fix where the #ifdef CFG_BOOTMAPSZ is placed.
Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb
interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT)
when it should have gone inside of the conditional. As a result, it
broke non-LIBFDT board builds.
Also added a missing "not." to the comment.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Ed Swarthout [Tue, 14 Aug 2007 19:06:45 +0000 (14:06 -0500)]
Fix malloc size error in ahci_init_one.
Typically this causes scsi init to corrupt the
devlist and break the coninfo command.
Fix a compiler size warning.
Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Tue, 14 Aug 2007 15:32:59 +0000 (10:32 -0500)]
Fix initrd/dtb interaction
The original code would wrongly relocate the blob to be right before
the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ,
if it is defined. So we make two changes:
1) flag the blob for relocation whenever its address is above BOOTMAPSZ
2) If the blob is being relocated, relocate it before kbd, not initrd
Signed-off-by: Andy Fleming <afleming@freescale.com>
Stefan Roese [Tue, 14 Aug 2007 12:41:55 +0000 (14:41 +0200)]
POST: Add option for external ethernet loopback test
When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
is not done using an internal loopback connection, but by assuming
that an external loopback connector is plugged into the board.
Peter Pearse [Tue, 14 Aug 2007 09:10:52 +0000 (10:10 +0100)]
Add MACH_TYPE records for several AT91 boards.
Merge to two at45.c files into a common file, split to at45.c and spi.c
Fix spelling error in DM9161 PHY Support.
Initialize at91rm9200 board (and set LED).
Add PIO control for at91rm9200dk LEDs and Mux.
Change dataflash partition boundaries to be compatible with Linux 2.6.
Signed-off-by: Peter Pearse <peter.pearse@arm.com>
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
Randy Vinson [Wed, 28 Feb 2007 02:42:22 +0000 (19:42 -0700)]
85xxCDS: Add make targets for legacy systems.
The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.
Haiying Wang [Tue, 19 Jun 2007 18:18:32 +0000 (14:18 -0400)]
Empirically set cpo and clk_adjust for mpc85xx DDR2 support
This patch is against u-boot-mpc85xx.git of www.denx.com
Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.
Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Andy Fleming [Mon, 13 Aug 2007 19:49:59 +0000 (14:49 -0500)]
MPC85xx BA bits not set for 3-bit bank address DIMM
The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).
Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
Andy Fleming [Mon, 13 Aug 2007 19:38:06 +0000 (14:38 -0500)]
Fix minor 85xx warnings
Some patches had inserted warnings into the build:
* mpc8560ads declared data without using it
* cpu_init declared ecm and immap without using it in all CONFIGs
* MPC8548CDS.h had its default filenames changed so that they contained
"\m" in the paths. Made the defaults not Windows-specific (or
anything-specific)
Signed-off-by: Andy Fleming <afleming@freescale.com>
Ed Swarthout [Fri, 27 Jul 2007 06:50:51 +0000 (01:50 -0500)]
8544ds PCIE support
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
Enable LBC and ECM errors and clear error registers.
Add tftpflash env var to get uboot from tftp server and flash it.
Add pci/pcie convenience env vars to display register space:
"run pcie3regs" to see all pcie3 ccsr registers
"run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h
Enable CONFIG_INTERRUPTS.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Tue, 14 Aug 2007 06:34:21 +0000 (01:34 -0500)]
85xx start.S cleanup and exception support
From: Ed Swarthout <Ed.Swarthout@freescale.com>
Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.
Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.
Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl
Move additional code from .text to boot page to make room for
exception vectors at start of image.
Handle Machine Check, External and Critical exceptions.
Fix e500 machine check error determination in traps.c
TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Calculate the data timeout based on values from the CSD instead of
just using a hardcoded DTOR value. This is a backport of a similar fix
in BSP 2.0, with one additional fix: the DTOCYC value is rounded up
instead of down.
include/asm-avr32/div64.h was recently moved to include/div64.h, but
cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of
the patch was merged perhaps?)
This patch updates cpu/at32ap/interrupts.c so that the avr32 port
compiles again.
Instead of always using the largest blocksize the card supports, check
if it can support smaller block sizes and use 512 bytes if possible.
Most cards do support this, and other parts of u-boot seem to have
trouble with block sizes different from 512 bytes.
projects / u-boot.git / log