Mike Frysinger [Sun, 12 Oct 2008 02:05:42 +0000 (22:05 -0400)]
Blackfin: implement real write support for OTP
Now that real documentation has been released for the OTP interface and
the on-chip ROM wrt writing/timings, implement support for reading/writing
as well as dumping/locking.
Mike Frysinger [Sun, 1 Jun 2008 05:26:29 +0000 (01:26 -0400)]
Blackfin: respect CONFIG_CLKIN_HALF
As pointed out by Ivan Koryakovskiy, the initialization code was not
actually respecting the CONFIG_CLKIN_HALF option when configuring the
PLL_CTL register.
Mike Frysinger [Sun, 12 Oct 2008 00:30:28 +0000 (20:30 -0400)]
Blackfin: bf533-ezkit: shuffle flash defines a little
Some of the flash defines weren't in the correct location and caused build
problems in some configurations, so let's move types and defines to better
local locations.
Mike Frysinger [Mon, 6 Oct 2008 08:16:47 +0000 (04:16 -0400)]
Blackfin: overhaul i2c driver
The current Blackfin i2c driver does not work properly with certain devices
due to it breaking up transfers incorrectly. This is a rewrite of the
driver and relocates it to the newer place in the source tree.
Also remove duplicated I2C speed defines in Blackfin board configs and
disable I2C slave address usage since it isn't implemented.
Mike Frysinger [Mon, 6 Oct 2008 07:35:44 +0000 (03:35 -0400)]
Blackfin: fix dcache handling when doing dma memcpy's
Our dcache invalidate function doesn't just invalidate, it also flushes.
So rename the function accordingly and fix the dma_memcpy() function so it
doesn't inadvertently corrupt the data destination.
Kim Phillips [Tue, 27 Jan 2009 22:03:53 +0000 (16:03 -0600)]
mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 build
extend commit c70564e6b1bd08f3230182392238907f3531a87e
"NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency
to the simpc8313 build and fix this:
...Large Page NAND...Configuring for SIMPC8313 board...
nand_boot_fsl_elbc.o: In function `nand_boot':
nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache'
make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1
make: *** [nand_spl] Error 2
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Peter Tyser [Wed, 28 Jan 2009 00:03:12 +0000 (18:03 -0600)]
Command usage cleanup
Remove command name from all command "usage" fields and update
common/command.c to display "name - usage" instead of
just "usage". Also remove newlines from command usage fields.
Mike Frysinger [Tue, 27 Jan 2009 21:12:21 +0000 (16:12 -0500)]
SATA: do not auto-initialize during boot
Rather than have the board code initialize SATA automatically during boot,
make the user manually run "sata init". This brings the SATA subsystem in
line with common U-Boot policy.
Rather than having a dedicated weak function "is_sata_supported", people
can override sata_initialize() to do their weird board stuff. Then they
can call the actual __sata_initialize().
Tomasz Figa [Tue, 30 Dec 2008 17:35:57 +0000 (18:35 +0100)]
jffs2: Fix zero sector_size when not using CONFIG_JFFS2_CMDLINE
This patch fixes a bug (?) introduced after inclusion of the new
JFFS2 code.
When not using CONFIG_JFFS2_CMDLINE, the code in cmd_jffs2.c doesn't
fill in part->sector_size (keeping it as 0), but a correct value is
needed by the code in jffs2_1pass.c. This causes all JFFS2 accesses
to be in the same place of the memory, what obviously means
impossibility to use the JFFS2 partition.
This problem is fixed in this patch by including sector size
calculation in non-CONFIG_JFFS2_CMDLINE mtdparts_init variant.
Signed-off-by: Tomasz Figa <tomasz.figa_at_gmail.com>
Mike Frysinger [Tue, 30 Dec 2008 07:59:25 +0000 (02:59 -0500)]
saveenv: standardize enablement
Rather than special casing each environment type for enabling the saveenv
command, have them all behave the same. This avoids bitrot as new env
sources are added/removed.
Andrew Dyer [Mon, 29 Dec 2008 23:36:01 +0000 (17:36 -0600)]
soft_i2c.c add option for repeated start in i2c_read()
This patch adds a #define to optionally change the behaviour of
i2c_read() in soft_i2c.c to send an I2C repeated start instead of a
stop-start between sending the device address pointer write and
reading back the data. The current behaviour is retained as the
default.
While most devices will work either way, I have a smart battery(*)
that requires repeated start, and someone at some point found a
device that required a stop-start.
Matthias Fuchs [Fri, 2 Jan 2009 14:11:41 +0000 (15:11 +0100)]
Fix gunzip in case of insufficient output buffer
U-Boot's gunzip() function does not handle the return code
of zlib's inflate() function correctly. gunzip() is implemented
to uncompress all input data in one run. So the correct return
code for the good case is Z_STREAM_END. In case of insufficient
output buffer memory inflate returns Z_OK. For gunzip() this
is an error.
It also makes sense to me to call inflateEnd() also in case
of an error.
Stefan Roese [Wed, 21 Jan 2009 16:20:20 +0000 (17:20 +0100)]
MIPS: Add flush_dcache_range() and invalidate_dcache_range()
This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Added flash_fixup_stm to fix geometry reversal on STMicro M29W320ET flash chip.
Modeled after flash_fixup_amd, this patch handles the geometry reversal
or erase sectors that exist for ST Micro (now Numonyx) M29W320ET flash.
Since I cannot test all STM's chips, the detection is implemented as
narrow as possible for now.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Stefan Roese <sr@denx.de>
Matthias Fuchs [Fri, 2 Jan 2009 11:19:47 +0000 (12:19 +0100)]
ppc4xx: Remove CONFIG_SYS_IGNORE_405_UART_ERRATA_59 from config files
Lot's of 405 board config files use CONFIG_SYS_IGNORE_405_UART_ERRATA_59.
Either they define or undef it. Because it's not used in any source
files this patch removes any references to it.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
Mike Frysinger [Tue, 30 Dec 2008 08:15:38 +0000 (03:15 -0500)]
easylogo: add optional gzip support
Some images can be quite large, so add an option to compress the
image data with gzip in the U-Boot image. Then at runtime, the
board can decompress it with the normal zlib functions.
Bryan Wu [Sat, 3 Jan 2009 01:47:45 +0000 (20:47 -0500)]
fat: fix unaligned errors
A couple of buffers in the fat code are declared as an array of bytes.
But it is then cast up to a structure with 16bit and 32bit members.
Since GCC assumes structure alignment here, we have to force the
buffers to be aligned according to the structure usage.
Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Brad Bozarth [Fri, 2 Jan 2009 03:45:47 +0000 (22:45 -0500)]
spi flash: fix crash due to spi flash miscommunication
Higher spi flash layers expect to be given back a pointer that was
malloced so that it can free the result, but the lower layers return
a pointer that is in the middle of the malloced memory. Reorder the
members of the lower spi structures so that things work out.
Yuri Tikhonov [Sat, 20 Dec 2008 11:54:21 +0000 (14:54 +0300)]
FPU POST: fix warnings when building with 2.18 binutils
When compile u-boot with the 2.18 binutils the following
warning messages for each object file in post/lib_ppc/fpu/ is
produced at the linking stage:
post/libpost.a(acc1.o) uses hard float, u-boot uses soft-float
...
This is because of the fact that, in general, the soft-float and
hard-float ABIs are incompatible; the 2.18 binutils do checking
of the Tag_GNU_Power_ABI_FP attribute of the files to be linked, and
produce the worning like above if these are not compatible.
The incompatibility of ABIs is concerned only the float values:
e.g. the soft-float ABI assumes the float argument passing in the
pair of rX registers, and the hard-float ABI assumes passing of
the float argument in the fX register. When we don't pass the float
arguments between the functions compiled with different floatness,
then such an application will work correctly.
This is the case for the FPU POST: u-boot (compiled with soft-float)
doesn't pass to (and doesn't get from) the FPU POST functions any
floats; there are no functions exported from the post/lib_ppc/fpu/
objects which would work with float parameters/returns too. So, we
can reassure the linker not to worry about the difference in ABI
attributes of linking files just by setting the 'soft-float'
attribute for the objects in post/lib_ppc/fpu. And this patch does
this.
Also, to avoid passing both soft- and hard-float options in CFLAGS
when compiling the files from post/lib_ppc/fpu (which is OK, but
looks rather dirty) this patch removes the soft-float string from
CFLAGS in post/lib_ppc/fpu/Makefile.
Peter Tyser [Wed, 17 Dec 2008 22:36:22 +0000 (16:36 -0600)]
Add support for Maxim's DS4510 I2C device
Initial support for the DS4510, a CPU supervisor with
integrated EEPROM, SRAM, and 4 programmable non-volatile
GPIO pins. The CONFIG_DS4510 define enables support
for the device while the CONFIG_CMD_DS4510 define
enables the ds4510 command. The additional
CONFIG_DS4510_INFO, CONFIG_DS4510_MEM, and
CONFIG_DS4510_RST defines add additional sub-commands
to the ds4510 command when defined.
Dirk Eibach [Tue, 16 Dec 2008 13:51:56 +0000 (14:51 +0100)]
common: Iteration limit for memory test.
The iteration limit is passed to mtest as a fourth parameter:
[start [end [pattern [iterations]]]]
If no fourth parameter is supplied, there is no iteration limit and the
test will loop forever.
Peter Korsgaard [Wed, 10 Dec 2008 15:24:16 +0000 (16:24 +0100)]
common/main: support bootdelay=0 for CONFIG_AUTOBOOT_KEYED
Support bootdelay=0 in abortboot for the CONFIG_AUTOBOOT_KEYED case
similar to the CONFIG_ZERO_BOOTDELAY_CHECK support for the
!CONFIG_AUTOBOOT_KEYED case.
Do this by reversing the loop so we do at least one iteration before
checking for timeout.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Graeme Russ [Sat, 6 Dec 2008 23:29:03 +0000 (10:29 +1100)]
Added MMCR reset functionality
Reset function specific to AMD SC520 microcontroller - Is more of a
'hard reset' that the triple fault.
Requires CONFIG_SYS_RESET_SC520 to be defined in config
I would have liked to add this to a new file (cpu/i386/sc520/reset.c)
but ld requires that a object file in a library arhive MUST contain
at least one function which does not override a weak function (and is
called from outside the object file) in order for that object file to
be extracted from the archive. This would be the only function on the
new file, and hence, will never get linked in.
Graeme Russ [Sat, 6 Dec 2008 23:29:02 +0000 (10:29 +1100)]
Moved generic (triple fault) reset code
Moved from interrupts.c to cpu.c and made into a weak function to
allow vendor specific override
Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be
added to the vendor specific code without the need to remember to
#undef usage of the generic method and if you forget to include your
custom reset method, you will always get the default.
Add a do_div() wrapper, lldiv(). The new inline function doesn't modify
the dividend and returns the result of division, so it is useful
in complex expressions, i.e. "return(a/b)" -> "return(lldiv(a,b))"
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Kumar Gala [Fri, 23 Jan 2009 20:22:13 +0000 (14:22 -0600)]
85xx: Handle eLBC difference w/36-bit physical
The eLBC only handles 32-bit physical address in systems with 36-bit
physical. The previos generation of LBC handled 34-bit physical
address in 36-bit systems. Added a new CONFIG option to convey
the difference between the LBC and eLBC.
Also added defines for XAM bits used in LBC for the extended 34-bit
support.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Haiying Wang [Thu, 15 Jan 2009 16:58:35 +0000 (11:58 -0500)]
Add secondary CPUs processor frequency for e500 core
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Dave Liu [Fri, 21 Nov 2008 08:31:43 +0000 (16:31 +0800)]
fsl-ddr: use the 1T timing as default configuration
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Dave Liu [Fri, 21 Nov 2008 08:31:35 +0000 (16:31 +0800)]
fsl-ddr: make the self refresh idle threshold configurable
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.
If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.
Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
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