Rafal Jaworowski [Fri, 23 Jan 2009 12:27:15 +0000 (13:27 +0100)]
API: Use stack pointer as API signature search hint in the glue layer.
De-hardcode range in RAM we search for the API signature. Instead use the stack
pointer as a hint to narrow down the range in which the signature could reside
(it is malloc'ed on the U-Boot heap, and is hoped to remain in some proximity
from stack area). Adjust PowerPC code in API demo to the new scheme.
Andy Fleming [Thu, 30 Oct 2008 21:41:01 +0000 (16:41 -0500)]
Add MMC Framework
Here's a new framework (based roughly off the linux one) for managing
MMC controllers. It handles all of the standard SD/MMC transactions,
leaving the host drivers to implement only what is necessary to
deal with their specific hardware.
This also hooks the infrastructure into the PowerPC board code
(similar to how the ethernet infrastructure now hooks in)
Some of this code was contributed by Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Thu, 30 Oct 2008 21:31:39 +0000 (16:31 -0500)]
Eliminated arch-specific mmc header requirement
The current MMC infrastructure relies on the existence of an
arch-specific header file. This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Mon, 16 Feb 2009 15:40:20 +0000 (09:40 -0600)]
TQM85xx: Fix a couple warnings in TQM8548 build
The ecm variable in sdram.c was being declared for all 8548, but only
used by specific 8548 boards, so we make that variable require those
specific boards, too
The nand code was using an index "i" into a table, and then re-using "i"
to set addresses for each upm. However, then it relied on the old value
of i still being there to enable things. Changed the second "i" to "j"
Signed-off-by: Andy Fleming <afleming@freescale.com>
MPC85xx: TQM8548: workaround for erratum DDR 19 and 20
This patch adds the workaround for erratum DDR20 according to MPC8548
Device Errata document, Rev. 1: "CKE signal may not function correctly
after assertion of HRESET". Furthermore, the bug DDR19 is fixed in
processor version 2.1 and the work-around must be removed.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
MPC85xx: TQM8548: use cache for AG and BE variants
This patch makes accesses to the system memory cachable by removing the
caching-inhibited and guarded flags from the relevant TLB entries for
the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards
are configured similarly.
This results in a big averall performace improvement. TFTP downloads,
NAND Flash accesses, kernel boots, etc. are much faster.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
MPC85xx: TQM8548: add support for the TQM8548_AG module
The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory,
CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module
with "$ make TQM8548_AG_config".
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
MPC85xx: TQM8548: add support for the TQM8548_BE module
The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN
interface. With NAND support, the image is significantly larger and
TEXT_BASE is adjusted accordingly. U-Boot can be built for this
module with "$ make TQM8548_BE_config".
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
MPC85xx: TQM85xx: make standard PCI/PCI-X configurable
The TQM8548_AG module does not have the standard PCI/PCI-X interface
connected but just the PCI Express interface . So far it was not
possible to disable it without disabling the complete PCI interface
(CONFIG_PCI) including PCI Express.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
MPC85xx: TQM85xx: fix flash protection for boot loader
As the reset vector is located at 0xfffffffc, all flash sectors from the
beginning of the U-Boot binary to 0xffffffff must be protected. On the
TQM8548-AG having small sectors at the end of the flash it happened that
the last two sector were not protected and an "erase all" left an
un-bootable system behind:
Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors
AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E
Erase timeout: 8192 ms, write timeout: 1 ms
Peter Tyser [Fri, 6 Feb 2009 20:30:40 +0000 (14:30 -0600)]
86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output
Peter Tyser [Thu, 5 Feb 2009 17:25:25 +0000 (11:25 -0600)]
86xx: Reset update
Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Kumar Gala [Wed, 11 Feb 2009 05:53:40 +0000 (23:53 -0600)]
fsl-ddr: Allow system to boot if we have more than 4G of memory
Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang. Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
Kumar Gala [Tue, 10 Feb 2009 23:36:15 +0000 (17:36 -0600)]
85xx: print boot header info to distinquish 36-bit addr map on MPC8572 DS
Added some info that is printed out when we boot to distiquish if we
built MPC8572DS_config vs MPC8572DS_36BIT_config since they have
different address maps.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 10 Feb 2009 04:03:04 +0000 (22:03 -0600)]
85xx: Fix bug in device tree setup in 36-bit physical confg
In the 36-bit physical config for MPC8572DS when need the start address
of memory and it size to be kept in phys_*_t instead of a ulong since
we support >4G of memory in the config and ulong cant represent that.
Otherwise we end up seeing the memory node in the device tree reporting
back we have memory starting @ 0 and of size 0.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 10 Feb 2009 04:03:05 +0000 (22:03 -0600)]
85xx: Fix address map for 36-bit config of MPC8572DS
When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map. Additionally, the change to the address
map exposes a small issue in our dummy read on the ULI bus. We need
to use the new mapping functions to handle that read properly in the
36-bit config.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 6 Feb 2009 15:56:35 +0000 (09:56 -0600)]
85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 6 Feb 2009 15:56:34 +0000 (09:56 -0600)]
fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller
If we only have one controller we can completely ignore how
memctl_intlv_ctl is set. Otherwise other levels of code get confused
and think we have twice as much memory.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Abraham, Thomas [Tue, 28 Oct 2008 11:21:31 +0000 (16:51 +0530)]
USB: Remove LUN number from CDB
The LUN number is not part of the Command Descriptor Block (CDB) for scsi inquiry, request sense, test unit ready, read capacity and read10 commands. This patch removes the LUN number information from the CDB.
Signed-off-by: Thomas Abraham <t-abraham@ti.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
V3: Fixed line-wrap problem due to user error in mail!
Added usb_configured() checks in usbtty_puts() and usbtty_putc() to get around a hang
when usb is not connected and the user has set up multi-io (setenv stdout serial,usbtty etc).
Got rid of redundant __attribute__((packed)) directives that were causing warnings from gcc.
i.MX31: Start the I2C clock on driver initialisation
i.MX31 powers on with most clocks running, so, after a power on this explicit
clock start up is not required. However, as Linux boots it disables most clocks
to save power. This includes the I2C clock. If we then soft reboot from Linux
the I2C clock stays off. This breaks the phycore, which has its environment in
I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver
initialisation routine.
Carolyn Smith [Thu, 12 Feb 2009 05:13:44 +0000 (06:13 +0100)]
ppc4xx: Fix initialization of the SDRAM_CODT register
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.
Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Wed, 11 Feb 2009 08:29:33 +0000 (09:29 +0100)]
ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boards
Some AMCC eval boards do have a board_eth_init() function calling
pci_eth_init(). These boards need to call cpu_eth_init() explicitly now
with the new eth_init rework.
Adam Graham [Mon, 9 Feb 2009 21:18:12 +0000 (13:18 -0800)]
ppc4xx: Autocalibration can set RDCC to over aggressive value.
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.
On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".
This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.
The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.
The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration. The default will be the
"T2 Sample" value. A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".
Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.
Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Heiko Schocher [Tue, 10 Feb 2009 08:31:47 +0000 (09:31 +0100)]
8xx serial, smc: add configurable SMC Rx buffer len
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 8xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.
When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.
Mike Frysinger [Fri, 6 Feb 2009 02:04:36 +0000 (21:04 -0500)]
common/{hush, kgdb, serial}.c: build by COBJS-$(...) in Makefile
Move global '#ifdef CONFIG_xxx .... #endif' out of the .c files and into
the COBJS-$(CONFIG_xxx) in the Makefile. Also delete unused var in kgdb
code in the process.
Jerry Van Baren [Fri, 6 Feb 2009 03:18:02 +0000 (22:18 -0500)]
Fix whitespace damage: double space changed to a tab
At some point an intentional double space at the end of the sentence
got changed into a tab in the GPL header line:
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
This patch fixes the damage.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Heiko Schocher [Tue, 10 Feb 2009 08:53:29 +0000 (09:53 +0100)]
cfi: make flash_get_info() non static
If on your board is more than one flash, you must know
the size of every single flash, for example, for updating
the DTS before booting Linux. So make this function
flash_get_info() extern, and you can have all info
about your flashes.
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Andy Fleming [Wed, 4 Feb 2009 00:26:41 +0000 (18:26 -0600)]
tsec: Fix a bug in soft-resetting
SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30
clock cycles, so it's been mostly working. But we had no guarantee, and at
slower bitrates, it's just over a microsecond (over 1000 clock cycles). This
enforces a 2 microsecond gap between assertion and deassertion.
Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Heiko Schocher [Fri, 30 Jan 2009 11:55:38 +0000 (12:55 +0100)]
82xx serial, smc: add configurable SMC Rx buffer len
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN.
With this option it is possible to allow the receive
buffer for the SMC on 82xx to be greater then 1. In case
CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the
old version.
When defining CONFIG_SYS_SMC_RXBUFLEN also
CONFIG_SYS_MAXIDLE must be defined to setup the maximum
idle timeout for the SMC.
Kumar Gala [Fri, 6 Feb 2009 14:08:06 +0000 (08:08 -0600)]
ppc: Fix roll over bug in flush_cache()
If we call flush_cache(0xfffff000, 0x1000) it would never
terminate the loop since end = 0xffffffff and we'd roll over
our counter from 0xfffffe0 to 0 (assuming a 32-byte cache line)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Wed, 4 Feb 2009 00:10:56 +0000 (18:10 -0600)]
mpc8641hpcn: Change PCI MEM pci bus address
Now that the rest of u-boot can support it, change the PCI bus
address of the PCI MEM regions from 0x80000000 to 0xc0000000,
and use the same bus address for both PCI1 and PCI2. This will
maximize the amount of PCI address space left over to map RAM
on systems with large amounts of memory.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Becky Bruce [Wed, 4 Feb 2009 00:10:53 +0000 (18:10 -0600)]
mpc8641hpcn: Clean up PCI mapping concepts
Clean up PCI mapping concepts in the 8641 config - rename _BASE
to _BUS, as it's actually a PCI bus address, separate virtual
and physical addresses into _VIRT and _PHYS, and use each
appopriately.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Becky Bruce [Wed, 4 Feb 2009 00:10:51 +0000 (18:10 -0600)]
powerpc: Move duplicated BAT defines to mmu.h
The BAT fields are architected; there's no need for these to be in
cpu-specific files. Drop the duplication and move these to
include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only
used by the alaska board, and switch to using the BATU_BL_xxx defines
used by all the other boards. The BL_ defines previously in use
had to be shifted into the proper position for use, which was inefficient.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Becky Bruce [Wed, 4 Feb 2009 00:10:50 +0000 (18:10 -0600)]
drivers/pci: Create pci_map_bar function
It is no longer always true that the pci bus address can be
used as the virtual address for pci accesses. pci_map_bar()
is created to return the virtual address for a pci region.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Becky Bruce [Wed, 4 Feb 2009 00:10:49 +0000 (18:10 -0600)]
mpc8641hpcn: Set up outbound pci windows before inbound
Because the inbound pci windows are mapped generously, set up
the more specific outbound windows first. This way, when we
search the pci regions for something, we will hit on the more
specific region. This can actually be a problem on systems
with large amounts of RAM.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Peter Tyser [Wed, 4 Feb 2009 19:39:40 +0000 (13:39 -0600)]
NAND: Silence warning when CONFIG_SYS_NAND_QUIET_TEST
Commit cfa460adfdefcc30d104e1a9ee44994ee349bb7b removed support
for disabling the "No NAND device found!!!" warning when
CONFIG_SYS_NAND_QUIET_TEST was defined. This re-adds support
for silencing the warning.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Coldfire: mcfmii: Allow non-autonegotiating PHYs to use mii command
Modified mii_init to support boards with PHYs that are not set to
autonegotiate, but still want to use u-boot's mii commands to probe
the smi bus. Such PHYs will not set the Autonegotiate-done bit.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Cleanup for M5271EVB:
Added clarification on the use of CONFIG_SYS_CLOCK.
Modified to use u-boot's HUSH parser.
Cleanup on environment settings.
Removed compiler warning by defining CONFIG_SYS_CS0_*
Dependencies:
Added the use of CONFIG_SYS_MCF_SYNCR for clock multiplier.
This depends on a patch to include/asm-m68k/m5271.h
that defines the multiplier and divider ratios.
Removed the definition of CONFIG_SYS_FECI2C.
This depends on a patch that removes the use of it in
cpu/mcf52x2/cpu_init.c
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core list
Added the CONFIG_M5271 to the list of Coldfire V2 processor. This
was causing the bus clock (not CPU clock) to be declared twice as
fast as it actually is. This causes UARTS to operate at half the
specified baudrate.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Dirk Eibach [Tue, 3 Feb 2009 14:15:21 +0000 (15:15 +0100)]
ppc4xx: Make PCIE support selectable
On some platforms PCIE support is not required, but would be included
because the cpu supports it. To reduce fooprint it is now configurable
via CONFIG_PCI_DISABLE_PCIE.
Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Matthias Fuchs [Tue, 3 Feb 2009 21:13:16 +0000 (22:13 +0100)]
ppc4xx: Only fixup opb attached UARTs
This patch updates the fdt UART clock fixup code to
only touch CPU internal UARTs on 4xx systems.
Only these UARTs are definitely clocked by gd->uart_clk.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
Mike Frysinger [Wed, 10 Dec 2008 17:33:54 +0000 (12:33 -0500)]
Blackfin: dynamically update UART speed when initializing
Previously, booting over the UART required the baud rate to be known ahead
of time. Using a bit of tricky simple math, we can calculate the new board
rate based on the old divisors.
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
projects / u-boot.git / log