Michael Walle [Mon, 30 May 2022 21:02:09 +0000 (23:02 +0200)]
board: sl28: support 8 GiB memory
The board supports up to 8 GiB memory. The memory is soldered on the
board but the configuration is equivalent to a dual chip select, dual
rank DIMM module.
Michael Walle [Mon, 30 May 2022 21:02:07 +0000 (23:02 +0200)]
board: sl28: set CPO value
With a 8GiB memory board, it seems that the "very unlikely event" of a
DDR initialization with non-optimal values are not really that unlikely.
It happens in about every other reboot. As described in erratum
A-009942, preset the DEBUG_28 register with an optimal value. The value
iself depends on the memory configuration of the board, but the used
value seems to work well for all variants.
Michael Walle [Mon, 30 May 2022 21:02:05 +0000 (23:02 +0200)]
armv8: layerscape: add missing RCW source defines
A board might need to get the source of the RCW word, which is also the
boot source in most cases.
These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.
Pali Rohár [Thu, 26 May 2022 08:52:27 +0000 (10:52 +0200)]
board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h
Code for changing boot source is platform generic and can be used by any
P1* and P2* compatible RDB board. Not only by boards which use config
header file p1_p2_rdb_pc.h.
So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.
This allows to use code for resetting board and rebooting to other boot
source also by other boards in future.
Pali Rohár [Wed, 11 May 2022 18:27:13 +0000 (20:27 +0200)]
mmc: fsl_esdhc: Add new config option for default fallback mode
Currently default fallback SDHC mode is 1-bit. Add new config option
CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback
mode. This is useful e.g. for SPL builds which loads other parts from SD
card during boot process.
Pali Rohár [Wed, 11 May 2022 18:27:12 +0000 (20:27 +0200)]
mmc: fsl_esdhc: Set fallback mode to 1-bit
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins
shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode
is provided). So 8-bit SDHC mode is really bad default.
When max bus width is not provided then set mode to 1-bit. This mode is
supported by all cards, so it is the best option for fallback mode.
Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card.
Alison Wang [Tue, 10 May 2022 10:29:10 +0000 (18:29 +0800)]
ls1028a: hdp: Add config support for HDP firmware loading
This patch adds config support for HDP firmware loading on LS1028A.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Pali Rohár [Sun, 1 May 2022 15:45:58 +0000 (17:45 +0200)]
powerpc: fsl_law: Add definition for first PCIe target interface
Header file asm/fsl_law.h already provides correct definition for second
and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But
is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1).
Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3
are slightly complicated, but are really correct for P2020 platform.
When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to
conflicting functions like watchdog_reset(). So disable compilation of
mpc85xx watchdog_reset() function when CONFIG_WDT is enabled.
Sean Anderson [Fri, 22 Apr 2022 18:34:19 +0000 (14:34 -0400)]
ARM: dts: ls1021a: update the clockgen node
QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).
This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Fri, 22 Apr 2022 18:34:18 +0000 (14:34 -0400)]
arm: layerscape: Add sfp driver
This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.
The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.
The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.
I suggest using the following procedure for programming:
1. Override the fuses you wish to program
=> fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
=> fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
write-protect bit you will usually want to write it last anyway.
=> fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
=> fuse read 0 2 4
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Peng Fan [Sat, 11 Jun 2022 12:21:01 +0000 (20:21 +0800)]
configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE
CONFIG_SPL_RAW_IMAGE_SUPPORT default y has been used to replace
CONFIG_SPL_ABORT_ON_RAW_IMAGE for quite some time, so drop
CONFIG_SPL_ABORT_ON_RAW_IMAGE.
Peng Fan [Sat, 11 Jun 2022 12:21:00 +0000 (20:21 +0800)]
imx: kontron-sl-mx8mm: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Peng Fan [Sat, 11 Jun 2022 12:20:59 +0000 (20:20 +0800)]
imx: imx8mn_var_som: enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Peng Fan [Sat, 11 Jun 2022 12:20:58 +0000 (20:20 +0800)]
imx: imx8m[m/p]_phycore: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Peng Fan [Sat, 11 Jun 2022 12:20:57 +0000 (20:20 +0800)]
imx: imx8mm_icore: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:56 +0000 (20:20 +0800)]
imx: imx8mm-cl-iot-gate: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart3 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Peng Fan [Sat, 11 Jun 2022 12:20:55 +0000 (20:20 +0800)]
imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #imx8mn_beacon
Add am62x_evm_r5_defconfig for R5 SPL and am62x_evm_a53_defconfig for
A53 SPL and U-Boot support.
To keep the changes to minimum. Only UART And SD boot related configs
are included. This should serve as good starting point for new board
bringup with AM62x.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
[trini: Migrate a number of CONFIG symbols, have re-tested] Tested-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 25 May 2022 08:08:48 +0000 (13:38 +0530)]
arm: dts: Add support for AM62-SK
AM62 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM625 SoC. It supports the following interfaces:
* 2 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 HDMI Port with audio + x1 OLDI/LVDS Display interface for Dual Display
* x1 Headphone Jack
* x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x4 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 20-pin header for Programmable Realtime Unit (PRU) IO pins
* 15-pin CSI header
Add basic support for AM62-SK.
To keep the changes to minimum. Only UART And SD are supported at the
moment. This should serve as good example for adding new board support
based on AM62x SoC
Suman Anna [Wed, 25 May 2022 08:08:47 +0000 (13:38 +0530)]
board: ti: Introduce the basic files to support AM62 SK board
Add basic support for AM62 SK. This has 2GB DDR.
Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from
BSS and does not step on BSS section
Add only the bare minimum required to support UART and SD.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 25 May 2022 08:08:42 +0000 (13:38 +0530)]
arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.
Some highlights of this SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
enabling battery powered system design.
AM625 is the first device of the family. Add DT bindings for the same.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Suman Anna [Wed, 25 May 2022 08:08:40 +0000 (13:38 +0530)]
dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
Add pinctrl macros for AM62x SoCs. These macro definitions are similar
to that of previous platforms, but adding new definitions to avoid any
naming confusions in the SoC dts files.
checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
drivers: mmc: am654_sdhci: Add new compatible for AM62 SoC
The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.
arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.
Masahisa Kojima [Tue, 17 May 2022 08:41:37 +0000 (17:41 +0900)]
spi: synquacer: wait until slave is deselected
synquacer_cs_set() function does not wait the chip select
is deasserted when the driver sets the DMSTOP to deselect
the slave.
This commit checks the Slave Select Released(SRS) bit to wait
until the slave is deselected.
Derald D. Woods [Mon, 16 May 2022 03:25:05 +0000 (22:25 -0500)]
ARM: omap3: evm: Fix 'fitImage' booting
This commit sets two additional variables in the default BOOTCOMMAND.
Adding 'boot=mmc' and 'addr_fit=0x8b000000' removes the need for a
special 'uEnv.txt' to be created. The 'addr_fit' variable is the key
piece here. It is normally defined as 0x90000000, in the macro
DEFAULT_FIT_TI_ARGS. For this OMAP34XX board, 0x8b000000 works without
touching other varibles. This was tested with a 'fitImage' created
using the following FIT source:
Vaishnav Achath [Mon, 9 May 2022 06:20:16 +0000 (11:50 +0530)]
ti: j721e: enable hyperflash spl fixup for j721e
On j721e, its not possible to use OSPI0 and HBMC simultaneously as they
are muxed within the Flash Subsystem hence disable HBMC by default and
keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash
mux selection instead of OSPI.
Also updated detect_enable_hyperflash to use correct GPIO when checking
hypermux selection state:
* J7200 - hypermux sel connected to WKUP_GPIO0_6
* J721E - hypermux·sel·connected·to·WKUP_GPIO0_8
Vaishnav Achath [Mon, 9 May 2022 06:20:13 +0000 (11:50 +0530)]
arm: dts: k3-j721e-common-proc-board: enable hyperflash mux sel GPIO
Add wkup_gpio pinmux setting which will be used for performing the
DT fixup for hbmc node according to mux selection state, on J721E
EVM, hypermux sel is tied to ·WKUP_GPIO0_8.
Add DT node for HyperBus Memory Controller and hbmc-mux in the
FSS. hbmc-am654 driver uses syscon_get_regmap() call which fails
with current compatible setting.
Tom Rini [Thu, 9 Jun 2022 19:20:11 +0000 (15:20 -0400)]
Merge branch '2022-06-09-add-support-for-nvmem-api' into next
To quote the author:
This adds support for the nvmem-cells properties cropping up in manyb
device trees. This is an easy way to load configuration, version
information, or calibration data from a non-volatile memory source. For
more information, refer to patch 6 ("misc: Add support for nvmem
cells").
For the moment I have only added some integration tests using the
ethernet addresses. This hits the main code paths (looking up nvmem
cells) but doesn't test writing. I can add a few stand-alone tests if
desired.
Sean Anderson [Thu, 5 May 2022 17:11:42 +0000 (13:11 -0400)]
test: Load mac address with i2c eeprom
This uses an i2c eeprom to load a mac address using the nvmem interface.
Enable I2C_EEPROM for sandbox SPL since it is the only sandbox config
which doesn't enable it eeprom.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:41 +0000 (13:11 -0400)]
net: Add support for reading mac addresses from nvmem cells
This adds support for reading mac addresses from the "mac-address" nvmem
cell. If there is no (local-)mac-address property, then we will try
reading from an nvmem cell.
For some existing examples of this property, refer to imx8mn.dtsi and
imx8mp.dtsi. Unfortunately, fuse drivers have not yet been converted
to DM.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:39 +0000 (13:11 -0400)]
misc: Add support for nvmem cells
This adds support for "nvmem cells" as seen in Linux. The nvmem device
class in Linux is used for various assorted ROMs and EEPROMs. In this
sense, it is similar to UCLASS_MISC, but also includes
UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding
to a Linux-style nvmem device should be implemented as one of the
previously-mentioned uclasses. The nvmem API acts as a compatibility
layer to adapt the (slightly different) APIs of these uclasses. It also
handles the lookup of nvmem cells.
While nvmem devices can be accessed directly, they are most often used
by reading/writing contiguous values called "cells". Cells typically
hold information like calibration, versions, or configuration (such as
mac addresses).
nvmem devices can specify "cells" in their device tree:
Because nvmem devices are not all of the same uclass, supported uclasses
must register a nvmem_interface struct. This allows CONFIG_NVMEM to be
enabled without depending on specific uclasses. At the moment,
nvmem_interface is very bare-bones, and assumes that no initialization
is necessary. However, this could be amended in the future.
Although I2C_EEPROM and MISC are quite similar (and could likely be
unified), they present different read/write function signatures. To
abstract over this, NVMEM uses the same read/write signature as Linux.
In particular, short read/writes are not allowed, which is allowed by
MISC.
The functionality implemented by nvmem cells is very similar to that
provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does
not seem to have made its way into Linux or into any device tree other
than sandbox. It is possible that with the introduction of this API it
would be possible to remove it.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Thu, 5 May 2022 17:11:38 +0000 (13:11 -0400)]
misc: i2c_eeprom: Add fallbacks
Add some fallback functions for when i2c_eeprom is disabled. This allows
code to reference i2c_eeprom_* functions without needing to check
whether support has been compiled in.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Sean Anderson [Thu, 5 May 2022 17:11:36 +0000 (13:11 -0400)]
net: dsa: Fix segmentation fault if master fails to probe
If the DSA master fails to probe for whatever reason, then DSA devices
will continue on as if nothing is wrong. This can cause incorrect
behavior. In particular, on sandbox, dsa_sandbox_probe attempts to
access the master's private data. This is only safe to do if the master
has been probed first. Fix this by probing the master after we look it
up, and bailing out if we get an error.
Fixes: fc054d563b ("net: Introduce DSA class for Ethernet switches") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Sean Anderson [Thu, 5 May 2022 17:11:35 +0000 (13:11 -0400)]
sandbox: Move some mac addresses to device tree
This prevents some conflicts when running sandbox with -D, since the
"rom" mac address will be random and won't match the environment. We
still need to keep addresses for eth1 and eth6 in the environment,
because dm_test_eth_rotate expects to be able to disable them by
removing their envaddr variables. This can likely be fixed in a future
series by adding a function to cause sandbox eth_opts callback for a
particular mac to fail immediately.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:34 +0000 (13:11 -0400)]
sandbox: Remove eth2addr from environment
DSA interfaces use the same mac address for each interface, unless
instructed otherwise. Just set eth4addr and let eth2addr and eth7addr be
set automatically.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:33 +0000 (13:11 -0400)]
sandbox: net: Remove fake-host-hwaddr
Instead of reading a pseudo-rom mac address from the device tree, just use
whatever we get from write_hwaddr. This has the effect of using the mac
address from the environment (or from the device tree, if it is
specified).
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ramon Fried <rfried.dev@gmail.com>
Sean Anderson [Thu, 5 May 2022 17:11:32 +0000 (13:11 -0400)]
test: eth: Add test for ethernet addresses
This adds a test to make sure that all the ethernet interfaces have
their addresses read properly. At the moment everything is read from the
environment, but the next few commits will add additional sources.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Thu, 5 May 2022 17:11:31 +0000 (13:11 -0400)]
sandbox: net: Add mac address for eth8 to environment
The phy_eth0 interface introduced in commit f3dd213e15 ("net: introduce
helpers to get PHY ofnode from MAC") uses a globally-administered
address. Switch to using a locally-administered address, and add it to
the sandbox environment, like the others.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
This caused the mac address assignment to switch around. Avoid this in
the future by assigning aliases for all ethernet devices. This reverts
the sequence to what it was before the aformentioned commit (with
phy-test-eth as seq 8). There is no ethernet1 for whatever reason.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Tom Rini [Wed, 8 Jun 2022 15:15:28 +0000 (11:15 -0400)]
Merge branch '2022-06-08-virtio-harden-and-test-vring' into next
To quote the author:
Make the virtio ring code resilient against corruption of the buffers
shared with the device.
It follows the example of Linux by keeping a private copy of the
descriptors and metadata for state tracking and only ever writing to the
descriptors that are shared with the device. I was able to test these
hardening steps in the sandbox by simulating device writes to the
queues.
Andrew Scull [Mon, 16 May 2022 10:41:39 +0000 (10:41 +0000)]
virtio: rng: Check length before copying
Check the length of data written by the device is consistent with the
size of the buffers to avoid out-of-bounds memory accesses in case
values aren't consistent.
Signed-off-by: Andrew Scull <ascull@google.com> Cc: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Scull [Mon, 16 May 2022 10:41:38 +0000 (10:41 +0000)]
test: dm: virtio: Test virtio device driver probing
Once the virtio-rng driver has been bound, probe it to trigger the pre
and post child probe hooks of the virtio uclass driver. Check the status
of the virtio device to confirm it reached the expected state.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Scull [Mon, 16 May 2022 10:41:37 +0000 (10:41 +0000)]
virtio: sandbox: Bind RNG rather than block device
The virtio-rng driver is extremely simple, making it suitable for
testing more of the virtio uclass logic. Have the sandbox driver bind
the virtio-rng driver rather than the virtio-blk driver so it can be
used in tests.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot.git / log