Simon Glass [Fri, 17 Jul 2020 14:48:08 +0000 (08:48 -0600)]
x86: Move MP code into mp_init
At present the 'flight plan' for CPUs is passed into mp_init. But it is
always the same. Move it into the mp_init file so everything is in one
place. Also drop the SMI function since it does nothing. If we implement
SMIs, more refactoring will be needed anyway.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 17 Jul 2020 14:48:07 +0000 (08:48 -0600)]
x86: mp_init: Switch to livetree
Update this code to use livetree calls instead of flat-tree.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Stefan Roese [Tue, 30 Jun 2020 10:08:58 +0000 (12:08 +0200)]
mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.
Stefan Roese [Tue, 30 Jun 2020 10:33:17 +0000 (12:33 +0200)]
mips: octeon: use mips_mach_early_init() to copy to L2 cache
This patch adds the code to copy itself from bootrom location to a
different location (TEXT_BASE) to the Octeon platform. Its used in
this case to copy the complete U-Boot image into L2 cache, which
greatly improves the bootup time - especially in regard to the
very long and complex DDR4 init code.
The Kconfig symbol CONFIG_MIPS_MACH_EARLY_INIT is enabled with this
patch for Octeon.
Aaron Williams [Tue, 30 Jun 2020 10:08:56 +0000 (12:08 +0200)]
mips: octeon: Initial minimal support for the Marvell Octeon SoC
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Tue, 30 Jun 2020 10:33:16 +0000 (12:33 +0200)]
mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init code
This patch adds the optional call to mips_mach_early_init() to start.S
at a very early stage. Its disabled per default. It can be used for
very early machine / platform specific init code. Its called very
early and at this stage the PC is allowed to differ from the linking
address (CONFIG_TEXT_BASE) as no absolute jump has been performed until
this call.
It will be used by thje Octeon platform.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
mips: add config options for generic cache setup code
Add an own Kconfig symbol for the initial disabling of caches
invoked from generic start code.
Also add an own Kconfig symbols for the initialization of caches
invoked from generic start code.
Until now both code paths could only be disabled with
CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for
RAM boot scenarios like EJTAG or SPL payload or for machines
which don't require cache initialization or which want to
provide their own cache implementation.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
Since commit 703ec9ddf965 ("MIPS: Stop building position independent code")
the relocation code was completely reworked and removed from start.S.
Remove some left-overs of the old code.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
Stefan Roese [Tue, 30 Jun 2020 10:33:19 +0000 (12:33 +0200)]
mips: cache: Make invalidate_dcache_range() weak to enable overwrite
This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.
Stefan Roese [Thu, 14 May 2020 09:59:04 +0000 (11:59 +0200)]
mips: cache: Make flush_cache() weak to enable overwrite
This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.
Stefan Roese [Fri, 5 Jun 2020 08:29:25 +0000 (10:29 +0200)]
mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usage
This patch changes the R_MIPS_NONE define from 0 to a magic value. This
makes it possible to better detect any forbidden pre-relocation usage
of BSS variables, as they are often zero'ed and then relocation is
stopped too early.
Additionally the error message is improved to also print the faulting
address. This helps finding the root-cause for this breakage by
comparing this address with the values in System.map.
This patch helps a lot when working on pre-relocation code, like the
Octeon DDR init code, where such variables have hit me multiple times
now.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
Stefan Roese [Thu, 14 May 2020 09:59:05 +0000 (11:59 +0200)]
mips: time: Only compile the weak get_tbclk() when needed
This patch opts-out the compilation of get_tbclk() if
CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon
platform, where the weak get_tbclk() function is overwritten by its
platform specific one.
Tom Rini [Fri, 17 Jul 2020 20:08:54 +0000 (16:08 -0400)]
Merge branch '2020-07-17-misc-fixes'
A large number of assorted fixes, including but not limited to:
- Correct fixdep and CONFIG_IS_ENABLED(...)
- lz4 on big endian
- Assorted LMB hardening
- Remove bd_t typedef
Martin Kaistra [Mon, 13 Jul 2020 12:40:02 +0000 (14:40 +0200)]
mtd: mtdpart: use uint64_t instead of int for cur_off
The types of "offset" and "size" of "struct mtd_partition" are uint64_t,
while mtd_parse_partitions() uses int to work with these values. When
the offset reaches 2GB, it is interpreted as a negative value, which
leads to error messages like
mtd: partition "<partition name>" is out of reach -- disabled
eg. when using the "ubi part" command.
Fix this by using uint64_t for cur_off and cur_sz.
Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de> Reviewed-by: Heiko Schocher <hs@denx.de>
Stephen Warren [Wed, 8 Jul 2020 21:45:56 +0000 (15:45 -0600)]
fixdep: fix CONFIG_IS_ENABLED etc. handling
When fixdep detects CONFIG_IS_ENABLED and other similar macros, it must
parse the macro parameter to determine which actual CONFIG_ option is
being referenced. This involves moving a pointer forward through the
entire CONFIG_ option "word". Currently, the code uses variable q to walk
through the word, but doesn't actually initialize it to point at the
parameter before doing so. Consequently, the walking process immediately
fails since it sees the macro invocatoins's ( rather than the expected
alpha-numeric characters in the macro parameter. Fix this by adding the
missing initialization.
Fixes: 67f2ee86ccbe ("kbuild: fixdep: Resync this with v4.17") Fixes: 7012865e961c ("gpio: fix test.py for gpio label lookup") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Since commit 4b0bcfa7c4ec (Kconfig: Migrate CONFIG_BOOTM_* options),
the config_defaults.h file has been void of any actual content - and
these days, "sane defaults for everyone" is achieved by appropriate
default values in Kconfig. Remove it, and thus make every translation
unit process one less header file.
Chin Liang See [Wed, 24 Jun 2020 08:31:08 +0000 (16:31 +0800)]
lib: zlib: Remove offset pointer optimization in inftrees.c
This fixes the CVE-2016-9840. Commit imported from [1].
inftrees.c was subtracting an offset from a pointer to an array,
in order to provide a pointer that allowed indexing starting at
the offset. This is not compliant with the C standard, for which
the behavior of a pointer decremented before its allocated memory
is undefined. Per the recommendation of a security audit of the
zlib code by Trail of Bits and TrustInSoft, in support of the
Mozilla Foundation, this tiny optimization was removed, in order
to avoid the possibility of undefined behavior.
Signed-off-by: Mark Adler <madler@alumni.caltech.edu> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Thomas Schaefer [Tue, 16 Jun 2020 20:03:52 +0000 (22:03 +0200)]
spl: fix ext4fs_mount return code handling
- Despite other ext4 filesystem functions, ext4fs_mount returns
0 in case of error.
- This leads to u-boot crash in case that an SD card
with valid partition table but without ext4 filesystem created
in a partition is found on SD card.
- Fix this by returning a proper error code of '-1' from spl_load_image_ext
function in case of ext4fs_mount error.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
[hthiery: slightly reword the commit message] Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tero Kristo [Fri, 12 Jun 2020 12:41:21 +0000 (15:41 +0300)]
cmd: booti: convert the debug print about image move to printf
Moving of the OS image may have some nasty side effects like corrupting
DTB. Convert the current debug print to printf so that the relocation of
the OS is always obvious to the user.
Tero Kristo [Fri, 12 Jun 2020 12:41:20 +0000 (15:41 +0300)]
common: bootm: add checks to verify if ramdisk / fdtimage overlaps OS image
These cases are typically fatal and are difficult to debug for random
users. Add checks for detecting overlapping images and abort if overlap
is detected.
Tero Kristo [Fri, 12 Jun 2020 12:41:19 +0000 (15:41 +0300)]
image: fdt: bail out with error if no boot time FDT image found
Currently the boot continues if the FDT image is clearly corrupted,
which just causes the loaded OS to hang. Abort boot properly if the FDT
is corrupted.
So the magic is ok, but the version check fails, also some reserved
bits are apparently set. But that's because the code interprets the
"flags" and "block_descriptor" bytes wrongly:
Using bit-fields to access individual bits of an "on the wire" format
is not portable, not even when restricted to the C flavour implemented
by gcc. Quoting the gcc manual:
* 'The order of allocation of bit-fields within a unit (C90 6.5.2.1,
C99 and C11 6.7.2.1).'
Determined by ABI.
and indeed, the PPC Processor ABI supplement says
* Bit-fields are allocated from right to left (least to most
significant) on Little-Endian implementations and from left to
right (most to least significant) on Big-Endian implementations.
The upstream code (github.com/lz4/lz4) uses explicit shifts and masks
for encoding/decoding:
/* Flags */
{ U32 const FLG = srcPtr[4];
U32 const version = (FLG>>6) & _2BITS;
blockChecksumFlag = (FLG>>4) & _1BIT;
blockMode = (FLG>>5) & _1BIT;
contentSizeFlag = (FLG>>3) & _1BIT;
contentChecksumFlag = (FLG>>2) & _1BIT;
dictIDFlag = FLG & _1BIT;
/* validate */
if (((FLG>>1)&_1BIT) != 0) return err0r(LZ4F_ERROR_reservedFlag_set); /* Reserved bit */
if (version != 1) return err0r(LZ4F_ERROR_headerVersion_wrong); /* Version Number, only supported value */
}
Do the same here, and while at it, be more careful to use unaligned
accessors to what is most likely unaligned. Also update the comment to
make it clear that it only refers to the lz4.c file, not the following
code of lz4_wrapper.c.
This has been tested partly, of course, by seeing that my
lz4-compressed kernel now boots, partly by running the (de)compression
test-suite in the (x86_64) sandbox - i.e., it should still work just
fine on little-endian hosts.
Reviewed-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes
Tom Rini [Fri, 17 Jul 2020 12:04:28 +0000 (08:04 -0400)]
Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX for 2020.10
----------------
- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM
Simon Glass [Fri, 17 Jul 2020 03:22:38 +0000 (21:22 -0600)]
x86: Rename board_final_cleanup() to board_final_init()
This function sounds like something that is called when U-Boot is about to
jump to Linux. In fact it is an init function.
Rename it to reduce confusion.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Fri, 17 Jul 2020 03:22:37 +0000 (21:22 -0600)]
x86: acpi: Correct the version of the MADT
Currently U-Boot implements version 2 but reports version 4. Correct it.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Fri, 17 Jul 2020 03:22:35 +0000 (21:22 -0600)]
x86: Update the comment about booting for FSP2
The comment here applies only to FSP1, so update it.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Fri, 17 Jul 2020 03:22:34 +0000 (21:22 -0600)]
x86: Store the coreboot table address in global_data
At present this information is used to locate and parse the tables but is
not stored. Store it so that we can display it to the user, e.g. with the
'bdinfo' command.
Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(),
so it is always set when booting from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Fri, 17 Jul 2020 03:22:33 +0000 (21:22 -0600)]
x86: apl: Adjust FSP-M code to avoid hard-coded address
Update this code to calculate the address to use, rather than hard-coding
it. Obtain the requested stack size from the FSP.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 17 Jul 2020 03:22:32 +0000 (21:22 -0600)]
x86: apl: Set the correct boot mode in the FSP-M code
If there is MRC information we should run FSP-M with a different
boot_mode flag since it is supposed to do a 'fast path' through the
memory init. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 17 Jul 2020 03:22:31 +0000 (21:22 -0600)]
x86: Add debugging to table writing
Writing tables is currently pretty opaque. Add a bit of debugging to the
process so we can see what tables are written and where they start/end in
memory.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Fri, 17 Jul 2020 03:22:30 +0000 (21:22 -0600)]
x86: apl: Fix save/restore of ITSS priorities
The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.
Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.
This fixes interrupt handling on coral.
Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:34 +0000 (21:32 -0600)]
x86: irq: Support flags for acpi_gpe
This binding currently has a flags cell but it is not used. Make use of it
to create ACPI tables for interrupts.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:33 +0000 (21:32 -0600)]
pmc: Move common registers to the header file
These registers need to be accesses from ACPI code, so move them to the
header file.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:32 +0000 (21:32 -0600)]
x86: apl: Hide the p2sb on exit from U-Boot
This confuses Linux's PCI probing so needs to be hidden when booting
Linux. Add a remove() method to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:31 +0000 (21:32 -0600)]
x86: apl: Support set_hide() in p2sb driver
Add support for this new method in the driver and in the fsp-s setup.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:30 +0000 (21:32 -0600)]
p2sb: Add a method to hide the bus
The P2SB bus needs to be hidden in some cases so that it does not get
auto-configured by Linux. Add a method for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:29 +0000 (21:32 -0600)]
i2c: designware_i2c: Support ACPI table generation
Update the PCI driver to generate ACPI information so that Linux has the
full information about each I2C bus.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Correct one typo in dw_i2c_gen_speed_config() comments] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:24 +0000 (21:32 -0600)]
x86: Add error checking for csrt table generation
Generation of this table can fail, so update the function to return an
error code.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:23 +0000 (21:32 -0600)]
x86: pinctrl: Drop the acpi_path member
This is in the device tree now, so drop the unnecessary field here.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:22 +0000 (21:32 -0600)]
x86: pinctrl: Set up itss in the probe() method
At present the itss is probed in the ofdata_to_platdata() method. This is
incorrect since itss is a child of p2sb which itself needs to probe the
pinctrl device. This means that p2sb is effectively not probed when the
itss is probed, so we get the wrong register address from p2sb.
Fix this by moving the itss probe to the correct place.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:21 +0000 (21:32 -0600)]
x86: pinctrl: Add multi-ACPI control
Add a Kconfig to control whether pinctrl is represented as a single ACPI
device or as multiple devices. In the latter case (the default) we should
return the pin number relative to the pinctrl device.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:19 +0000 (21:32 -0600)]
x86: pinctrl: Add a way to get the pinctrl reg address
At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:18 +0000 (21:32 -0600)]
sound: Add an ACPI driver for Maxim MAX98357ac
This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Use the correct acpi_irq_polarity enum number] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:17 +0000 (21:32 -0600)]
sound: Add an ACPI driver for Dialog Semicondutor da7219
This chip is used on coral and we need to generate ACPI tables for sound
to make it work. Add a driver that does just this (i.e. at present does
not actually support playing sound).
Simon Glass [Wed, 8 Jul 2020 03:32:16 +0000 (21:32 -0600)]
x86: Add support for building up an NHLT structure
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.
Add functions to allow adding to the structure that is eventually written
to the ACPI tables. Also add the device-tree bindings.
Simon Glass [Wed, 8 Jul 2020 03:32:15 +0000 (21:32 -0600)]
acpi: Support writing named values
Allow writing named integers and strings to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix the "new blank line at EOF" warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:14 +0000 (21:32 -0600)]
acpi: Support generation of a device
Allow writing an ACPI device to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix build failures on Sandbox] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:13 +0000 (21:32 -0600)]
x86: Add bindings for NHLT
Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
(NHLT).
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:12 +0000 (21:32 -0600)]
acpi: mmc: Generate ACPI info for the PCI SD Card
Write required information into the SSDT to describe the SD card
card-detect pin. Since the required GPIO properties are not present in
the device-tree binding, set them manually for now.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:11 +0000 (21:32 -0600)]
acpi: Support generation of a generic register
Allow writing out a generic register.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix build failures on Sandbox] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:10 +0000 (21:32 -0600)]
acpi: Support generation of a scope
Add a function to write a scope to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Fix build failures on Sandbox] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:09 +0000 (21:32 -0600)]
acpi: Export functions to write sized values
At present only acpigen_write_integer() is exported for use by other code.
But in some cases it is useful to call the specific function depending on
the size of the value.
Export these functions and add a test.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Fix the "new blank line at EOF" warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 8 Jul 2020 03:32:08 +0000 (21:32 -0600)]
dm: acpi: Add support for the NHLT table
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.
Add core support for this, based on a structure which is built up through
calls to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:07 +0000 (21:32 -0600)]
dm: core: Add a way of overriding the ACPI device path
Some devices such as GPIO need to override the normal path that would be
generated by driver model. Add a device-tree property for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:06 +0000 (21:32 -0600)]
dtoc: Support ACPI paths in of-platdata
The start of an ACPI path typically has backslashes in it. These are not
preserved during the translation from device tree to C code, since dtc
(correctly) uses the first backslash as an escape character, and dtoc
therefore leaves it out of the C string.
Simon Glass [Wed, 8 Jul 2020 03:32:05 +0000 (21:32 -0600)]
acpi: Allow creating the GNVS to fail
In some cases an internal error may prevent this from working. Update the
function return value and report the error. At present the API for writing
tables does not easily support reporting errors, but once it is fully
updated to use a context pointer, this will be easier.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Wed, 8 Jul 2020 03:32:03 +0000 (21:32 -0600)]
binman: Refactor binman_entry_find() to allow other nodes
At present we can only read from a top-level binman node entry. Refactor
this function to produce a second local function which supports reading
from any node.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 7 Jul 2020 19:12:12 +0000 (13:12 -0600)]
acpi: Add an acpi command to list/dump generated ACPI items
Add a command that shows the individual blocks of data generated by each
device, effectively splitting the full table into its component parts.
This can be helpful for debugging.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 7 Jul 2020 19:12:11 +0000 (13:12 -0600)]
dm: acpi: Enhance acpi_get_name()
For many device types it is possible to figure out the name just by
looking at its uclass or parent. Add a function to handle this, since it
allows us to cover the vast majority of cases automatically.
However it is sometimes impossible to figure out an ACPI name for a device
just by looking at its uclass. For example a touch device may have a
vendor-specific name. Add a new "acpi,name" property to allow a custom
name to be created.
With this new feature we can drop the get_name() methods in the sandbox
I2C and SPI drivers. They were only added for testing purposes. Update the
tests to use the new values.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 7 Jul 2020 19:12:10 +0000 (13:12 -0600)]
pci: Avoid a crash in device_is_on_pci_bus()
This function cannot currently be called on the root node. Add a check
for this as well as a test.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 7 Jul 2020 19:12:09 +0000 (13:12 -0600)]
x86: Allow devices to write to DSDT
Call the new core function to inject ASL programmatically into the DSDT.
This is made up of fragments generated by devices that have the
inject_dsdt() method. The normal, compiled ASL file is added after this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 7 Jul 2020 19:12:08 +0000 (13:12 -0600)]
acpi: Add support for DSDT generation
Some devices need to inject extra code into the Differentiated System
Descriptor Table (DSDT). Add a method to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in inject_dsdt() comments] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 7 Jul 2020 19:12:07 +0000 (13:12 -0600)]
x86: Allow devices to write an SSDT
Call the new core function to write the SSDT. This is made up of fragments
generated by devices that have the fill_ssdt() method.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
projects / u-boot.git / log