Add the new compatible "microchip,24aa02e48" to accommodate 24AA02E48,
the 24AA02E48 is a 2K I2C Serial EEPROM with pre-programmed globally
unique, 48-bit node address, and 8-byte page size.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Rob Clark [Sat, 9 Sep 2017 10:47:42 +0000 (06:47 -0400)]
vsprintf.c: add GUID printing
This works (roughly) the same way as linux's, but we currently always
print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
mostly just because that is what uuid_bin_to_str() supports.
It will be used by a later efi_loader paths for efi variables and for
device-path-to-text protocol, and also quite useful for debug prints
of protocol GUIDs.
Signed-off-by: Rob Clark <robdclark@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Rob Clark [Sat, 9 Sep 2017 10:47:41 +0000 (06:47 -0400)]
vsprintf.c: add UTF-16 string (%ls) support
This is convenient for efi_loader which deals a lot with UTF-16. Only
enabled with CC_SHORT_WCHAR, leaving room to add a UTF-32 version when
CC_SHORT_WCHAR is not enabled.
Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Rob Clark [Sat, 9 Sep 2017 10:47:39 +0000 (06:47 -0400)]
kbuild: Enable -fshort-wchar
EFI_LOADER really wants UTF-16 strings (ie. %ls and L"string" are 16bit
chars instead of 32bit chars). But rather than enabling -fshort-wchar
conditionally if EFI_LOADER is enabled, it was deemed preferrable to
globally switch.
Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
dm: test: replace dm_scan_dt() by of dm_extended_scan_fdt() in dm_do_test
This allows to scan the DT including all "clocks" node's sub-nodes
in which fixed-clock are defined.
All fixed-clock should be defined inside a clocks node which collect all
external oscillators. Until now, all clocks sub-nodes can't be binded except
if the "simple-bus" compatible string is added which is a hack.
Update test.dts by moving clk_fixed node inside clocks.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Currently, all fixed-clock declared in "clocks" node in device tree
can be binded by clk_fixed_rate.c driver only if each of them have
the "simple-bus" compatible string.
This constraint has been invoked here [1].
This patch offers a solution to avoid adding "simple-bus" compatible
string to nodes that are not busses.
[1] https://patchwork.ozlabs.org/patch/558837/
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Chris Packham [Fri, 1 Sep 2017 08:57:53 +0000 (20:57 +1200)]
patman: add support for omitting bouncing addresses
Add support for reading a list of bouncing addresses from a in-tree file
(doc/bounces) and from the ~/.patman config file. These addresses are
stripped from the Cc list.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
Simon Glass [Sun, 13 Aug 2017 22:02:54 +0000 (16:02 -0600)]
moveconfig: Use fd.write() instead of print >>
Adjust this code so that it can work with Python 2 and 3.
Fixes: d73fcb1 (moveconfig: Support building a simple config database) Reported-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 1 Aug 2017 23:33:33 +0000 (16:33 -0700)]
sandbox: Introduce Kconfig option for 32/64 bit host
It seems most of the time we are building and running sandbox on 64-bit host.
But we do support 32-bit host as well. Introduce Kconfig option for this.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
blk: dm: make blk_create_device() take a number of block instead of a size
There is an overflow problem when taking the size instead of the number
of blocks in blk_create_device(). This results in a wrong device size: the
device apparent size is its real size modulo 4GB.
Using the number of blocks instead of the device size fixes the problem and
is more coherent with the internals of the block layer.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Create board/$(VENDOR)/common folder to accommodate the common code
shared by other atmel boards, now put the code to set ethernet mac
address from eeprom, which uses the i2c eeprom driver.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Steve Kipisz [Tue, 22 Aug 2017 08:22:58 +0000 (13:52 +0530)]
board: ti: am571x: Add 666MHz support for AM571x IDK
AM571x supports DDR running at 666MHz. Right now it is
clocked at 532MHz which is lower than what is supported.
In order to have maximum performance on AM571-IDK,
switch DDR to 666MHz.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Mon, 21 Aug 2017 07:21:00 +0000 (12:51 +0530)]
arm: dts: Add u-boot specific compatibles
Separate out u-boot specific compatibles from dts files.
This will help in syncing dts files in future.
Also these will get deleted eventually once respective drivers
are capable of handling Linux dts files.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Mon, 21 Aug 2017 07:20:55 +0000 (12:50 +0530)]
board: ti: dra76-evm: Add DDR data
dra76-evm has the ddr parts connectedi running at 666MHz:
EMIF1: MT41K512M16HA-125 AIT:A x 2
EMIF2: MT41K512M8RH-125-AAT:E x 4
Add support for configuring the above DDR parts.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Praneeth Bajjuri [Mon, 21 Aug 2017 07:20:52 +0000 (12:50 +0530)]
arm: dra76: Add support for ES1.0 detection
dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 1 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN
Adding CPU detection support for the dra76 ES1.0 soc
and update prcm, control module, dplls data.
York Sun [Fri, 8 Sep 2017 16:33:49 +0000 (09:33 -0700)]
armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.
Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
York Sun [Thu, 7 Sep 2017 17:12:32 +0000 (10:12 -0700)]
armv8: fsl-layerscape: Fix MC reserved memory calculation
In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.
Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
Ran Wang [Mon, 4 Sep 2017 10:46:53 +0000 (18:46 +0800)]
armv7: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
Ran Wang [Mon, 4 Sep 2017 10:46:52 +0000 (18:46 +0800)]
armv7: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
Ran Wang [Mon, 4 Sep 2017 10:46:49 +0000 (18:46 +0800)]
armv8: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Thu, 31 Aug 2017 10:42:55 +0000 (16:12 +0530)]
armv8: ls1088aqds: Add support of LS1088AQDS
This patch add support of LS1088AQDS platform.
The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Thu, 31 Aug 2017 10:42:54 +0000 (16:12 +0530)]
armv8: ls1088ardb: Add support for LS1088ARDB platform
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file] Reviewed-by: York Sun <york.sun@nxp.com>
WIP: disable NAND for LS1088ARDB
Ashish Kumar [Thu, 31 Aug 2017 10:42:53 +0000 (16:12 +0530)]
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
Ran Wang [Mon, 28 Aug 2017 02:40:33 +0000 (10:40 +0800)]
armv8: fsl: Use correct conditional compile for ls1012a
According current code base, CONFIG_LS1012A should be
CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
wrongly called to disable all dwc3 USB nodes on LS1012A, which
cause Linux USB function stop working at all.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Priyanka Jain [Thu, 24 Aug 2017 11:12:43 +0000 (16:42 +0530)]
drivers:net:fsl-mc: Update MC address calculation
Update MC address calculation as per MC design requirement of address
as least significant 512MB address of MC private allocated memory,
i.e. address should point to end address masked with 512MB offset in
private DRAM block.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
[YS: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Wed, 16 Aug 2017 11:13:28 +0000 (07:13 -0400)]
SECURE_BOOT: Unify memory map for Layerscape based platforms
Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Fri, 11 Aug 2017 05:39:14 +0000 (11:09 +0530)]
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
ipu_common: Let the MX6 IPU clock be calculated in run-time
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz.
When running a SPL target, which supports multiple MX6 variants we cannot
properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as
such decision is done in build-time currently.
Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be
configured in run-time on mx6.
Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
[agust: fixed #endif in cgtqmx6eval.h] Signed-off-by: Anatolij Gustschin <agust@denx.de>
Bin Meng [Sun, 10 Sep 2017 12:12:53 +0000 (05:12 -0700)]
cmd: ide: Make the first device the default one
At present the IDE device number is initialized to -1, which means
we cannot type "ide read" command before setting the device number
via "ide device #".
For convenience, let's set the first device as the default one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 10 Sep 2017 12:12:51 +0000 (05:12 -0700)]
block: ide: Fix block read/write with driver model
This converts the IDE driver to driver model so that block read and
write are fully functional.
Fixes: b7c6baef ("x86: Convert MMC to driver model") Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 8 Sep 2017 17:12:16 +0000 (13:12 -0400)]
env: Migrate CONFIG_ENV_AES to Kconfig and deprecate
The underlying implementation for ENV_AES has security complications and
is not recommended for use. Please see CVE-2017-3225 and CVE-2017-3226
for more details. Mark this as deprecated now and delete this in the
medium term if no one comes forward to re-work the support.
Chris Packham [Mon, 28 Aug 2017 08:50:45 +0000 (20:50 +1200)]
usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig
CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on
USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and
LAN78XX options under new menu. Finally update the defconfigs that need
CONFIG_USB_HOST_ETHER.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 8 Sep 2017 03:00:54 +0000 (11:00 +0800)]
rockchip: enable SPL_SYSRESET config for all Rockchip SoCs
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET
for do_reset() in SPL for Rockchip SoCs.
References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro" Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 6 Sep 2017 07:58:25 +0000 (15:58 +0800)]
rockchip: rk3328: fix syscon id table
syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Disable CONFIG_ARCH_FIXUP_FDT_MEMORY to prevent U-Boot from modifying
the memory {} nodes in the DT passed to the Linux kernel. The R8A779x
DT contains multiple memory {} nodes, while U-Boot only modifies the
first one and stuffs all the memory entries into it, which is wrong.
Disabling CONFIG_ARCH_FIXUP_FDT_MEMORY is the least intrusive way to
fix the issue this close to the release, while the real fix is to
extend the fdt_fixup_memory_banks() to handle multiple memory nodes
in DT.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 5 Sep 2017 13:11:14 +0000 (15:11 +0200)]
ARM: rmobile: Fix SD divider settings on Gen3
On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
projects / u-boot.git / log