Lukasz Majewski [Thu, 10 Dec 2015 15:32:25 +0000 (16:32 +0100)]
usb: host: ehci: samsung: Move hcor initialization after usb phy setup
With the old order of initialization the hcor pointer has been setup to
the same address as Exynos EHCI base address (0x12110000 instead of
0x12110010).
Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI
HCCPBASE register without doing proper clock initialization before.
To fix this problem hcor initialization has been moved after USB PHY setup.
Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value.
Marek Vasut [Wed, 19 Aug 2015 21:27:26 +0000 (23:27 +0200)]
usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*
The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:
git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
while read line ; do
sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
done
Marek Vasut [Fri, 4 Dec 2015 01:34:46 +0000 (02:34 +0100)]
usb: s3c-otg: Rename sources to dwc2_*c
The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.
Marek Vasut [Fri, 4 Dec 2015 01:32:22 +0000 (02:32 +0100)]
usb: s3c-otg: Rename local headers to dwc2_*h
The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.
Marek Vasut [Fri, 4 Dec 2015 01:03:45 +0000 (02:03 +0100)]
usb: s3c-otg: Rename s3c_udc_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.
Marek Vasut [Fri, 4 Dec 2015 00:44:41 +0000 (01:44 +0100)]
usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phy
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.
Marek Vasut [Fri, 4 Dec 2015 00:36:36 +0000 (01:36 +0100)]
usb: s3c-otg: Split private bits from s3c_udc.h
Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.
Marek Vasut [Fri, 4 Dec 2015 00:11:45 +0000 (01:11 +0100)]
usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.
Unify the code for doing read/write into single function, since the
code for both the read and write is almost identical. This again
trims down the code duplication.
----------------------->8--------------------
where the same one routine is utilized for both EEPROM writing and
reading. The only difference was supposed to be a "read" flag which
in both cases was set with 1 somehow.
That lead to a missing delay in case of writing which lead to write
failure (in my case no data was written).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de>
Tang Yuantian [Wed, 9 Dec 2015 07:32:18 +0000 (15:32 +0800)]
armv8: Add sata support on Layerscape ARMv8 board
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 8 Dec 2015 08:24:30 +0000 (13:54 +0530)]
drivers/crypto/fsl: fix endianness issue in RNG
For Setting and clearing the bits in SEC Block registers
sec_clrbits32() and sec_setbits32() are used which work as
per endianness of CAAM block.
So these must be used with SEC register address as argument.
If the value is read in a local variable, then the functions
will not behave correctly where endianness of CAAM and core is
different.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 8 Dec 2015 08:24:29 +0000 (13:54 +0530)]
armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 8 Dec 2015 08:24:28 +0000 (13:54 +0530)]
include/linux: move typdef for uintptr_t
uintptr_t which is a typdef for unsigned long is needed for creating
pointers (32 or 64 bit depending on Core) from 32 bit variables
storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *),
compiler gives a warning in case size of pointer on the core is 64 bit.
The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Stein [Wed, 4 Nov 2015 08:19:10 +0000 (09:19 +0100)]
fsl_qspi: Pet the watchdog while reading/writing
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 7 Dec 2015 19:08:58 +0000 (11:08 -0800)]
armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
York Sun [Mon, 7 Dec 2015 19:05:29 +0000 (11:05 -0800)]
common: Rewrite hiding the end of memory
As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
some memory from the end of ram, tracked by gd->ram_size. It is not
always the top of u-boot visible memory. Rewrite the macro with a
weak function to provide flexibility for complex calcuation. Legacy
use of this macro is still supported.
Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
York Sun [Fri, 4 Dec 2015 19:57:08 +0000 (11:57 -0800)]
armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
York Sun [Fri, 4 Dec 2015 19:57:07 +0000 (11:57 -0800)]
Reserve secure memory
Secure memory is at the end of memory, separated and reserved
from OS, tracked by gd->secure_ram. Secure memory can host
MMU tables, security monitor, etc. This is different from PRAM
used to reserve private memory. PRAM offers memory at the top
of u-boot memory, not necessarily the real end of memory for
systems with very large DDR. Using the end of memory simplifies
MMU setup and avoid memory fragmentation.
"bdinfo" command shows gd->secure_ram value if this memory is
marked as secured.
Tom Rini [Mon, 14 Dec 2015 16:08:38 +0000 (11:08 -0500)]
armv7: omap-common: Rework SPL board_mmc_init()
Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional. For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC). A further rework and consolidation of the
functions should be done at a later date.
Tested on Beaglebone Black (SD and eMMC boot).
Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Tom Rini <trini@konsulko.com>
Eric Nelson [Sat, 5 Dec 2015 19:32:28 +0000 (12:32 -0700)]
spl: mmc: use block device number, not hard-coded 0
In order to support boot from multiple devices through board_boot_order,
it's necessary to use the block number of a device.
The use of a hard-coded 0 for the device number also creates a need
to re-order block devices for use in SPL like this:
http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195
Tom Rini [Sat, 28 Nov 2015 13:04:42 +0000 (08:04 -0500)]
qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submit
With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and
becomes BUG_ON((!a) != b). In this case reading of the function leads to
us wanting to rewrite this as BUG_ON(a != b).
Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com> Cc: Haiying Wang <Haiying.Wang@freescale.com> Cc: Roy Pledge <Roy.Pledge@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
Tom Rini [Sat, 28 Nov 2015 13:04:41 +0000 (08:04 -0500)]
fsl_*_serdes.c: Modify memset call in serdes_init
GCC 5.x does not like sizeof(array_variable) and errors out. Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).
Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 23 Nov 2015 07:23:48 +0000 (15:23 +0800)]
armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Tue, 10 Nov 2015 11:20:16 +0000 (19:20 +0800)]
freescale: fman: make sure phy-handle property is big endian
When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Stephen Warren [Wed, 9 Dec 2015 16:48:04 +0000 (09:48 -0700)]
part: fix "part list ... -bootable varname" to use hex
Unfortunately U-Boot assumes that almost all numbers are in hex, including
partition numbers passed to e.g. "load". So, the command "part list mmc 0
-bootable devplist" should use hex when writing partition numbers into
$devplist, so they'll be correctly interpreted.
Change-Id: I9a70b19749643876baadb45efbc3decaef8bfee2 Fixes: 0798d6fd4191 ("part: Add support for list filtering on bootable partitions") Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Egli, Samuel [Wed, 2 Dec 2015 14:27:56 +0000 (15:27 +0100)]
am33xx,ddr3: fix ddr3 sdram configuration
This patch fixes the DDR3 initialization procedure in
order to comply with DDR3 standard. A 500 us delay is specified
between the DDR3 reset and clock enable signal. Until now,
this delay was not respected. Some DDR3 chips don't bother
but the bigger the RAM becomes the more likely it seems that
this delay is needed. We observed that DRAM > 256 MB from
the manufacturer Samsung have an issue when the specification
is not respected.
Changes:
1) Add a 1 ms wait for L3 timeout error trigger
2) Don't delay DDR3 initialization
Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his
suppresses the initialization of DDR3
Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Reviewed-by: James Doublesin <doublesin@ti.com> Cc: Tom Rini <trini@konsulko.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
Miao Yan [Wed, 2 Dec 2015 07:39:01 +0000 (23:39 -0800)]
VxWorks: fixup MAC address for VxWorks
VxWorks 7 kernels retrieve 'local-mac-addr' from dtb and use
that for NIC MAC address. As a result, when booting the same
kernel image on multiple boards, there will be address
conflicts.
So fixup MAC address when booting VxWorks 7 kernels
Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Jagan Teki [Sun, 6 Dec 2015 16:03:32 +0000 (21:33 +0530)]
sf: sf_probe: Remove spi_slave pointer argument
Since spi_slave is a spi pointer in spi_flash{} then assign
spi_slave{} pointer to flash->spi and remove spi_slave
pointer argument to
- spi_flash_probe_slave
- spi_flash_scan
Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Wed, 25 Nov 2015 19:33:33 +0000 (01:03 +0530)]
sf: Remove unneeded SST_BP and SST_WP
SST parts added on sf_params.c supports both SST_WR which consits
of both BP and WP and there is a spi controller ich which supports
only BP so the relevent _write hook set based on "slave->op_mode_tx"
hence there is no respective change required from flash side hance
removed these.
Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 29 Sep 2015 20:31:23 +0000 (02:01 +0530)]
sf: Flash power up read-only based on idcode0
Using macro's for flash power up read-only access code
leads wrong behaviour hence use idcode0 for runtime
detection, hence the flash which require this functionality
gets detected at runtime.
Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 29 Sep 2015 16:59:33 +0000 (22:29 +0530)]
sf: Use simple name for register access functions
Most of the register access function are static,
so used simple name to represent each.
Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 3 Nov 2015 18:57:35 +0000 (00:27 +0530)]
sf: probe: Code cleanup
- Move bar read code below the bar write hance both
at once place, hence it easy for #ifdef macro only
once and readable.
- Move read_cmd_array at top
Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 29 Sep 2015 12:36:04 +0000 (18:06 +0530)]
sf: Move read_id code to sf_ops
read_id code is related to spi_flash stuff
hence moved to sf_ops.
Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Fri, 11 Dec 2015 16:06:34 +0000 (21:36 +0530)]
sf: Move spi_flash_scan code to sf_ops
Intension is that sf_ops should deals all spi_flash
related stuff and sf_probe (which should renamed future)
should be an interface layer for spi_flash versus spi drivers.
sf_ops => spi_flash interface
sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers
Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 29 Sep 2015 11:58:20 +0000 (17:28 +0530)]
sf: spi_flash_validate_params => spi_flash_scan
Rename spi_flash_validate_params to spi_flash_scan
as this code not only deals with params setup but
also configure all spi_flash attributes.
And also moved all flash related code into
spi_flash_scan for future functionality addition.
Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Peng Fan [Mon, 30 Nov 2015 09:45:02 +0000 (17:45 +0800)]
imx: mx7dsabresd: Add QSPI support
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Stefan Roese [Thu, 26 Nov 2015 12:38:43 +0000 (13:38 +0100)]
dm: serial: Minor coding style cleanup of some comments
Fix incorrect comment alignments.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Thu, 26 Nov 2015 12:38:01 +0000 (13:38 +0100)]
dm: core: Fix Kconfig text to mention SPL in SPL_OF_TRANSLATE
Add a remark about SPL to this Kconfig option. Otherwise its identitcal
to the non-SPL version, which is confusing.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
Jens Kuske [Thu, 10 Dec 2015 10:41:02 +0000 (11:41 +0100)]
sunxi: Fix H3 DRAM DQ read delay configuration
The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.
Signed-off-by: Jens Kuske <jenskuske@gmail.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
projects / u-boot.git / log