Marek Vasut [Mon, 1 Mar 2021 15:41:28 +0000 (16:41 +0100)]
ARM: imx: Include u-boot.img in u-boot-with-spl.imx if OF_SEPARATE=y
The u-boot-with-spl.imx is a concatenation of SPL and u-boot.uim.
The u-boot.uim is u-boot.bin wrapped in uImage. In case OF_SEPARATE
is enabled, the u-boot.bin does not contain control DT for U-Boot,
and so u-boot.uim does not contain the DT, and so u-boot-with-spl.imx
does not contain the DT, and a system where u-boot-with-spl.imx is
written to offset 1024B to the start of storage no longer boots, as
it is missing DT.
In case OF_SEPARATE is enabled, u-boot.img contains both u-boot.bin
and the necessary DTs. Therefore, use u-boot.img instead of u-boot.uim
to generate u-boot-with-spl.imx when OF_SEPARATE is enabled.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Christoph Niedermaier <cniedermaier@dh-electronics.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
Marek Vasut [Sat, 27 Feb 2021 13:59:00 +0000 (14:59 +0100)]
ARM: imx: Do not hard-code MX8M MMU table DRAM entry offset
Instead of hard-coding the offset of DRAM entries in MMU table all over
the code, auto-detect the offset. This removes error-prone code which
would break e.g. in case the MMU table is modified.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Commit 247bbeb74c18 ("ARM: dts: imx8m: increase off-on delay on the SD Vcc
regulator") caused the imx8mq-evk board to not be able to store the
environment variables in the SD card.
Remove the u-boot,off-on-delay-us property to fix the regression.
Adam Ford [Tue, 16 Feb 2021 14:19:52 +0000 (08:19 -0600)]
imx: Add 2GB lpddr support for i.MX8MN Beacon EmbeddedWorks devkit.
There is a second lpddr configuration with 2GB of RAM, but this requires
different RAM timings, so in addition to adding the timing file, a
separate defconfig is necessary.
Add 'O=' to make and build in separate directory as one issue has been noticed
where it was trouble building directly inside u-boot source dir. Restructure the workflow
and copy binaries after defconfig to ensure that build directory is created.
Ye Li [Sun, 21 Feb 2021 02:25:45 +0000 (18:25 -0800)]
mx6sabre: Fix boot failure
CONFIG_SPL_LEGACY_IMAGE_SUPPORT is necessary for mx6sabresd and
mx6sabreauto, because u-boot is packed as legacy image not FIT.
However, this config is not set when CONFIG_SPL_LOAD_FIT is enabled.
Must enable it explicitly, otherwise will fail to boot like below.
U-Boot SPL 2021.04-rc2 (Feb 20 2021 - 16:43:04 -0800)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
Haibo Chen [Fri, 19 Feb 2021 19:25:32 +0000 (11:25 -0800)]
mmc: fsl_esdhc_imx: fix the DTOCV to 0xE
On imx6Q/imx6DL, we find if config the DTOCV to 0~3, it will impact
cmd6 behavior, after cmd6 get transfer complete interrupt, the data0
line will keep low over 5 seconds. This should be a IC bug on imx6Q/DL.
For other platforms, do not has this issue.
To fix this issue, fix the DTOCV to 0xE, the max setting, this also align
with Linux configuration.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The RGMII link delays can be set on either MAC or PHY side. Set the
rgmii-id PHY mode for FEC and remove FEC_ENET_ENABLE_.XC_DELAY
setting, so that these definitions aren't used anymore throughout
the U-Boot.
ARM: imx8: Add missing FEC ENET quirk for i.MX8/i.MX8X
Both NXP SoCs i.MX8 and i.MX8X have ENET gigabit MAC.
Define FEC_QUIRK_ENET_MAC for the imx8 platform and remove this
definition from configs of boards, based on MX8/MX8X.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Acked-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Respect that some compression algos can be enabled separately for SPL
Some compression algorithms currently can be enabled for SPL and
U-Boot proper separately. Therefore take into account USE_HOSTCC
is well as CONFIG_IS_ENABLED() in these cases to prevent compiling these
functions in case of a host tool build.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Sat, 6 Feb 2021 00:11:05 +0000 (16:11 -0800)]
thermal: imx_tmu: enable monitoring and default alert/critical
Set default critical/alert temperature and enabling monoitoring.
Without calling imx_tmu_enable_msite() monitoring will not be enabled
and read_temperature will return 0. Additionally without setting alert
temperature will cause imx_tmu_get_temp() to spin indefiniately thinking
the system needs to cool.
This resolves the board spinning endlessly when enabling IMX_TMU in the
SPL.
Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Sean Anderson [Thu, 4 Feb 2021 21:44:22 +0000 (16:44 -0500)]
ARM: mx6: Add function to set serial#
The serial number OTP is similar to the imx7 version, except that the
register names are different. This also sets serial# directly, instead of
providing board_get_serial.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 4 Feb 2021 18:00:32 +0000 (19:00 +0100)]
ARM: imx6: mx6sabre-common: Search for boot components in /boot too
Some root filesystem configurations do not have separate /boot partition,
but rather place kernel, DT, scripts into /boot directory. Search the /boot
directory for these boot components in case they are not found in /, which
is the old behavior.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Thu, 4 Feb 2021 00:17:02 +0000 (01:17 +0100)]
ARM: imx6: dh-imx6: Drop the SF hunk in config
There is now CONFIG_SPL_DM_SPI{,_FLASH}, however keeping
CONFIG_DM_SPI{,_FLASH} enabled in SPL seems to grow the SPL
by a couple of bytes:
text data bss dec hex filename
- 34069 1568 96 35733 8b95 spl/u-boot-spl
+ 34075 1568 96 35739 8b9b spl/u-boot-spl
In either case, the binary is bootable, so remove the part
in board config.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Ludwig Zenz <lzenz@dh-electronics.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Wed, 3 Feb 2021 21:36:33 +0000 (22:36 +0100)]
ARM: imx: Revert "dh_imx6: Switch to full DM-aware"
This reverts commit 03a673cf49e ("dh_imx6: Switch to full DM-aware").
According to discussion [1], the patch is known to break the dh_imx6
board, however it made it upstream just before 2021.01-rc4, likely by
mistake. Revert this patch to put the board back into working order.
Also note that this board has no DM SPL support due to OCRAM size
limitations, but that is fine, as SPL DM support is optional.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Ludwig Zenz <lzenz@dh-electronics.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 26 Feb 2021 17:41:06 +0000 (12:41 -0500)]
Merge tag 'u-boot-stm32-20210226' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Add USB host boot support in stm32mp1 config
- Enable uefi related commands for STMicroelectronics STM32MP15 boards
- Remove duplicate uart nodes in stm32mp15 device tree
Ilias Apalodimas [Fri, 26 Feb 2021 12:52:51 +0000 (14:52 +0200)]
configs: stm32mp1: enable uefi related commands
The board can boot with UEFI. With the latest changes in U-Boot's
EFI subsystem we also have support for EFI runtime variables, without
SetVariable support. We can also store the EFI variables in a file on the
ESP partition and preserve them across reboots.
The env and efidebug commands are missing in order to configure
EFI variables and the efibootmgr though. Since U-Boot's default config
enables other EFI related commands (e.g bootefi), let's add the env related
and efidebug commands and allow users to do that
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Wed, 24 Feb 2021 10:00:56 +0000 (11:00 +0100)]
arm: dts: stm32mp15: remove duplicate uart nodes
Remove duplicated uart nodes introduced with commit 62f95af92a3f
("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4"),
because the uart nodes wasn't correctly ordered in alphabetic order.
Only cosmetic: the generated device tree don't change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Stefan Brüns [Sat, 20 Feb 2021 16:26:06 +0000 (17:26 +0100)]
usb: kbd: Also accept keyboards with Interrupt OUT endpoint
The OUT endpoint can just be ignored as it is not used, just as the
corresponding Set_Report request for IN-only interfaces. E.g. the
Linux gadget hid keyboard also provides an interrupt endpoint.
Also cleanup confusing debug messages like "found set protocol", which
is printed when a keyboard device is found, while the Set_Protocol request
is issued quite some time later.
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Sean Anderson [Fri, 5 Feb 2021 14:39:02 +0000 (09:39 -0500)]
doc: Document partition specifications
This documents the way U-Boot understands partitions specifications.
This also updates the fastboot documentation for the changes in the
previous commit.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Fri, 5 Feb 2021 14:39:01 +0000 (09:39 -0500)]
doc: Rename k210 partitions anchor
This anchor is only for the k210 partition layout, so rename it
appropriately. This keeps it from conflicting with the (to be added)
anchor for U-Boot partitions in general.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Fri, 5 Feb 2021 14:39:00 +0000 (09:39 -0500)]
fastboot: Allow u-boot-style partitions
This adds support for partitions of the form "dev.hwpart:part" and
"dev#partname". This allows one to flash to eMMC boot partitions without
having to use CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT. It also allows one to
flash to an entire device without needing CONFIG_FASTBOOT_MMC_USER_NAME.
Lastly, one can also flash MMC devices other than
CONFIG_FASTBOOT_FLASH_MMC_DEV.
Because devices can be specified explicitly, CONFIG_FASTBOOT_FLASH_MMC_DEV
is used only when necessary for existing functionality. For those cases,
fastboot_mmc_get_dev has been added as a helper function. This allows
There should be no conflicts with the existing system, but just in case, I
have ordered detection of these names after all existing names.
The fastboot_mmc_part test has been updated for these new names.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Fri, 5 Feb 2021 14:38:58 +0000 (09:38 -0500)]
fastboot: Remove mmcpart argument from raw_part_get_info_by_name
The only thing mmcpart was used for was to pass to blk_dselect_hwpart.
This calls blk_dselect_hwpart directly from raw_part_get_info_by_name. The
error handling is dropped, but it is reintroduced in the next commit
(albeit less specificly).
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Fri, 5 Feb 2021 14:38:55 +0000 (09:38 -0500)]
part: Give several functions more useful return values
Several functions in disk/part.c just return -1 on error. This makes them
return different errnos for different failures. This helps callers
differentiate between failures, even if they cannot read stdout.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Fri, 5 Feb 2021 14:38:54 +0000 (09:38 -0500)]
test: dm: Add test for fastboot mmc partition naming
This test verifies the mapping between fastboot partitions and partitions
as understood by U-Boot. It also tests the creation of GPT partitions,
though that is not the primary goal.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Fri, 5 Feb 2021 14:38:53 +0000 (09:38 -0500)]
mmc: sandbox: Add support for writing
This adds support writing to the sandbox mmc backed by an in-memory
buffer. The unit test has been updated to test reading, writing, and
erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF
then that can be easily changed.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
- turris_mox: Enhancements, mostlly defconfig changes (Pali)
- pci-aardvark: Set Max Payload Size and Max Read Request Size
to 512 bytes (Pali)
- pci_mvebu: Minor cleanup and refactoring (Marek)
- Upgrade A38x DDR3 training to version 14.0.0 (Marek)
Reto Schneider [Thu, 11 Feb 2021 12:05:48 +0000 (13:05 +0100)]
mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.
As the overlaps are huge, variable names have been generalized
accordingly.
Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.
New hardware features are not supported, namely:
- Power on reset
- Unique ID
- Double transfer rate (DTR)
- Parameter page
- Random data quad IO
The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.
The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.
Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Hauke Mehrtens [Thu, 11 Feb 2021 12:05:47 +0000 (13:05 +0100)]
mtd: nand: spi: Only one dummy byte in QUADIO
The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG
Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 5 Feb 2021 04:11:08 +0000 (23:11 -0500)]
mtd: spi-nor-core: Fix typo in documentation
This line should come before the docs for the next function.
Fixes: 7aeedac0153 ("mtd: spi: Port SPI NOR framework from Linux") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 5 Feb 2021 04:11:07 +0000 (23:11 -0500)]
cmd: sf: Print error on test failure
The sf test command is used to test spi flashes (and spi masters). Printing
the exact error code is very helpful to those debugging the spi stack.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Sean Anderson [Fri, 5 Feb 2021 04:11:06 +0000 (23:11 -0500)]
cmd: sf: Display errno on erase failure
If there is an error while erasing SPI flash, no errno is displayed. This
makes it difficult to determine the cause of the error. This change mirrors
the logic for write errors above.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Adam Ford [Mon, 18 Jan 2021 21:32:49 +0000 (15:32 -0600)]
spi: nxp_fspi: Fix error reporting
On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set. When checking for errors, it only
checks that it is not NULL. Since positive numbers are not errors,
only check for negative numbers when handling errors.
Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Marek Behún [Fri, 19 Feb 2021 16:11:26 +0000 (17:11 +0100)]
ddr: marvell: a38x: fix comment in conditional macro
The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Marek Behún [Fri, 19 Feb 2021 16:11:25 +0000 (17:11 +0100)]
ddr: marvell: a38x: bump version to 14.0.0
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.
Signed-off-by: heaterC <airyguy@gmx.de> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.
Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
the twin-die combined memory device should be treatened as X8
device and not as X16 one
Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
all boards, as this was default behaviour prior this change ] Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.
- function mv_ddr_spd_die_capacity_user_get() has a bug,
since it insert a user memory enum to it,
instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
at mv_ddr_mem_sz_per_cs_get() function
Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com> Reviewed-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
then the algorithm will fail, since it think that there are no phase to correct
Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Marek Behún [Mon, 8 Feb 2021 22:01:41 +0000 (23:01 +0100)]
pci: pci_mvebu: set local dev to number 1
Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.
Let's do it also in U-Boot.
With this commit the pci command in U-Boot prints something like:
=> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x168c 0x003c Network controller 0x80
Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Mon, 8 Feb 2021 22:01:40 +0000 (23:01 +0100)]
pci: pci_mvebu: refactor validation of addresses for config access
Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.
We can simplify the code by putting the validation into separate
function.
Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
(by default this register is set to 0) there is a
"Marvell Memory controller", which isn't useful in root complex
mode,
* on all other slots the real PCIe card connected to the PCIe slot.
We can simplify the code even more by simply allowing access only to
the real PCIe card.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Mon, 8 Feb 2021 22:01:39 +0000 (23:01 +0100)]
pci: pci_mvebu: debug rd/wr config as other drivers do
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when
debugging is enabled. Print size for pci_mvebu as well.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Mon, 8 Feb 2021 22:01:38 +0000 (23:01 +0100)]
pci: pci_mvebu: cosmetic fix
Write bdf address in a same way in mvebu_pcie_read/write_config.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Mon, 8 Feb 2021 22:01:37 +0000 (23:01 +0100)]
pci: pci_mvebu: use dev_seq instead of static variable
PCI uclass maps PCI bus numbers to the seq member of struct udevice.
Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an
incrementing a static variable.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 5 Feb 2021 14:32:28 +0000 (15:32 +0100)]
arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to
Armada 3720 SOC. Without this U-Boot crashes when trying to access
enumerated USB devices connected to this XHCI PCIe controller.
This should be done according to the PCIe Link Initialization sequence, as
defined in Marvell Armada 3720 Functional Specification.
Linux has this code too.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
According to the datasheets, all of these 3 types support BP(0,1,2) and
TB bits in the status register (SR), so it could reuse the flash
protection logic for ST Micro.
So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
flags to the w25q128 entry of spi_nor_ids table.
Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[jagan: remove comments in spi-nor-ids.c] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Sun, 21 Feb 2021 01:06:28 +0000 (20:06 -0500)]
ppc: configs: Remove a few non-updated build configurations
In the cases of T2080RDB_SECURE_BOOT, T2080RDB_SRIO_PCIE_BOOT,
P2041RDB_SECURE_BOOT, P2041RDB_SRIO_PCIE_BOOT, P3041DS_SRIO_PCIE_BOOT
and P4080DS_SRIO_PCIE_BOOT while some forms of the board have been
migrated more fully to current build standards, these have not. Remove
them.
projects / u-boot.git / log