smbios: if a string value is unknown, use string number 0
The SMBIOS specification describes: "If a string field references no string,
a null (0) is placed in that string field."
Accordingly we should avoid writing a string "Unknown" to the SMBIOS table.
dmidecode displays 'Not Specified' if the string number is 0.
Commit 00a871d34e2f ("smbios: empty strings in smbios_add_string()")
correctly identified that strings may not have length 0 as two
consecutive NULs indentify the end of the string list. But the suggested
solution did not match the intent of the SMBIOS specification.
Fixes: 00a871d34e2f ("smbios: empty strings in smbios_add_string()") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
When no string is present in a table, next_ptr points to the same
location as eos. When calculating the string table length, we would only
reserve one \0. By spec a SMBIOS table has to end with two \0\0 when no
strings a present.
Signed-off-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Add description for parameter sysinfo_id of function get_str_from_dt().
Fixes: 07c9e683a484 ("smbios: Allow a few values to come from sysinfo") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* Add RISC-V falcon mode documentation
* Add Clang build support
* Add cmd to detect Debug Trigger Extension support
* Add PWM setting for Unmatched board
* Add Milk-V Duo board support
* Add new device node and enable new config option for VisionFive2 board
* Add second virtio device for RISC-V QEMU
Kongyang Liu [Sun, 28 Jan 2024 07:05:24 +0000 (15:05 +0800)]
riscv: dts: sophgo: add basic device tree for Milk-V Duo board
Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Aurelien Jarno [Sat, 27 Jan 2024 13:48:45 +0000 (14:48 +0100)]
configs: visionfive2: Disable ENV_IS_NOWHERE
The VisionFive 2 board supports saving the u-boot environment settings
are saved to on-board SPI flash. However the defconfig enables both
ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH, preventing the "saveenv" command
to work. Fix that by disabling ENV_IS_NOWHERE.
Fixes: 7d79bed00c9e ("configs: starfive: Enable environment in SPI flash support") Reported-by: E Shattow <lucent@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Vincent Chen [Tue, 16 Jan 2024 06:35:57 +0000 (14:35 +0800)]
board: sifive: spl: Initialized the PWM setting in the SPL stage
LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nylon Chen <nylon.chen@sifive.com> Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Co-developed-by: Zong Li <zong.li@sifve.com> Signed-off-by: Zong Li <zong.li@sifve.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Aurelien Jarno [Wed, 10 Jan 2024 20:26:53 +0000 (21:26 +0100)]
riscv: qemu: enable booting on a second virtio device
QEMU RISC-V supports multiple virtio devices, but only tries to boot to
the first one. Enable support for a second virtio device, that is useful
for instance to boot on a disk image + an installer. Ideally that should
be made dynamic, but that's a first step.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Aurelien Jarno [Wed, 10 Jan 2024 20:17:44 +0000 (21:17 +0100)]
board: starfive: handle compatible property in dynamic DT configuration
The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
handled dynamically by looking at the PCB version in the EEPROM in order
to have a single u-boot version for both versions of the board. While
the "model" property is correctly handled, the "compatible" one is
always the the one of version 1.3b.
This patch add support for dynamically configuring that property.
Fixes: 9b7060bd15e7 ("riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Randolph [Fri, 29 Dec 2023 08:32:22 +0000 (16:32 +0800)]
spl: riscv: falcon: move fdt blob to specified address
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tom Rini [Tue, 30 Jan 2024 12:54:28 +0000 (07:54 -0500)]
Merge tag 'clk-2024.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk
Clock changes for v2024.04
This pull has the usual fixes and new (clock-adjacent) drivers. It also has some
cleanups for the clock API; in particular removing the unused rfree callback.
Svyatoslav Ryhel [Wed, 10 Jan 2024 16:09:56 +0000 (18:09 +0200)]
clk: clk-gpio: add actual gated clock
Existing gpio-gate-clock driver acts like a simple GPIO switch without any
effect on gated clock. Add actual clock actions into enable/disable ops and
implement get_rate op by passing gated clock if it is enabled.
Sean Anderson [Sat, 16 Dec 2023 19:38:43 +0000 (14:38 -0500)]
clk: Document clk_ops return codes and behavior
Currently, clock consumers cannot take any programmatic action based on the
return code of a clock function. This is because there is no
standardization, and generally no way of separating e.g. "there was a major
problem setting the rate for this clock" which usually should not be
recovered from, from "this clock doesn't support setting its rate" or "this
clock doesn't support *this* rate" which could be absolutely fine depending
on the driver.
This commit aims to standardize the acceptable codes which may be returned
from clock operations. In general,
- ENOSYS should be returned when an operation is not supported for a
particular clock.
- ENOENT may be returned if the clock ID is invalid. However, it is
encouraged to move any checks to request() to reduce code duplication.
- EINVAL should be returned for logical errors only (such as requesting an
invalid rate).
Each function has had specific guidance added for when to return each error
code. This is just guidance for now; most of the clock subsystem does not
yet conform to this standard. However, it is expected that new clock
drivers return these error codes.
Additionally, this commit adds expected behavior for each of the clock
operations. I believe these should be mostly straightforward and correspond
to existing behavior. I remember not understanding what the expected
invariants were for several clock functions, so hopefully this should help
out new driver authors. In the future, some of these invariants could be
checked via an optional config option.
Julien Masson [Fri, 15 Dec 2023 14:09:43 +0000 (15:09 +0100)]
clk: fix clk_get_rate() always return ulong
When we call clk_get_rate(), we expect to get clock rate value as
ulong.
In that case we should not use log_ret() macro since it use internally
an int.
Otherwise we may return an invalid/truncated clock rate value.
Signed-off-by: Julien Masson <jmasson@baylibre.com> Fixes: 5c5992cb90c ("clk: Add debugging for return values") Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/87o7erv9p4.fsf@baylibre.com
Tom Rini [Mon, 29 Jan 2024 21:19:10 +0000 (16:19 -0500)]
Merge tag 'efi-2024-04-rc1-4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc1-4
Documentation:
* uefi: remove ".py" suffix for pytest.py command
* correct date in migration plan for CONFIG_DM
UEFI:
* fix conflicting SPDX license in RISC-V EFI linker scripts
* page align EFI binary section in RISC-V EFI binaries
* separate .data and .text sections of RISC-V EFI binaries
* use common function to get EFI configuration table
Quentin Schulz [Tue, 23 Jan 2024 17:57:01 +0000 (18:57 +0100)]
tools: buildman: fix non-existing SafeConfigParser in Python 3.12+
SafeConfigParser was renamed back in Python 3.2 (yes, no typo) to
ConfigParser[1], but it was still working as an alias until it got
removed in 3.12[2].
Janne Grunau [Wed, 17 Jan 2024 22:27:34 +0000 (23:27 +0100)]
video: Support VIDEO_X2R10G10B10 in truetype console
Without explicit support for VIDEO_X2R10G10B10 VIDEO_X8R8G8B8 white
will be rendered as cyan-ish. The conversion leaves to lowest 2 bits
unset for more compact code.
Devarsh Thakkar [Wed, 24 Jan 2024 09:07:11 +0000 (14:37 +0530)]
video: tidss: Use DT property names for parsing nodes
Use device-tree node property names for parsing nodes instead of
indexing as indexing could be different between different SoCs based on
number of DSS entities available on that particular SoC.
Also correct the video layer naming in driver to match to actual one
being used in upstream DSS device-tree node [1].
This also fixes AM62x splash screen usage using the latest upstream DSS
device-tree nodes where hard-coded indexing which driver was using
before this patch was not matching the correct properties in the DT
node.
Fixes: 5f9f816bb8 ("drivers: video: tidss: TIDSS video driver support for AM62x") Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Tom Rini [Mon, 29 Jan 2024 19:49:25 +0000 (14:49 -0500)]
Merge patch series "Move framebuffer reservation for SPL to RAM end"
Devarsh Thakkar <devarsht@ti.com> says:
Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.
Also catch the bloblist before starting reservations to avoid the same
problem.
While at it, also fill missing fields in video handoff struct before
passing it to next stage.
This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:21 +0000 (21:25 +0530)]
video: Fill video handoff in video post probe
Fill video handoff fields in video_post_probe as at this point we have
full framebuffer-related information.
Also fill all the fields available in video hand-off struct as those
were missing earlier and U-boot framework expects them to be filled for
some of the functionalities.
While filling framebuffer size in video hand-off structure use the
actual framebuffer region size as derived from gd->video_top and
gd->video_bottom instead of directly using the size populated in
video_uc_plat as it contains unaligned size.
Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:20 +0000 (21:25 +0530)]
video: Skip framebuffer reservation if already reserved
Skip framebufer reservation if it was already reserved from previous
stage and whose information was passed using a bloblist.
Return error in case framebuffer information received from bloblist is
invalid i.e NULL or empty.
While at it, improve the debug message to make it more clear that
address in discussion is of framebuffer and not bloblist and also match
it with printing scheme followed in video_reserve function.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:19 +0000 (21:25 +0530)]
common/board_f: Catch bloblist before starting reservations
Start reservations needed for init sequence only after catching
bloblists from previous stage.
This is to avoid catching bloblists in the middle causing gaps while
u-boot is reserving.
Adjust the relocaddr as per video hand-off information received from
previous stage so that further reservations start only after regions
reserved for previous stages
Skip reservation for video memory if it was already filled by a
bloblist.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:18 +0000 (21:25 +0530)]
board: ti: am62x: evm: Remove video_setup from spl_board_init
Remove video_setup from evm_init sequence since video memory is getting
called at an earlier place to make sure video memory is reserved at
the end of RAM.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:17 +0000 (21:25 +0530)]
arm: mach-k3: common: Reserve video memory from end of the RAM
Setup video memory before page table reservation using
"spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
reserved from the end of RAM.
This is done to enable the next stage to directly skip the
pre-reserved area from previous stage right from the end of RAM without
having to make any gaps/holes to accommodate those regions which was the
case before as previous stage reserved region not from the end of RAM.
Use gd->ram_top instead of local ram_top and update gd->reloc_addr after
each reservation to ensure further regions are reserved properly.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:16 +0000 (21:25 +0530)]
spl: Enforce framebuffer reservation from end of RAM
Add an API which enforces framebuffer reservation from end of RAM.
This is done so that next stage can directly skip this region before
carrying out further reservations.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 29 Jan 2024 15:57:42 +0000 (10:57 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Some cleanups in header files: those do not affect the generated
binaries at all.
- The usual update of DT files from the kernel repo, mostly adding new
board files this time. On the wake of this there is one defconfig to
enable a new board, some H618 TV box branded as "Transpeed".
- Samuel's series to support SPL FIT image loading for 32-bit SoCs as
well, so far this was restricted to ARM64 boards. I refrained from
automatically enabling this everywhere, instead this requires user
intervention during board configuration. This allows to ship the
"crust" management processor firmware on H3 boards, which enables
better power saving.
- One defconfig for an older H3 board. There was a close-by defconfig
for a related board, but there are some differences which deserve a
separate file.
- Support for the EMAC driver to work with fixed-link PHYs, which allows
to directly wire the MAC to a switch IC.
Love Kumar [Fri, 19 Jan 2024 14:37:13 +0000 (20:07 +0530)]
test/py: scsi: Add test for scsi commands
Add a following test cases for scsi commands:
scsi_reset - To reset SCSI controller
scsi_info - To show available SCSI devices
scsi_scan - To (re-)scan SCSI bus
scsi_device - To show or set surrent device
scsi_part - To print partition table of selected SCSI device
Love Kumar [Fri, 19 Jan 2024 14:26:02 +0000 (19:56 +0530)]
test/py: usb: Add tests for USB device
Add the test cases for usb commands to test its various functionality
such as start, stop, reset, info, tree, storage, dev, part, ls, load,
and save. It also adds different file systems cases such as fat32, ext2
and ext4.
Love Kumar [Fri, 19 Jan 2024 14:25:50 +0000 (19:55 +0530)]
test/py: mmc: Add tests for MMC device
Add the test cases for mmc commands to test its various functionality
such as mmc list, dev, info, rescan, part, ls, load, and save. It also
adds different file systems cases such as fat32, ext2 and ext4.
Love Kumar [Fri, 19 Jan 2024 10:01:29 +0000 (15:31 +0530)]
test/py: secure: Add secure tests for Zynq & ZynqMP
Add test cases to verify the different type of secure boot images loaded
at DDR location for AMD's ZynqMP SoC. It also adds tests authentication
and decryption functionality using AES and RSA features for Zynq.
Love Kumar [Fri, 19 Jan 2024 05:38:34 +0000 (11:08 +0530)]
test/py: gpio: Add gpio pins generic test
Add gpio pins generic test for the set of gpio pin list to test various
gpio related functionality, such as the input, set, clear, and toggle,
it also tests the input and output functionality for shorted gpio pins.
This test depends on boardenv* configuration to define gpio pins names.
Caleb Connolly [Tue, 2 Jan 2024 11:55:30 +0000 (11:55 +0000)]
pytest: update requirements.txt
Update pygit2 and py to their latest versions. Even in the venv pygit2
still links against the system libgit2 library which is failing on
latest Arch Linux.
The py library also needs updating to fix a KeyNotFound exception during
test initialisation.
Samuel Holland [Tue, 31 Oct 2023 05:17:41 +0000 (00:17 -0500)]
sunxi: Consider SPL size limitations for FIT loading
Now that 32-bit SoCs can load U-Boot proper (and possibly other firmware)
from a FIT, people can use that by enabling CONFIG_SPL_LOAD_FIT.
However SPL_FIT_IMAGE_TINY is required to stay within the 24 or 32 KiB
SPL size limit on early SoCs; for consistency, enable it everywhere.
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: drop unconditional FIT image enablement for all SoCs] Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Tue, 31 Oct 2023 05:17:40 +0000 (00:17 -0500)]
sunxi: binman: Support FIT generation for 32-bit SoCs
Some 32-bit SoCs can use SCP firmware to implement additional PSCI
functionality, such as system suspend. In order to load this firmware
from SPL, we need to generate and use a FIT instead of a legacy image.
Adjust the binman FIT definition so it does not rely on TF-A BL31, as
this is not used on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly. This requires to provide an
entry point property for the U-Boot image node, which confuses some
loaders like sunxi-fel, so protect that to only be used if we have no
BL31.
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: filter U-Boot entry point property] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Samuel Holland [Tue, 31 Oct 2023 05:17:39 +0000 (00:17 -0500)]
sunxi: binman: Move BL31 and SCP firmware addresses to Kconfig
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Tue, 31 Oct 2023 05:17:38 +0000 (00:17 -0500)]
sunxi: spl: Disable padding from SPL_PAD_TO
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Chuanhong Guo [Thu, 28 Dec 2023 05:29:15 +0000 (13:29 +0800)]
sunxi: add defconfig for nanopi_duo2
FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and
Ampak AP6212 WiFi module. The device-tree for it is already
available in u-boot source tree. Add a default config for it.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[Andre: enable USB gadgets] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Maksim Kiselev [Sat, 20 Jan 2024 16:26:24 +0000 (19:26 +0300)]
net: sun8i-emac: Add support for fixed-link phy
Make the "phy-handle" property optional, which allows support
for a fixed-link phy configuration.
Thus if the "phy-handle" is present in a DT, then driver will work as
before. Otherwise, phyaddr initialization will not be necessary,
as it is not needed in case of a fixed-link config.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 21 Jan 2024 00:06:00 +0000 (00:06 +0000)]
sunxi: dts: update devicetree files from Linux-v6.8-rc1
Sync the devicetree files from the official Linux kernel tree, v6.8-rc1.
This time only small changes in the existing files, but five new boards
got added, which opens the door for their respective defconfig files.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:06 +0000 (14:46 +0900)]
mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID
Infineon(Cypress) S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with
Octal interface. It is a dual-die package parts and has same features
with existing S28 series.
Enabling Octal DTR mode in multi-die package parts requires reister setup
for each die. That can be done by simple for-loop. write_enable() takes
effect to all die at once so we can call it before the loop. Besides we
can replace spi_mem_exec_op() calls with spansion_read/write_any_reg().
And finally, we must mask CFR2V[7:4] when changing dummy cycles, as
CFR2V[7] indicates current addressing mode and that should be 1 (4-byte
address mode) for multi-die package parts.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:04 +0000 (14:46 +0900)]
mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 and S28
s28hx_t_post_bfpt_fixup() fixes erase opcode, erase size, and page size.
s25_post_bfpt_fixup() is doing same thing including multi-die support.
We can consolidate s28hx_t_post_bfpt_fixup() and s25_post_bfpt_fixup()
into one named s25_s28_post_bfpt_fixup().
In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to
be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing
but it works actually (confirmed).
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:03 +0000 (14:46 +0900)]
mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28
s28hx_t_setup() only checks sector layout setting. To support multi-die
package parts like S28HS02GT, it needs to check device size and assign
ready() hook for multi-die package parts. These are covered in s25_setup()
so we can consolidate s28hx_t_setup() and s25_setup() into one named
s25_s28_setup().
spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be
removed since there is no op that makes device busy state before setup.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:02 +0000 (14:46 +0900)]
mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR mode
s25_mdp_ready() handles status polling for multi-die package parts that
requires to read and check status register for each die. To support
S28HS02GT(dual-die package with Octal DTR support), rename function and
use nor->rdsr_dummy in octal DTR mode.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:01 +0000 (14:46 +0900)]
mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28
Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode.
Instead, it supports CLPEF(0x82) which has the same functionality as CLSR.
spansion_sr_ready() is for multi-die package parts including S28HS02GT, so
we need to use CLPEF instead of CLSR.
This change does not affect to S25x02GT which uses spansion_sr_ready() as
S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30).
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:00 +0000 (14:46 +0900)]
mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode
In Infineon multi-die package parts, we need to use Read Any Register op
to read status register in 2nd or further die. Infineon S28HS02GT is
dual-die package and supports Octal DTR interface. To support this,
spansion_read_any_reg() needs to be reworked. Implementation is similar
to existing read_sr() that already supports Octal DTR mode.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:45:59 +0000 (14:45 +0900)]
mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28
s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector
layout (32 x 4KB sectors overlaid at bottom address) and doing same thing.
Consolidate them into single helper named s25_s28_erase_non_uniform().
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:45:58 +0000 (14:45 +0900)]
mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28
Some macro definitions used in Infineon(Cypress) S25 and S28 series are
redundant and some have inconsistent prefix. This patch removes
redundant ones and renames some to have same prefix as others.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Kankan Sun <ssunkkan@gmail.com>
[jagan: update the commit message] Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tejas Bhumkar [Sun, 28 Jan 2024 06:37:46 +0000 (12:07 +0530)]
spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data
The current implementation encounters issues when testing data ranging
from 0 to 8 bytes. This was confirmed through testing with both ISSI
(IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.
Upon investigation, it was observed that utilizing the
"SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in
STIG mode results in a read failure, leading to a compare test failure.
To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized
instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode.
This is based on patch series:
https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tejas Bhumkar [Wed, 27 Dec 2023 16:28:39 +0000 (21:58 +0530)]
mtd: spi-nor-ids: Add is25lx512 chip
Added support for the ISSI OSPI flash part IS25LX512M.
Initial testing was performed on the Tenzing-se1 board using
SDR mode, covering basic erase, write, and readback operations.
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Maksim Kiselev [Thu, 21 Dec 2023 10:13:30 +0000 (13:13 +0300)]
spi: dw: add check for Rx FIFO overflow
If even one byte is lost due to Rx FIFO overflow then we will never
exit the read loop. Because the (priv->rx != priv->rx_end) condition will
be always true.
Let's check if Rx FIFO overflow occurred and exit the read loop
in this case.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Fix conflicting SPDX license information in linker scripts introduced by
commit 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel
style").
Fixes: 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Alexander Dahl [Wed, 24 Jan 2024 07:48:58 +0000 (08:48 +0100)]
doc: dm: Fix typo
That's most probably a typo, because driver model design documents seem
to be from 2012 and there is no 2010.01 release.
Fixes: 282ed24fb3ca ("dm: MIGRATION: Add migration plan for CONFIG_DM") Signed-off-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:27 +0000 (00:12 +0000)]
sunxi: simplify U-Boot proper only builds
At the moment every Allwinner board builds and requires an SPL, even
though we select this individually in each _defconfig file.
For experiments and for early bringup of new SoCs it would be beneficial
to only build U-Boot proper, for instance to postpone a tedious SPL port
(including DRAM support) in the initial phase.
Protect some SPL related symbols that we unconditionally select at the
moment with "if SPL", to avoid Kconfig conflicts when CONFIG_SPL is
disabled.
This alone does not cleanly build U-Boot proper only yet, but gets it
far enough so that the binary can be harvested.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:26 +0000 (00:12 +0000)]
sunxi: remove common.h inclusion
The usage of the common.h include file is deprecated, and has already
been removed from several files.
Get rid of all inclusions in the arch/arm/mach-sunxi directory. Most
files actually don't need the header at all, for the few others just
include the headers that we actually require.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:24 +0000 (00:12 +0000)]
sunxi: sun9i: remove unneeded base addresses from header
The cpu_sun9i.h header file defined the base addresses for quite some
peripherals of the Allwinner A80 CPU, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:23 +0000 (00:12 +0000)]
sunxi: sun4i: remove unneeded base addresses from header
The cpu_sun4i.h header file defined the base addresses for quite some
peripherals of earlier Allwinner CPUs, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
projects / u-boot.git / log