Ilias Apalodimas [Fri, 15 Mar 2024 06:43:47 +0000 (08:43 +0200)]
arm: fix __efi_runtime_rel_start/end definitions
__efi_runtime_rel_start/end are defined as c variables for arm7 only in
order to force the compiler emit relative references. However, defining
those within a section definition will do the same thing since [0].
On top of that the v8 linker scripts define it as a symbol.
So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
the correct section.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for shared object")
Suggested-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com> # Binary output identical Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Ilias Apalodimas [Fri, 15 Mar 2024 06:43:46 +0000 (08:43 +0200)]
arm: clean up v7 and v8 linker scripts for bss_start/end
commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated")
and
commit f84a7b8f54db ("ARM: Fix __bss_start and __bss_end in linker scripts")
were moving the bss_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].
However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable type with
the value being a fixed offset from the base of a section [1].
So let's start cleaning this up starting with the bss_start and bss_end
variables. Convert them into symbols within the .bss section definition.
[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for shared object")
[1] https://sourceware.org/binutils/docs/ld/Expression-Section.html
Ilias Apalodimas [Fri, 15 Mar 2024 06:43:45 +0000 (08:43 +0200)]
arm: baltos: remove custom linker script
commit 3d74a0977f514 ("ti: am335x: Remove unused linker script") removed
the linker script for the TI variant. This linker script doesn't seem to
do anything special and on top of that, has no definitions for the EFI
runtime sections.
So let's get rid of it and use the generic linker script which defines
those correctly
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 15 Mar 2024 13:15:31 +0000 (09:15 -0400)]
Merge tag 'u-boot-rockchip-20240315' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
Please pull the updates for rockchip platform:
- Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC,
Toybrick TB-RK3588X;
rk3588s Cool Pi 4B;
rk3566 Pine64 PineTab2;
- Add saradc v2 support;
- Add PMIC RK806 support;
- rk3588 disable force_jtag by default;
- Migrate to use IO-domain driver for all boards;
- Use common bss and stack addresses for rk33xx and rk35xx boards;
- Other updates for driver, config and dts;
Quentin Schulz [Thu, 14 Mar 2024 09:36:29 +0000 (10:36 +0100)]
rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support
ADC support is implied by the Rockchip arch Kconfig but that means it
should be possible to disable ADC support and still be able to build.
However the weak implementation of rockchip_dnl_key_pressed() currently
blindly use functions from the ADC subsystem which do not exist when ADC
is not enabled, failing the build.
Therefore, let's encapsulate this logic with a check on the ADC symbol
being selected.
Quentin Schulz [Thu, 14 Mar 2024 09:36:27 +0000 (10:36 +0100)]
adc: add missing depends on ADC for controller drivers
The ADC controller drivers are obviously all depending on ADC symbol
being selected.
While they don't seem to fail to build without, they won't be useful
without that symbol selected, so let's make sure the options aren't
shown in menuconfig when ADC isn't selected.
Quentin Schulz [Thu, 14 Mar 2024 09:36:26 +0000 (10:36 +0100)]
rockchip: jaguar-rk3588: enable SARADC and derivatives
The SARADC is used on Jaguar for multiple things:
- channel 0 is used (at runtime) as a BIOS button,
- channel 2 is exposed on the Mezzanine connector for customer specific
logic,
- channel 5 and 6 are used for identification,
Since the SARADC requires a vref-supply provided by the RK806 PMIC, its
support and the support for its regulators are also enabled.
The button, adc, pmic and regulator commands are also enabled for CLI
use in U-Boot for debugging and scripting purposes.
The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable
Rockchip SPI controller driver.
Finally, the SARADC channel 1 on Jaguar is hardwired so will never
change in the lifetime of a unit, for that reason, disable the Rockchip
Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0.
Quentin Schulz [Thu, 14 Mar 2024 09:36:25 +0000 (10:36 +0100)]
power: pmic: rk8xx: fix duplicate prompt
SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it
difficult to know at first glance in menuconfig what's for what, let's
fix this by adding "in SPL" at the end of the prompt for the SPL symbol.
Quentin Schulz [Thu, 14 Mar 2024 09:36:24 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: add support for RK3588
This adds support for the SARADCv2 found on RK3588.
There is no stop callback as it is currently configured in single
conversion mode, where the ADC is powered down after a single conversion
has been made.
Due to what seems to be a silicon bug, a controller reset needs to be
issued before starting a channel conversion otherwise Rockchip says that
channel 1 will error whatever that means. This is aligned with upstream
and downstream Linux kernel as well as downstream U-Boot.
Quentin Schulz [Thu, 14 Mar 2024 09:36:23 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: factor out stop callback
SARADC v2 doesn't have a stop mechanism once in single mode. In series
conversion, the logic is different anyway. Therefore, let's abstract
this function so that it can be provided from the udevice.data pointer.
Quentin Schulz [Thu, 14 Mar 2024 09:36:22 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: factor out start_channel callback
SARADC v1 and v2 have a different way of starting a channel, therefore
let's abstract this function so that it can be provided from the
udevice.data pointer.
Quentin Schulz [Thu, 14 Mar 2024 09:36:21 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: factor out channel_data callback
SARADC v1 and v2 have a different way of reading data, therefore let's
abstract this function so that it can be provided from the udevice.data
pointer.
Quentin Schulz [Thu, 14 Mar 2024 09:36:20 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: use union for preparing for v2
The registers are entirely different between SARADC v1 and SARADC v2, so
let's prepare to add another struct for accessing v2 registers by adding
a union.
Quentin Schulz [Thu, 14 Mar 2024 09:36:18 +0000 (10:36 +0100)]
power: rk8xx: add support for RK806
This adds support for RK806, only the SPI variant has been tested.
The communication "protocol" over SPI is the following:
- write three bytes:
- 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write
- 1 byte: LSB register address
- 1 byte: MSB register address
- write/read length of payload
The CRC is always disabled for now.
The RK806 technically supports I2C as well, and this should be able to
support it without any change, but it wasn't tested.
The DT node name prefix for the buck converters has changed in the
Device Tree and is now dcdc-reg. The logic for buck converters is
however manageable within the current logic inside the rk8xx regulator
driver. The same cannot be said for the NLDO and PLDO.
Because pmic_bind_children() parses the DT nodes and extracts the LDO
index from the DT node name, NLDO and PLDO will have overlapping
indices. Therefore, we need a separate logic from the already-existing
ldo callbacks. Let's reuse as much as possible though.
Quentin Schulz [Thu, 14 Mar 2024 09:36:17 +0000 (10:36 +0100)]
regulator: rk8xx: add indirection level for some ldo callbacks
By passing a rk8xx_reg_info directly to the internal get_value, it'd be
possible to call this same function with a logic for getting the
rk8xx_reg_info different from the current get_ldo_reg, e.g. for NLDO and
PLDO support for RK806.
Quentin Schulz [Thu, 14 Mar 2024 09:36:15 +0000 (10:36 +0100)]
regulator: rk8xx: remove unused functions
Those two functions had their last user removed in commit f9c68a566c4d
("rockchip: phycore_rk3288: remove phycore_init() function") part of
v2023.01 release, so let's do some cleanup here.
Quentin Schulz [Thu, 14 Mar 2024 09:36:14 +0000 (10:36 +0100)]
rockchip: spi: rk_spi: do not write bytes when in read-only mode
The read-only mode is currently supported but only for 16b-aligned
buffers. For unaligned buffers, the last byte will be read in RW mode
right now, which isn't what is desired. Instead, let's put the
controller back into RO mode for that last byte and skip any write in
the xfer loop.
This is required for 3-wire SPI mode where PICO/POCI lanes are shorted
on HW level. This incidentally the recommended design for RK806 PMIC for
RK3588 products.
Ben Wolsieffer [Fri, 8 Mar 2024 03:00:51 +0000 (22:00 -0500)]
rockchip: load env from boot MMC device
Currently, if the environment is stored on an MMC device, the device
number is hardcoded by CONFIG_SYS_MMC_ENV_DEV. This is problematic
because many boards can choose between booting from an SD card or a
removable eMMC. For example, the Rock64 defconfig sets
CONFIG_SYS_MMC_ENV_DEV=1, which corresponds to the SD card. If an eMMC
is used as the boot device and no SD card is installed, it is impossible
to save the environment.
To avoid this problem, we can choose the environment MMC device based on
the boot device. The theobroma-systems boards already contain code to do
this, so this commit simply moves it to the common Rockchip board file,
with some refactoring. I also removed another implementation of
mmc_get_env_dev() from tinker_rk3288 that performed MMC boot device
detection by reading a bootrom register.
This has been tested on a Rock64v2.
Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Chris Morgan [Mon, 5 Feb 2024 18:58:55 +0000 (12:58 -0600)]
board: rockchip: Add early ADC button detect for RGxx3
Add ADC button detect for early SPL stage for RGxx3 device. This is
important because on at least the RG353P and RG353V a clk pin is not
exposed that would allow us to take the eMMC out of the boot path.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 5 Feb 2024 18:58:54 +0000 (12:58 -0600)]
configs: Remove unnecessary options from RGxx3 config
Based on feedback from the mailing list while adding support for a new
device (the Powkiddy X55), correct the config options for the RGxx3
as well to remove unnecessary drivers and increase the SPL stack size.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 5 Feb 2024 18:58:53 +0000 (12:58 -0600)]
board: rockchip: Add support for Powkiddy RGB10MAX3
Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device
is extremely similar to all the other devices and can use the same
bootloader with the same detection logic.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 12 Mar 2024 23:36:15 +0000 (23:36 +0000)]
rockchip: io-domain: Add support for RK3399
Port the RK3399 part of the Rockchip IO-domain driver from linux.
This differs from linux version in that pmu io iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supply that have been configured.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 12 Mar 2024 23:36:14 +0000 (23:36 +0000)]
board: rockchip: Add a common ROCK Pi 4 target
Move ROCK Pi 4 specific board code from the shared evb_rk3399 target
into its own board target and update related defconfigs to use the new
TARGET_ROCKPI4_RK3399 option.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
These functions is excluded from SPL build and BOARD_EARLY_INIT_F is not
enabled for any of the affected boards, so this legacy code is not used.
Rockchip common board code already enable all regulators flagged as
always-on or boot-on in device tree, and fixed/gpio regulators now have
basic reference counting support so the original intent of this code is
no longer valid.
Remove the unneeded and unused code that used to enable usb regulators.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 10 Mar 2024 18:51:00 +0000 (18:51 +0000)]
rockchip: Migrate to use DM_USB_GADGET on RK3328
USB gadget is not working fully as expected on RK3328, it uses a
board_usb_init() function to initialize the DWC2 OTG port.
The board_usb_init() function does not intgrate with the generic phy
framework and as a result the USB phy is not properly configured before
or after USB gadget use.
Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
causing some issues.
Trying to use rockusb or ums command after usb stop result in a freeze
due to usb stop is putting the phy in a suspended state.
=> usb start
=> usb stop
=> ums 0 mmc 0
--> freeze due to usb phy is suspended <--
Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
depending on the most likely usage of the otg port and by migrating to
use DM_USB_GADGET instead of a board_usb_init() function.
The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
Type-C connector, mark these boards dr_mode as peripheral, the most
likely usage is for recovery and image download.
The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
driver from these boards to ensure that the USB_DWC2 driver is used.
The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
and DWC2_OTG is removed from this board.
Enable RockUSB and UMS on all boards with a otg port in peripheral mode.
Also with the migration to DM_USB_GADGET completed the U-Boot specific
change to reorder usb nodes in the soc device tree can be reverted.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 10 Mar 2024 18:50:58 +0000 (18:50 +0000)]
rockchip: board: Prepare for use of DM_USB_GADGET with DWC2_OTG
The board_usb_init() and board_usb_cleanup() functions is always
included when USB_GADGET and USB_GADGET_DWC2_OTG is enabled.
Prepare for a change to use DM_USB_GADGET with DWC2_OTG by adding an
extra ifdef condition. The extra separate ifdef for USB_GADGET prepare
for next patch that adds a g_dnl_bind_fixup() function.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 10 Mar 2024 18:50:57 +0000 (18:50 +0000)]
rockchip: Update the default USB Product ID value
RK3036 is using the USB product id normally used by RK3066B, and RK3328
is using the product id normally used by RK3368.
Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option
for remaining supported Rockchip SoCs to match the product id used in
Maskrom mode.
Also remove a reference to an undefined ROCKCHIP_RK3229 Kconfig symbol.
SPL can safely load U-Boot proper + FDT to [10M, 11.5M) with this layout.
However, on ROCK 5A the SPL stacks is overlapping:
[ -X, 16M) - SPL pre-reloc stack (SPL_STACK)
[15.5M, 16M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[ -X, 16M) - SPL reloc stack (SPL_STACK_R_ADDR)
[ 15M, 16M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
Because bind and probe udevice instanses is allocated on the pre-reloc
malloc heap, there is going to be an overlap when reloc malloc heap
reaches close to 512 KiB of usage.
Migrate to use common bss, stack and malloc heap size and addresses to
mitigate these limitations and allow for a larger U-Boot proper size.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Update for new boards defconfig) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
SPL can safely load U-Boot proper + FDT to [10M, 12M-128K) with this
layout.
Migrate to use common bss, stack and malloc heap size and addresses to
remove this size limitation.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Update for pinetab2-rk3566_defconfig) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 2 Mar 2024 19:16:14 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK3399
With the stack and text base used by U-Boot SPL and proper on RK3399
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.
SPL can safely load U-Boot proper + FDT to [2M, 4M-16K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.
Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 2 Mar 2024 19:16:13 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK3328
With the stack and text base used by U-Boot SPL and proper on RK3328
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.
SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.
Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 2 Mar 2024 19:16:11 +0000 (19:16 +0000)]
rockchip: Add common default bss and stack addresses
On Rockchip the typical aarch64 boot steps are as follows:
- BROM load TPL to SRAM
- TPL init full DRAM
- use stack in SRAM at TPL_STACK addr
- use malloc heap on stack, size is TPL_SYS_MALLOC_F_LEN
- TPL jump back to BROM
- BROM load SPL to beginning of DRAM
- SPL init storage devices
- use bss in DRAM at SPL_BSS_START_ADDR, size is SPL_BSS_MAX_SIZE
- use stack in DRAM at SPL_STACK addr (or CUSTOM_SYS_INIT_SP_ADDR)
- use malloc heap on stack, size is SPL_SYS_MALLOC_F_LEN
- SPL load FIT images from storage to DRAM
- use stack in DRAM at SPL_STACK_R_ADDR
- use new malloc heap on stack, size is SPL_STACK_R_MALLOC_SIMPLE_LEN
- SPL jump to TF-A at 0x40000
- (optional) TF-A load OPTEE
- TF-A jump to U-Boot proper at TEXT_BASE
- U-Boot proper init pre-reloc devices
- use stack in DRAM at CUSTOM_SYS_INIT_SP_ADDR
- use malloc heap on stack, size is SYS_MALLOC_F_LEN
- U-Boot proper relocate to end of usable DRAM
- U-Boot proper init devices and complete boot
SPL have access to full DRAM, however, current configuration for text
base, stack addr and malloc heap size used at the different boot steps
are at risk of overlapping, e.g. when U-Boot proper + FDT grows close
to 1 MiB on RK3328/RK3399 or when pre-reloc and reloc stack and malloc
heap overlap on ROCK 5A.
Fix this by defining safe defaults for bss, stack and malloc size and
addresses. A range at around [60 MiB, 64 MiB) was chosen to be used for
bss and stack until U-Boot proper have been relocated to end of usable
DRAM. The range was primarily chosen to be able to accommodate SoCs with
a small amount of embedded DRAM, e.g. RK3308G has 64 MiB DRAM.
Overiew of the new common memory layout:
[ 0, 2M) - SPL / TF-A / reserved
[ 2M, +X) - U-Boot proper pre-reloc
[ -X, 64M) - bss, stack and malloc heap
During SPL pre-reloc phase:
[ 0, 256K) - SPL binary is loaded by BROM to beginning of DRAM
[ -X, 63M) - SPL pre-reloc stack
[ -32K, 63M) - SPL pre-reloc malloc heap
[63.5M, +32K) - SPL bss
After SPL reloc phase:
[ 0, 256K) - SPL binary
[ 256K, +X) - TF-A image is loaded by SPL
[ 2M, +X) - U-Boot proper + FDT image is loaded by SPL
[ -X, 62M) - SPL reloc stack
[ 60M, 62M) - SPL reloc malloc heap
[ -32K, 63M) - SPL init malloc heap, memory allocated during SPL
pre-reloc phase is still in use at reloc phase
[63.5M, +32K) - SPL bss
Jonas Karlman [Sun, 4 Feb 2024 17:30:35 +0000 (17:30 +0000)]
board: rockchip: Add Pine64 PineTab2
The Pine64 PineTab2 is a tablet computer based on the Rockchip RK3566
SoC. The table features 4/8 GB LPDDR4 RAM and 64/128 GB eMMC storage.
Features tested on a Pine64 PineTab2 8GB v2.0:
- SD-card boot
- eMMC boot
- SPI Flash boot
- USB host
Device tree is imported from linux maintainer branch v6.9-armsoc/dts64,
commit 1b7e19448f8f ("arm64: dts: rockchip: Add devicetree for Pine64
PineTab2").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a minimal generic RK3588S/RK3588 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3588S/RK3588 boards that follow reference board design.
Also fix the alphabetical order of RK3588 boards listed in Makefile and
documentation.
TB-RK3588X board is a Rockchip Toybrick RK3588 based development board.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB Memory LPDDR4x
Mali G610MC4 GPU
2× MIPI-CSI0 Connector
1x 2Lanes PCIe3.0 Connector
1x SATA3.0 Connector
32GB eMMC Module
2x USB 2.0, 2x USB 3.0
1x HDMI Output, 1x HDMI Input
2x Ethernet Port
Functions work normally:
[1] USB2.0 Host
[2] Ethernet0 with PHY RTL8211F
More information can be obtained from the following websites:
[1] https://t.rock-chips.com/en/wiki/EN/tb-rk3588x_en/index.html
[2] http://t.rock-chips.com/
Kernel commits: 8ffe365f8dc7 ("arm64: dts: rockchip: Add devicetree support for TB-RK3588X board") 7140387ff49d ("dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X")
Jonas Karlman [Sun, 25 Feb 2024 22:10:20 +0000 (22:10 +0000)]
phy: rockchip-inno-usb2: Limit changes made to regs
The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.
Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.
When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.
Jonas Karlman [Sun, 25 Feb 2024 22:10:19 +0000 (22:10 +0000)]
phy: rockchip-inno-usb2: Write to correct GRF
On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
that is supported by this driver have the USB2PHY regs in a different
GRF.
When support for RK356x, RK3588 and RK3328 was added this driver was
never updated to use correct GRF and have instead incorrectly written
to wrong GRF for these SoCs.
The default reset values for the USB2PHY have made USB mostly working
even when wrong GRF was used, however, following have been observed:
scanning bus usb@fd840000 for devices...
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
unable to get device descriptor (error=-1)
Fix this by using a regmap from rockchip,usbgrf prop and fall back to
getting a regmap for parent udevice instead of always getting the
common GRF.
Also protect against accidental clear of bit 0 in a reg with offset 0,
only bind driver to enabled otg/host-ports and remove unused headers.
Fixes: 3da15f0b49a2 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568") Fixes: cdf9010f6e17 ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY") Fixes: 9aa93d84038b ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 12:34:04 +0000 (12:34 +0000)]
rockchip: spl: Enable caches to speed up checksum validation
FIT checksum validation is very slow in SPL due to D-cache not being
enabled.
Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation,
from seconds to milliseconds.
This change enables caches in SPL on all Rockchip ARM64 boards, the
Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to
disable caches for a specific board or SoC if needed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Sat, 17 Feb 2024 11:25:00 +0000 (19:25 +0800)]
board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB
Cool Pi CM5 EVB works as a mother board connect with CM5.
CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S
CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header
The dts is from linux-6.8 rc1.
Signed-off-by: Andy Yan <andyshrk@163.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
Andy Yan [Sat, 17 Feb 2024 11:24:59 +0000 (19:24 +0800)]
board: rockchip: Add support for rk3588s based Cool Pi 4B
CoolPi 4B is a rk3588s based SBC.
Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header
The dts is from linux-6.8 rc1.
Signed-off-by: Andy Yan <andyshrk@163.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:05 +0000 (21:51 +0800)]
rockchip: rk3399: Read cpuid and generate MAC address from efuse
The rockchip-efuse driver supports the efuse found on RK3399. This
hardware block is part of the SoC and contains the CPUID, which can
be used to generate stable serial numbers and MAC addresses.
Enable the driver and reading cpuid by default for RK3399.
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:04 +0000 (21:51 +0800)]
rockchip: rk3328: Read cpuid and generate MAC address from efuse
The rockchip-efuse driver supports the efuse found on RK3328. This
hardware block is part of the SoC and contains the CPUID, which can
be used to generate stable serial numbers and MAC addresses.
Enable the driver and reading cpuid by default for RK3328.
Booting from SPI was already allowed before this commit was first
introduced. A few lines further down the exact same code already existed
and still does.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:36 +0000 (00:22 +0000)]
rng: rockchip: Use same compatible as linux
Replace the rockchip,cryptov1-rng compatible with compatibles used in
the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC
device tree from linux.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:35 +0000 (00:22 +0000)]
gpio: rockchip: Use gpio alias id as gpio bank id
The U-Boot driver try to base the gpio bank id on the gpio-ranges prop
and fall back to base the bank id on the node name. However, the linux
driver try to base the bank id on the gpio alias id and fall back on
node order.
This can cause issues when SoC DT is synced from linux and gpioX@ nodes
has been renamed to gpio@ and gpio-ranges or a SoC specific alias has
not been assigned.
Try to use the gpio alias id as first fallback when a gpio-ranges prop
is missing to ease sync of updated SoC DT. Keep the current fallback on
node name as a third fallback to not affect any existing unsynced DT.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:34 +0000 (00:22 +0000)]
rockchip: rk3328: Fix loading FIT from SD-card when booting from eMMC
When RK3328 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there is a fallback to
read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card will fail:
U-Boot SPL 2024.04-rc1 (Feb 05 2024 - 22:18:22 +0000)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC2
Card did not respond to voltage select! : -110
spl: mmc init failed with error: -95
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update defconfig for rk3328-orangepi-r1-plus boards with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
&gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.
Add PHY_ROCKCHIP_INNO_USB2=y option to support the onboard USB PHY.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add missing device tree files to MAINTAINERS file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:32 +0000 (00:22 +0000)]
rockchip: rk3328-nanopi-r2: Update defconfig
Update defconfig for rk3328-nanopi-r2* boards with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
&gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add DM_REGULATOR_GPIO=y and SPL_DM_REGULATOR_GPIO=y to support the
regulator-gpio compatible.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add missing device tree files to MAINTAINERS file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:31 +0000 (00:22 +0000)]
rockchip: rk3328-rock-pi-e: Update defconfig
Update defconfig for rk3328-rock-pi-e with new defaults.
Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_MDIO=y to ensure device tree props can be used by PHY driver.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add myself as a reviewer for this board.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:30 +0000 (00:22 +0000)]
rockchip: rk3328-roc-cc: Update defconfig
Update defconfig for rk3328-roc-cc with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands. Also add CMD_POWEROFF=y to be able to use the poweroff command.
Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common
ethernet PHYs.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Also add missing device tree file to MAINTAINERS and add myself as a
reviewer for this board.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:29 +0000 (00:22 +0000)]
rockchip: rk3328-rock64: Update defconfig
Update defconfig for rk3328-rock64 with new defaults.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands. Also add CMD_POWEROFF=y to be able to use the poweroff command.
Remove the NET_RANDOM_ETHADDR=y option, ethaddr and eth1addr is set
based on cpuid read from eFUSE.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Also add missing device tree file to MAINTAINERS and add myself as a
reviewer for this board.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 17 Feb 2024 00:22:28 +0000 (00:22 +0000)]
rockchip: rk3328-evb: Update defconfig
Update defconfig for rk3328-evb with new defaults.
Add DM_RESET=y to support using reset signals.
Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL.
Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.
Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.
Add MISC_INIT_R=y, ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y,
ethaddr and eth1addr is set based on cpuid read from eFUSE.
Remove pinctrl-0 and pinctrl-names from CONFIG_OF_SPL_REMOVE_PROPS,
SPL need to configure pinctrl for e.g. SD-card.
Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.
Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common
ethernet PHYs.
Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.
Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.
Add SYSINFO=y to support the sysinfo uclass.
Also add missing device tree files to MAINTAINERS and remove the
obsolete README file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Commit 2027e99e61aa ("Makefile: Run defconfig files through the C
preprocessor") adds `generated_defconfig' file, but fails to clean that
up. It might be useful to have that file around after `make' is done,
but it's better to clean that up on `make clean'. Also we probably want
to hide it in `git status' list. This patch makes the described changes,
and also adds `-P' parameter to the CPP command that produces the
`generated_defconfig' to avoid generating linemarkers.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: 2027e99e61aa ("Makefile: Run defconfig files through the C preprocessor") Acked-by: Andrew Davis <afd@ti.com>
Maxim Moskalets [Thu, 7 Mar 2024 21:29:14 +0000 (00:29 +0300)]
cmd: add FDT setup for bootelf by flag
Added the ability to use FDT for ELF applications, required to run some
OS. To make FDT setup, you need to set the -d fdt_addr_r cmd option for
bootelf command. Enable by selecting CMD_ELF_FDT_SETUP.
Masahisa Kojima [Wed, 6 Mar 2024 06:11:10 +0000 (15:11 +0900)]
board: developerbox: fix mem_map setup timing
The setup of global variable mem_map was moved into enable_caches()
by commit a70c75cabae1 ("board: developerbox: move mem_map setup later")
since U-Boot was directly booted from NOR flash in XIP
and bss is not yet available in dram_init() at that time.
This has a problem, mem_map variable is used by
the get_page_table_size() to calculate the page table size,
but get_page_table_size() is called earlier than enable_caches()
which fills mem_map variable. With that, U-Boot fails to boot when
64GB DIMM is installed.
Currently U-Boot on the Developerbox board is not booted in XIP
and bss is available in dram_init(), let's move mem_map setup
in dram_init().
Signed-off-by: Masahisa Kojima <kojima.masahisa@socionext.com>
Andrew Davis [Tue, 5 Mar 2024 16:19:37 +0000 (10:19 -0600)]
arm: dts: k3-am64: Move to OF_UPSTREAM
Enable OF_UPSTREAM for AM64-EVM and SK-AM64 boards. Remove DT files that
are now available in dts/upstream. Update the appended files based on
version of latest OF_UPSTREAM sync point (v6.7-rc7).
Caleb Connolly [Tue, 5 Mar 2024 14:55:13 +0000 (14:55 +0000)]
initcall: break loop immediately on failure
The current ordering always results in func pointing to the next
function in the init_sequence. e.g. if fdtdec_setup() fails, ret will
be set to the error code, then func will be updated to point to
initf_malloc(), only then is ret checked and the loop broken. The end
result of this is that the "initcall failed at ..." error will point you
to initf_malloc(), when the error actually occured in fdtdec_setup()!
This can be quite confusing and result in a lot of time wasted debugging
code that has nothing to do with the failure (ask me how I know :P).
Adjust the for loop to check ret immediately after the call and break
early so that func will correctly reference the failed function.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Hanyuan Zhao [Tue, 5 Mar 2024 07:37:35 +0000 (15:37 +0800)]
cli: allow users to determine history buffer allocation method
This commit allows users to choose the appropriate memory
allocation method between static allocated and dynamically
calloc. The previous static-array way will not obviously
contribute to the final binary size since it is uninitialized,
and might have better performance than the dynamical one.
Now we provide the users with both the two options.
Hanyuan Zhao [Tue, 5 Mar 2024 07:37:33 +0000 (15:37 +0800)]
cli: panic when failed to allocate memory for the history buffer
This commit simply modifies the history initialize function,
replacing the return value by panic with reasons. The calling
chains of hist_init don't have steps explicitly throwing or
dealing with the ENOMEM error, and once the init fails, the
whole system is died. Using panic here to provide error
information instead.
Tom Rini [Mon, 4 Mar 2024 15:26:17 +0000 (10:26 -0500)]
boards: Remove empty BOARD_SPECIFIC_OPTIONS
While there are currently uses for a stanza of "config BOARD_SPECIFIC_OPTIONS"
followed by "def_bool y" and a series of select/imply statements, having
this option set followed by nothing else doesn't provide anything.
Remove these stanzas.
Marek Vasut [Sat, 2 Mar 2024 22:54:02 +0000 (23:54 +0100)]
fdt: Fix bootm_low handling
According to README CFG_SYS_BOOTMAPSZ section, in case both "bootm_low" and
"bootm_size" variables are defined, "bootm_mapsize" variable is not defined
and CFG_SYS_BOOTMAPSZ macro is not defined, all data for the Linux kernel
must be between "bootm_low" and "bootm_low" + "bootm_size".
Currently, for systems with DRAM between 0x4000_0000..0x7fff_ffff and with
e.g. bootm_low=0x60000000 and bootm_size=0x10000000, the code will attempt
to reserve memory from 0x4000_0000..0x4fff_ffff, which is incorrect. This
is because "bootm_low" is not taken into consideration correctly.
The last parameter of lmb_alloc_base() is the maximum physical address of
the to be reserved LMB area. Currently this is the start of DRAM bank that
is considered for LMB area reservation + min(DRAM bank size, bootm_size).
In case bootm_low is set to non-zero, this maximum physical address has to
be shifted upward, to min(DRAM bank start + size, bootm_low + bootm_size),
otherwise the reserved memory may be below bootm_low address.
In case of multiple DRAM banks, the current change reserves top part of
the first bank, and reserves the rest of memory in the follow up banks.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Wed, 13 Mar 2024 14:10:25 +0000 (10:10 -0400)]
Merge patch series "Introduce basic support for TI's AM62Px SoC family"
Bryan Brattlof <bb@ti.com> says:
Hello Again Everyone!
The AM62Px is an extension of the existing Sitara AM62x low-cost family
of application processors built for Automotive and Linux Application
development. Scalable Arm Cortex-A53 performance and embedded features,
such as: multi high-definition display support, 3D-graphics
acceleration, 4K video acceleration, and extensive peripherals make the
AM62Px well-suited for a broad range of automation and industrial
application, including automotive digital instrumentation, automotive
displays, industrial HMI, and more.
Some highlights of AM62P SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Dual/Single core variants are provided in the same package to allow HW
compatible designs.
* One Device manager Cortex-R5F for system power and resource
management, and one Cortex-R5F for Functional Safety or
general-purpose usage.
* One 3D GPU up to 50 GLFOPS
* H.264/H.265 Video Encode/Decode.
* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure
boot, debug security and crypto acceleration and trusted execution
environment.
* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
enabling battery powered system design.
For those interested, more details about this SoC can be found in the
Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83
Bryan Brattlof [Tue, 12 Mar 2024 20:20:31 +0000 (15:20 -0500)]
arm: mach-k3: fixup whitespace in SPDX License IDs
The SPDX ID format usese a single space used after the
'SPDX-License-Identifier:'. Fix all files that use any other white-space
character other than a single space.
projects / u-boot.git / log