Sergej Stepanov [Wed, 17 Oct 2007 09:18:42 +0000 (11:18 +0200)]
changes for IDS8247 board support
To get the IDS8247 board working following are done:
- FCC2 is deactivated
- FCC1 is activated
- I2C is activated
- CFI driver is activated
- Adapted for use with LIBFDT
Wolfgang is right: It's not a good idea to set up default initial
ethernet addresses for a board, even though they belong to the local
range.
This will change the failure mode from "IT manager screams at you for
using duplicate ethernet addresses" to a nice error message explaining
that the ethernet address hasn't been set properly.
Found a bug in the way the DHCP Request packet is built, where the IP address
that is offered by the server is bound to prematurely. This patch is a fix of
that bug where the IP address offered by the DHCP server is not used until
after the DHCP ACK from the server is received.
Signed-off-by: Justin Flammia <jflammia@savantav.com> Signed-off-by: Ben Warren <bwarren@qstreams.com>
Martin Krause [Wed, 24 Oct 2007 06:42:25 +0000 (08:42 +0200)]
TQM5200: fix spurious characters on second serial interface
With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Martin Krause [Wed, 24 Oct 2007 06:41:27 +0000 (08:41 +0200)]
TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Martin Krause [Mon, 22 Oct 2007 14:45:53 +0000 (16:45 +0200)]
TQM5200: fix spurious characters on second serial interface
With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Martin Krause [Mon, 22 Oct 2007 14:40:06 +0000 (16:40 +0200)]
TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Marcel Ziswiler [Thu, 18 Oct 2007 22:25:33 +0000 (00:25 +0200)]
fix pxa255_idp board
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Bartlomiej Sieka [Tue, 23 Oct 2007 11:14:10 +0000 (13:14 +0200)]
Motion-PRO: Update configuration to accomodate next generation board.
New board has faster oscillator and a different Flash chip. This affects:
- CFG_MPC5XXX_CLKIN
- SDRAM timings
- Flash CS configuration (timings)
- Flash sector size, and thus MTD partition layout
- malloc() arena size (due to bigger Flash sectors)
- smaller memory test range (due to bigger malloc() arena)
This patch also enables more extensive memory testing via "mtest".
Bartlomiej Sieka [Tue, 23 Oct 2007 09:36:07 +0000 (11:36 +0200)]
Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.
Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.
Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use.
As a general principle, we should use _gp for $gp.
Thanks to linker script's help we fortunately have _gp which equals to
_GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not
be able to access to GOT entires, global variables and procedure entry
points. The right thing to do is to use _gp.
This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_'
which holds the offset from _gp. When updating GOT entries, we use this
offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_.
This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then
I made some change to leave over num_got_entries.
Vlad Lungu [Thu, 4 Oct 2007 17:47:10 +0000 (20:47 +0300)]
Fix NE2000 driver:
Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try
to do anything in eth_stop() if eth_init() was not called.
Simplified RX path in order to avoid timeouts on really really
fast NE2000 cards (read: qemu with internal tftp), NetLoop() is
clever enough to cope with 1 packet per eth_rx().
Dan Wilson [Fri, 19 Oct 2007 16:33:48 +0000 (11:33 -0500)]
tsec driver should clear RHALT on startup
This was causing problems for some people.
Signed-off-by: Alain Gravel <agravel@fulcrummicro.com> Signed-off-by: Dan Wilson <dwilson@fulcrummicro.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Thu, 11 Oct 2007 05:29:18 +0000 (00:29 -0500)]
Improve handling of PCI interrupt device tree fixup on MPC85xx CDS
On the MPC85xx CDS we have two issues:
1. The device tree fixup code did not check to see if the property we are
trying to update is actually found. Its possible that it would update
random memory starting at 0.
2. Newer Linux kernel's have moved the location of the PCI nodes to be
sibilings of the soc node and not children. The explicit PATH to the PCI
node would not be found for these device trees. Add the ability to handle
both paths. In the future we shouldn't handle such fixups by explicit path.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 11 Oct 2007 05:18:48 +0000 (00:18 -0500)]
Set OF_STDOUT_PATH to match the default console on MPC8568 MDS
On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured
console. Make it so we match that config what we tell Linux as the early
STDOUT console.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jon Loeliger [Mon, 27 Aug 2007 17:41:03 +0000 (12:41 -0500)]
86xx: Allow for fewer DDR slots per memory controller.
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.
Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.
Rodolfo Giometti [Mon, 15 Oct 2007 09:59:17 +0000 (11:59 +0200)]
PXA USB OHCI: "usb stop" implementation.
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Stefan Roese [Mon, 15 Oct 2007 09:39:00 +0000 (11:39 +0200)]
ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier
The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.
This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.
Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.
This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Martin Krause [Thu, 27 Sep 2007 12:54:36 +0000 (14:54 +0200)]
TQM866M: fix SDRAM refresh
At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 97. This result
in a refresh rate of 4 * 7.8 us at the default clock
50 MHz. At 133 MHz the value will be then 4 * 2.9 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
CFG_MEMTEST_START uses weird magic involving gd, which fails to
compile. Use hardcoded values instead (we actually know how much RAM
we have on board.)
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