The designware eth driver registers an mdio bus during probe, but if no
PHY is found, this bus is never removed although probe failes and the
driver is shown as not probed in the dm tree.
This later leads to errors when e.g. the mii or mdio commands try to
use available mdio buses because the mdio bus is still registered but
all corresponding data structures are invalid because probe failed.
Fix this by unregistering the mdio bus on probe failure (just as it is
unregistered in the .remove callback, too).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
cmd: mdio: prevent data abort when no mdio bus is found
Calling 'mdio read ...' currently leads to a data abort when no mdio
bus is found.
To fix this, check if 'bus' is a valid pointer before accessing it.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean [Fri, 12 Jul 2019 07:13:51 +0000 (10:13 +0300)]
doc: bindings: Add description for MDIO MUX dts nodes
Adds a short bindings document describing the expected structure of a MDIO
MUX dts node. This is based on Linux binding and the example is in fact
copied from there.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Alex Marginean [Fri, 12 Jul 2019 07:13:50 +0000 (10:13 +0300)]
net: add MDIO_MUX DM class
Adds a class for MDIO MUXes, which control access to a series of
downstream child MDIOs.
MDIO MUX drivers are required to implement a select function used to switch
between child buses.
MUX children are registered as MDIO buses and they can be used just like
regular MDIOs.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean [Thu, 11 Jul 2019 15:32:56 +0000 (18:32 +0300)]
net: add comments to phy APIs
Added a comment on the limitations of phy_find_by_mask API when scanning
MDIO buses with multiple PHYs present. Added short descriptions to the
other APIs in phy.h for consistency.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Alex Marginean [Fri, 5 Jul 2019 09:28:55 +0000 (12:28 +0300)]
drivers: net: phy: Ignore PHY ID 0 during PHY probing
Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
drivers: net: phy: Use Aquantia driver for AQR112, AQR412
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Andre Przywara [Sun, 23 Jun 2019 14:09:50 +0000 (15:09 +0100)]
sunxi: H6: Enable USB for existing boards
So far USB was not enabled for the Allwinner H6 boards, as the PHY
driver was not ready and the clock gates were missing. Since this is now
fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for
all existing H6 boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Sun, 23 Jun 2019 14:09:49 +0000 (15:09 +0100)]
sunxi: phy: Add USB PHY support for Allwinner H6
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual),
which require a small addition to the USB PHY driver:
In this case the second PHY is PHY3, not PHY1, so we need to skip number
1 and 2 in the code. Just use the respective code from Linux for that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Sun, 23 Jun 2019 14:09:48 +0000 (15:09 +0100)]
sunxi: clocks: Add H6 USB clock gates and resets
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add some basic line delay values to be used with DDR3 DRAM chips on
some H6 TV boxes.
Taken from a register dump after boot0 initialised the DRAM.
Put them as the default delay values for DDR3 DRAM until we know better.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Mon, 15 Jul 2019 01:27:08 +0000 (02:27 +0100)]
sunxi: H6: Add DDR3-1333 timings
Add a routine to program the timing parameters for DDR3-1333 DRAM chips
connected to the H6 DRAM controller.
The values were gathered from doing back-calculations from a register
dump, trying to match them up with the official JEDEC DDDR3 spec.
If in doubt, the register dump values were taken for now, but the JEDEC
recommendation were added as a comment.
Many thanks to Jernej for contributing fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Mon, 15 Jul 2019 01:27:07 +0000 (02:27 +0100)]
sunxi: H6: Add DDR3 support to DRAM controller driver
At the moment the H6 DRAM driver only supports LPDDR3 DRAM.
Extend the driver to cover DDR3 DRAM as well.
The changes are partly motivated by looking at the ZynqMP register
documentation, partly by looking at register dumps after boot0/libdram
has initialised the controller.
Many thanks to Jernej for contributing some fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Mon, 15 Jul 2019 01:27:06 +0000 (02:27 +0100)]
sunxi: H6: move LPDDR3 timing definition into separate file
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.
Follow this recommendation by setting bit 0 in a separate step.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Mon, 15 Jul 2019 01:27:04 +0000 (02:27 +0100)]
sunxi: H6: DRAM: avoid memcpy() on MMIO registers
Using memcpy() is, however tempting, not a good idea: It depends on the
specific implementation of memcpy, also lacks barriers. In this
particular case the first registers were written using 64-bit writes,
and the last register using four separate single-byte writes.
Replace the memcpy with a proper loop using the writel() accessor.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Radu Pirea [Fri, 7 Jun 2019 11:18:36 +0000 (14:18 +0300)]
net: macb: Add support for 1000-baseX
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX
phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and
LPA_1000XHALF bits.
Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Radu Pirea [Fri, 7 Jun 2019 11:18:35 +0000 (14:18 +0300)]
net: macb: Fixed reading MII_LPA register
If macb is gem and is gigabit capable, lpa value is not read from
the right register(MII_LPA) and is read from MII_STAT1000. This patch
fixes reading of the lpa value.
Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Independent Interface (RMII), and the Management Data Input/Output (MDIO)
interface for physical layer device (PHY) management. The TI AM65x SoC has
integrated two-port Gigabit Ethernet Switch subsystem into device MCU
domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
and RMII interfaces and an internal Communications Port Programming
Interface (CPPI) port (Host port 0).
Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
channels and on RX channels operating by TI am654 NAVSS Unified DMA
Peripheral Root Complex (UDMA-P) controller.
Horatiu Vultur [Sun, 9 Jun 2019 13:27:29 +0000 (15:27 +0200)]
net: mscc: refactor mscc_miim
Because all MSCC SoC use the same MDIO bus, put the implementation in
one common file(mscc_miim) and make all the other MSCC network drivers to
use these functions.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean [Mon, 3 Jun 2019 16:12:28 +0000 (19:12 +0300)]
test: dm: add MDIO test
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean [Mon, 3 Jun 2019 16:10:30 +0000 (19:10 +0300)]
net: introduce MDIO DM class for MDIO devices
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices. Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Horatiu Vultur [Thu, 23 May 2019 19:45:33 +0000 (21:45 +0200)]
net: mscc: serval: Remove delay when serdes is configured
When serdes configuration was written in hardware there was a delay
of 100ms to be sure that configuration was written. But the delay is not
needed because already the function serdes_write it is checking that the
operation finished.
Therefore remove the mdelay. This improves the speed of configuring the
network driver.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Trent Piepho [Fri, 10 May 2019 17:49:08 +0000 (17:49 +0000)]
net: phy: ti: Fix clock output DT property
The code block reading the DT property for the clock output control was
before the phy's DT node pointer was set, so it could never work. Move
it after the node pointer is set.
Also store the unsigned 32-bit property into an unsigned value, not a
signed value, as the former will cause a problem if value overflows.
For instance, if one were to add 0xffffffff as a code to mean the clock
output should be turned off.
Trent Piepho [Thu, 9 May 2019 19:41:51 +0000 (19:41 +0000)]
net: phy: ti: Use default values for tx/rx delay and fifo size
When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver. When using DM_ETH, they should come
from the device tree. However, if the device tree does not have the
properties, the driver will silent use -1. Which is entirely out of
range, programs nonsense into the PHY's registers, and does not work.
Change this to use the same defaults as non-DM_ETH if the device tree is
lacking the properties.
As an alternative, the kernel driver for the phy will display an error
message and fail if the device tree is lacking.
Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Trent Piepho [Thu, 9 May 2019 19:23:39 +0000 (19:23 +0000)]
cmd: mii: Refactor some of the MII reg dump code
Share the code that prints out a register field with the function that
prints out the "special" fields.
There were two arrays the register dump list, one with reg number and
name, another with a pointer to the field table and the table size.
These two arrays had have each entry match what register is referred to.
Combine them into just one table. Now they can't not match and there is
just one table.
Add some missing consts to pointers to string literals.
The dump code was ignoring the regno field in the description table and
assuming register 0 was at index 0, etc. Have it use the field.
Change reg > max+1 into reg >= max, which doesn't fail if max+1 could
overflow, besides just making more sense.
Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 15 Jul 2019 13:42:41 +0000 (09:42 -0400)]
Merge tag 'mmc-2019-7-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- mmc spi driver model support
- drop mmc_spi command
- enhanced Strobe mmc HS400 support
- minor mmc bug/fixes and optimization
- omap hsmmc and mvbeu update
- sdhci card detect support
Marcus Cooper [Sun, 2 Jun 2019 06:38:40 +0000 (08:38 +0200)]
sun8i: h3: Add support for the Beelink-x2 STB
The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a
dual colour LED and an optical S/PDIF connector.
Linux commit details about the sun8i-h3-beelink-x2.dts sync:
"ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2"
(sha1: cc4bddade114b696ab27c1a77cfc7040151306da)
Signed-off-by: Marcus Cooper <codekipper@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Mon, 27 May 2019 00:45:11 +0000 (01:45 +0100)]
sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to Kconfig
The choice of the SPL_TEXT_BASE is not really a decision that should be
specified by each board's defconfig, as this setting is actually
dictated by the SoC's memory map and the BootROM behaviour.
To make this obvious and reduce the clutter in the defconfig files,
let's specify the SoC constraints in the Kconfig stanza.
This allows us to remove these lines from the defconfig files again.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Peng Fan [Wed, 10 Jul 2019 09:35:30 +0000 (09:35 +0000)]
mmc: fsl_esdhc_imx: enlarge mmc timeout
Flash system partition with fastboot will earse the partition firstly
The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make
it works for most of sdcard
Cc: guoyin.chen <guoyin.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 10 Jul 2019 06:43:07 +0000 (14:43 +0800)]
mmc: support hs400 enhanced strobe mode
eMMC 5.1+ supports HS400 Enhances Strobe mode without the need for
tuning procedure.
The flow is as following:
- set HS_TIMIMG (Highspeed)
- Host change freq to <= 52Mhz
- set the bus width to Enhanced strobe and DDR8Bit(CMD6),
EXT_CSD[183] = 0x86 instead of 0x80
- set HS_TIMING to 0x3 (HS400)
- Host change freq to <= 200Mhz
- Host select HS400 enhanced strobe complete
Ye Li [Thu, 11 Jul 2019 03:29:02 +0000 (03:29 +0000)]
mmc: fsl_esdhc_imx: fix config check issue when building in SPL
Should use CONFIG_IS_ENABLED not IS_ENABLED for clock and regulator drivers,
CONFIG_IS_ENABLED will check the CONFIG_SPL_CLK and CONFIG_SPL_DM_REGULATOR
when building SPL.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The mmc_spi command was added to manually setup MMC over SPI bus
using command. This was required by the legacy non-DM MMC_SPI driver.
With DM based MMC_SPI driver in-place, we can now use all general
storge commands and mmc command for MMC over SPI bus hence we remove
the mmc_spi command all it's references.
Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
mmc: do not change mode when accessing a boot partition
Accessing the boot partition had been error prone with HS200 and HS400 and
was disabled. The driver first switched to a lesser mode and then switched
the partition access. It was mostly due to a bad handling of the switch and
has been fixed, so let's remove this 'feature'
mmc: During a switch, poll on dat0 if available and check the final status
The switch operation can sometimes make the bus unreliable, in that case
the send_status parameter should be false to indicate not to poll using
CMD13. If polling on dat0 is possible, we should use it to detect the end
of the operation.
At the end of the operation it is safe to use CMD13 to get the status of
the card. It is important to do so because the operation may have failed.
mmc: When switching partition, use the timeout specified in the ext_csd
The e-MMC spec allows the e-MMC to specify a timeout for the partition
switch command. It can take up to 2550 ms. There is no lower limit to this
value in the spec, but do as the the linux driver does and force it to be
at least 300ms.
Using the DAT0 line as a rdy/busy line is an alternative to reading the
status register of the card. It especially useful in situation where the
bus is not in a good shape, like when modes are switched.
This is also how the linux driver behaves.
Note of warning: As per the specification, while polling on DAT0 the CLK
must not turned off: "[...] Without a clock edge the Device (unless
previously disconnected by a deselect command (CMD7)) will force the DAT0
line down, forever. [...]"
mmc: add mmc_poll_for_busy() and change the purpose of mmc_send_status()
mmc_send_status() is currently used to poll the card until it is ready, not
actually returning the status of the card.
Make it return the status and add another function to poll the card.
Also remove the 'extern' declaration in the mmc-private.h header to comply
with the coding standard.
mmc: omap_hsmmc: reset FSM for DAT and CMD lines if needed before a new command
It sometimes happen that the PSTATE register does not indicate that the
bus is ready when it really is. This usually happens after a mode switch.
In that case it makes sense to reset the FSM handling the CMD and DATA
Also reset the FSMs if the STATE register cannot be cleared. This also
sometimes happens after a mode switch.
T Karthik Reddy [Tue, 25 Jun 2019 11:39:03 +0000 (13:39 +0200)]
mmc: sdhci: Read cd-gpio from devicetree
This patch reads cd-gpio property from devicetree
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Sun, 14 Jul 2019 13:09:49 +0000 (09:09 -0400)]
Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- syscon: add support for power off
- stm32mp1: add op-tee config
- stm32mp1: add specific commands: stboard and stm32key
- add stm32 mailbox driver
- solve many stm32 warnings when building with W=1
- update stm32 gpio driver
Adam Ford [Wed, 12 Jun 2019 20:26:26 +0000 (15:26 -0500)]
ARM: dts: logicpd som-lvs and torpedos: Shrink SPL DTB
Since we have limited resources in SPL, it is the best interest
to keep the SPL as small as possible and that includes the DTB.
There are a few items in the device tree that can be removed,
because these boards don't use them.
Heiko Schocher [Wed, 12 Jun 2019 04:11:46 +0000 (06:11 +0200)]
gpio: add gpio-hog support
add gpio-hog support. GPIO hogging is a mechanism
providing automatic GPIO request and configuration
as part of the gpio-controller's driver probe function.
for more infos see:
doc/device-tree-bindings/gpio/gpio.txt
Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Michal Simek <michal.simek@xilinx.com> (zcu102) Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Adam Ford [Mon, 10 Jun 2019 18:25:08 +0000 (13:25 -0500)]
ARM: davinci: da850: Manual pinmux only when PINCTRL not available
With a recent update to the pinctrl-single driver and the fact
that the da850evm has both DM and OF_CONTROL working in both SPL
and U-Boot, some of the manual pinmuxing can be setup to only
be activated when either the driver doesn't have DM for it, or
when CONFIG_PINMUX isn't available (only during SPL). If the
code ever shrinks enough to support PINCTRL in SPL, a lot of this
can go away. This also remove some manual pinmuxing not needed
by SPL to give SPL a little more breathing room.
Adam Ford [Mon, 10 Jun 2019 18:15:55 +0000 (13:15 -0500)]
pinctrl: pinctrl-single: Add 'pinctrl-single, bits' support
The TI Davinci (da850/l138/am1808) use pinctrl-single,bits for
pinmuxing peripherals. This patch allosw the pinctrl-single
driver to parse the pinctrl-single,bits options and correctly
setup devices.
Tom Rini [Sat, 8 Jun 2019 16:46:18 +0000 (12:46 -0400)]
configs: Make USE_TINY_PRINTF depend on SPL||TPL and be default
The USE_TINY_PRINTF symbol only changes things within SPL and TPL
builds, so make it depend on that support. Next, make it default as
within these cases we should rarely have need of more advanced print
formats outside of the debug context.
To do this, in a few cases we need to correct our Kconfig dependencies
as we had cases of non-SPL targets select'ing this symbol. Finally, in
the case of a few boards we really do need the full printf
functionality.
Keerthy [Thu, 6 Jun 2019 10:36:56 +0000 (16:06 +0530)]
power: regulator: Kconfig: Add SPL_DM_REGULATOR configs for palmas/lp873x/lp87565
Add SPL_DM_REGULATOR configs for palmas/lp873x/lp87565. These were missing
and the Makefile already assumes them to be defined. Add the corresponding
SPL config options. This enables the regulator support in SPL.
Keerthy [Thu, 6 Jun 2019 10:36:55 +0000 (16:06 +0530)]
power: pmic: Kconfig: Add SPL_PMIC configs for palmas/lp873x/lp87565
Add SPL_PMIC configs for palmas/lp873x/lp87565. These were missing
and the Makefile already assumes them to be defined. Add the corresponding
SPL config options. This enables the pmics in SPL.
Derald D. Woods [Tue, 28 May 2019 02:22:00 +0000 (21:22 -0500)]
usb: musb-new: omap2430: Fix compilation warning with USB_MUSB_GADGET
This commit addresses the following warning, when _NOT_ USB_MUSB_HOST:
[...]
CC drivers/usb/gadget/f_mass_storage.o
CC drivers/usb/musb-new/omap2430.o
CC drivers/usb/gadget/f_fastboot.o
CC env/common.o
CC env/env.o
/src/etinker/software/u-boot-master/drivers/usb/musb-new/omap2430.c: In function ‘omap2430_musb_probe’:
/src/etinker/software/u-boot-master/drivers/usb/musb-new/omap2430.c:239:6: warning: assignment to ‘int’ from ‘struct musb *’ makes integer from pointer without a cast [-Wint-conversion]
ret = musb_register(&platdata->plat,
^
LD drivers/usb/host/built-in.o
CC drivers/usb/gadget/f_sdp.o
CC fs/ext4/ext4fs.o
[...]
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Derald D. Woods [Tue, 28 May 2019 02:20:50 +0000 (21:20 -0500)]
ARM: omap3: evm: Enable DM_USB in defconfig
This addresses the following warning message:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
As USB support for older OMAP3 SoC's improves, OMAP3 EVM can be
readily adapted. There is some additional 'gpio-hog' support
needed to fully setup USB in a similar manner to Linux.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Ezequiel Garcia [Sat, 25 May 2019 22:25:22 +0000 (19:25 -0300)]
mmc: Register only the first MMC device on MMC_TINY
When MMC_TINY is enabled, support for only one MMC device
is provided. Boards that register more than one device,
will just write over mmc_static keeping only the last one
registered.
This commit prevents this, keeping only the first MMC
device created. A debug warning message is added, if nothing
else, as a hint/documentation for developers.
Ezequiel Garcia [Sat, 25 May 2019 22:25:21 +0000 (19:25 -0300)]
spl: Move SPL_MMC_TINY option to appear under SPL menu
The SPL_MMC_TINY implements feature-reduced MMC support
on SPL, and as such, it's more consistent and convenient
to find it as part of the SPL configuration.
Leo Ruan [Fri, 24 May 2019 15:20:19 +0000 (17:20 +0200)]
cmd: nvedit: Add sub-command 'env info'
Add sub-command 'env info' to display environment information:
- env_valid : is environment valid
- env_ready : is environment imported into hash table
- env_use_default : is default environment using
This command can be optionally used for evaluation in scripts:
[-d] : evaluate whether default environment is used
[-p] : evaluate whether environment can be persisted
The result of multiple evaluations will be combined with AND.
Signed-off-by: Leo Ruan <tingquan.ruan@cn.bosch.com> Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com> Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Do not enable by default] Signed-off-by: Tom Rini <trini@konsulko.com>
Peng Fan [Wed, 22 May 2019 07:08:14 +0000 (07:08 +0000)]
drivers: core: use strcmp when find device by name
`if (!strncmp(dev->name, name, strlen(name)))` might find out
the wrong device, it might find out `dram_pll_ref_sel`, when name is
`dram_pll`. So use strcmp to avoid such issue.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Tue, 21 May 2019 10:04:31 +0000 (12:04 +0200)]
pci: ensure enumeration of all devices in pci_init
Use the uclass_first_device_check and uclass_next_device_check functions
instead of uclass_first_device and uclass_next_device in pci_init. This
ensures that all PCI devices are tried to be probed. Currently if a
device fails to probe, the enumeration stops and the devices which come
after the failed device are not probed.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: VlaoMao <vlaomao@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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