]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
5 years agowatchdog: Split WDT from SPL_WDT
Marek Vasut [Sun, 9 Jun 2019 01:46:21 +0000 (03:46 +0200)]
watchdog: Split WDT from SPL_WDT

Use CONFIG_IS_ENABLED(WDT) to permit use of WDT in SPL without DM,
while the full U-Boot can use rich DM/DT WDT driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Suniel Mahesh <sunil.m@techveda.org>
5 years agoARM: display5: Remove U_BOOT_DEVICE definition of serial_mxc
Lukasz Majewski [Sun, 9 Jun 2019 20:54:44 +0000 (22:54 +0200)]
ARM: display5: Remove U_BOOT_DEVICE definition of serial_mxc

Before the wide DM/DTS adoption in the U-Boot proper, the display5
has been using only DM_SERIAL to provide serial console in
pre-relocation.

After moving to full DM/DTS adoption in the U-Boot proper the
U_BOOT_DEVICE definition is not needed anymore, as it has been
replaced with udevice creation from provided DTS description.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoDTS: Add imx6q-display5-u-boot.dtsi file with u-boot specific properties
Lukasz Majewski [Sun, 9 Jun 2019 20:54:43 +0000 (22:54 +0200)]
DTS: Add imx6q-display5-u-boot.dtsi file with u-boot specific properties

This file setups UART5 based serial to be used as pre-relocation
console in the U-Boot proper.

On purpose pinux configuration is omitted here as it has been already
done in SPL. For early pre-relocation code we only need the serial
device from DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoDTS: imx: Add display5 board (imx6q based) device tree description (v5.1)
Lukasz Majewski [Sun, 9 Jun 2019 20:54:42 +0000 (22:54 +0200)]
DTS: imx: Add display5 board (imx6q based) device tree description (v5.1)

This commit ports from Linux kernel - tag: v5.1 - the device tree
description for display5 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoARM: display5: Increase the pre-relocation malloc pool size to 4KiB
Lukasz Majewski [Sun, 9 Jun 2019 20:54:41 +0000 (22:54 +0200)]
ARM: display5: Increase the pre-relocation malloc pool size to 4KiB

Porting more DTS code from Linux kernel for display5 board required
increase of pre-relocation malloc pool size in U-Boot proper.

The early malloc memory is necessary for handling parsing and setup of
e.g. serial port device (and all its ancestors in DT tree).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
5 years agogpio: Add missing parenthesis to the GPIO_TO_PORT define
Lukasz Majewski [Sun, 9 Jun 2019 20:54:40 +0000 (22:54 +0200)]
gpio: Add missing parenthesis to the GPIO_TO_PORT define

Add missing parenthesis to the GPIO_TO_PORT macro.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoARM: display5: Fix CS check after moving some SPI related CONFIGs to Kconfig
Lukasz Majewski [Sun, 9 Jun 2019 20:54:39 +0000 (22:54 +0200)]
ARM: display5: Fix CS check after moving some SPI related CONFIGs to Kconfig

After commit 14453fbfadc2 ("Convert CONFIG_SF_DEFAULT_* to Kconfig")
and commit abe66b1b5dec ("Convert CONFIG_ENV_SPI_* to Kconfig") ,which
moved some SPI related CONFIG_* defines to Kconfig the display5 board has
become unbootable as the SPI CS check condition had wrong value.

This commit fixes this check and allows proper SPI NOR flash operation in
SPL.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agocosmetic: Update comment in cmd/eeprom.c
Lukasz Majewski [Sun, 9 Jun 2019 20:54:38 +0000 (22:54 +0200)]
cosmetic: Update comment in cmd/eeprom.c

This commit just corrects spelling of 'accessed' word in the EEPROM
comment.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agocosmetic: display5: Remove not needed comments
Lukasz Majewski [Sun, 9 Jun 2019 20:54:37 +0000 (22:54 +0200)]
cosmetic: display5: Remove not needed comments

Some comments are not needed anymore after Kconfig automated conversion.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoconfigs: icorem6: Enable Nand bcb command
Shyam Saini [Wed, 12 Jun 2019 08:43:16 +0000 (14:13 +0530)]
configs: icorem6: Enable Nand bcb command

This would be used for writing spl images along nand BCB

Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
5 years agoconfigs: icore: Fix U-Boot proper loading from nand
Shyam Saini [Mon, 3 Jun 2019 05:43:21 +0000 (11:13 +0530)]
configs: icore: Fix U-Boot proper loading from nand

SPL on Engicam i.Core M6 boards enabled DM, so it would require some
malloc() pool before relocation in order to load U-Boot proper properly.

So, enable SPL malloc() pool of 0x2000 size similarly like what we have
used for icore mmc defconfigs.

Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
5 years agopwm: imx: add DM_PWM support
Heiko Schocher [Tue, 28 May 2019 04:51:52 +0000 (06:51 +0200)]
pwm: imx: add DM_PWM support

add DM support for pwm-imx driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
5 years agopwm: imx: add Kconfig support
Heiko Schocher [Tue, 28 May 2019 04:51:51 +0000 (06:51 +0200)]
pwm: imx: add Kconfig support

add Kconfig support for this driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Martyn Welch <martyn.welch@collabora.co.uk>
5 years agoopos6uldev: remove board_ehci_hcd_init function
Sébastien Szymanski [Mon, 20 May 2019 09:43:16 +0000 (11:43 +0200)]
opos6uldev: remove board_ehci_hcd_init function

This function sets the polarity of the PWR signal which is not used on
the opos6uldev board. Remove it.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
5 years agodoc: Update parallel NOR flash related information in README.falcon
Lukasz Majewski [Thu, 16 May 2019 14:01:38 +0000 (16:01 +0200)]
doc: Update parallel NOR flash related information in README.falcon

This commit updates the doc/README.falcon regarding Falcon boot on
NOR flash memories.

This code is used by MCCMON6 board - so for more details please refer to
configs/mccmon6_nor_defconfig.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoKconfig: Add CMD_SPL_NOR_OFS config for falcon boot argument offset
Lukasz Majewski [Thu, 16 May 2019 14:01:37 +0000 (16:01 +0200)]
Kconfig: Add CMD_SPL_NOR_OFS config for falcon boot argument offset

This option will provide the offset in the parallel NOR flash memory to,
which the falcon boot data is stored.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoKconfig: cosmetic: Update description of CMD_SPL_NAND_OFS
Lukasz Majewski [Thu, 16 May 2019 14:01:36 +0000 (16:01 +0200)]
Kconfig: cosmetic: Update description of CMD_SPL_NAND_OFS

The CMD_SPL_NAND_OFS description was a bit misleading, has
been updated.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoKconfig: Make CMD_SPL_NAND_OFS only available when proper memory is used
Lukasz Majewski [Thu, 16 May 2019 14:01:35 +0000 (16:01 +0200)]
Kconfig: Make CMD_SPL_NAND_OFS only available when proper memory is used

This commit makes the CMD_SPL_NAND_OFS only visible when we use NAND
memory.
Before this change it was present when only CMD_SPL was enabled (and
would stay when board with other falcon boot medium is used).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoARM: imx: Disable 1Gbps support on MCCMON6's KSZ9031 PHY
Lukasz Majewski [Thu, 16 May 2019 07:41:44 +0000 (09:41 +0200)]
ARM: imx: Disable 1Gbps support on MCCMON6's KSZ9031 PHY

mccmon6 works in 10/100 MiB Ethernet environment, so disabling 1GiB support
improves robustness of the network after power up (as one don't need to
wait for autoneg).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoARM: imx: config: Disable support for USB on MCCMON6
Lukasz Majewski [Thu, 16 May 2019 07:41:43 +0000 (09:41 +0200)]
ARM: imx: config: Disable support for USB on MCCMON6

The IMX6Q based MCCMON6 is not using USB for any purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoARM: imx: cosmetic: Remove not needed comment from the mccmon6.h file
Lukasz Majewski [Thu, 16 May 2019 07:41:42 +0000 (09:41 +0200)]
ARM: imx: cosmetic: Remove not needed comment from the mccmon6.h file

This comment is a leftover from the Kconfig CONFIG_*MTD* move.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agomx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0
Ye Li [Wed, 15 May 2019 09:57:01 +0000 (09:57 +0000)]
mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0

On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer "mx7ulp_evk: Change APLL and its PFD0 frequencies"), we set DDR
clock to 352.8Mhz (25.2Mhz * 14) by using the clock path:

APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock

To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)

NIC0_DIV:      1
NIC1_DIV:      0
LCDIF_PCC_DIV: 6

APLL and APLL PFD0 settings:

PFD0 FRAC:  27
APLL MULT:  22
APLL NUM:   1
APLL DENOM: 20

This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agomx7ulp: Select the SCG1 APLL PFD as a system clock source
Ye Li [Wed, 15 May 2019 09:56:59 +0000 (09:56 +0000)]
mx7ulp: Select the SCG1 APLL PFD as a system clock source

Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
5 years agomx7ulp_evk: Change APLL and its PFD0 frequencies
Ye Li [Wed, 15 May 2019 09:56:56 +0000 (09:56 +0000)]
mx7ulp_evk: Change APLL and its PFD0 frequencies

To support HDMI display on EVK board, the LCDIF pix clock must be
25.2Mhz. Since the its PCC divider range is from 1-8, the max rate
of LCDIF PCC source clock is 201.6Mhz. This limits the source clock
must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs
are higher than this max rate.

The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source
is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK,
NIC1 and NIC1 bus.

Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz
(25.2 * 12), with settings:

PFD0 FRAC:  32
APLL MULT:  22
APLL NUM:   2
APLL DENOM: 5

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
5 years agomx7ulp_evk: Update LPDDR3 script
Ye Li [Wed, 15 May 2019 09:56:53 +0000 (09:56 +0000)]
mx7ulp_evk: Update LPDDR3 script

Update LPDDR3 script with the changes below:
  -Update the precharge command to CMD=01 at the DDR initialization phase
  -remove unimplemented registers
   Write data bit delay --refer to the DDR_TRIM bits in
   IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn

Test:
  One EVK board passes overnight stress test.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
5 years agomx7ulp: Fix APLL num and denom setting issue
Ye Li [Wed, 15 May 2019 09:56:51 +0000 (09:56 +0000)]
mx7ulp: Fix APLL num and denom setting issue

For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
the NUM should always be less than the DENOM. So our setting violates the rule.

Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
is 318.9888Mhz, which also meet the DDR requirement.
To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
5 years agowarp7: Specify a default CONFIG_OPTEE_LOAD_ADDR if non provided
Bryan O'Donoghue [Wed, 8 May 2019 18:14:48 +0000 (19:14 +0100)]
warp7: Specify a default CONFIG_OPTEE_LOAD_ADDR if non provided

If no CONFIG_OPTEE_LOAD_ADDR is provided i.e. you are not loading OPTEE
into memory in u-boot, then just set the non-existent CONFIG option to
zero, elsewise stringify(CONFIG_OPTEE_LOAD_ADDR) will return
"CONFIG_OPTEE_LOAD_ADDR" - which looks weird in the u-boot environment.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agowarp7: include: configs: Specify an fdtovaddr
Bryan O'Donoghue [Wed, 8 May 2019 18:14:47 +0000 (19:14 +0100)]
warp7: include: configs: Specify an fdtovaddr

In the Mbed Linux OS bootflow OP-TEE runs before u-boot and provides a DTB
overlay at 0x83100000.

This overlay should subsequently be merged into the main DTB before handing
over to the kernel.

This patch defines fdtovaddr at 0x83100000.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agowarp7_bl33: configs: Enable CONFIG_OF_LIBFDT_OVERLAY
Bryan O'Donoghue [Wed, 8 May 2019 18:14:46 +0000 (19:14 +0100)]
warp7_bl33: configs: Enable CONFIG_OF_LIBFDT_OVERLAY

This commit enables CONFIG_OF_LIBFDT_OVERLAY a requirement to perform a
merge of an OPTEE provided DTB overlay into our main kernel DTB image.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agowarp7_bl33: configs: Enable CONFIG_OF_LIBFDT
Bryan O'Donoghue [Wed, 8 May 2019 18:14:45 +0000 (19:14 +0100)]
warp7_bl33: configs: Enable CONFIG_OF_LIBFDT

In order to switch on DTB overlay support in WaRP7 BL33 we first need to
switch on LIBFDT support. Do that now.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agowarp7: include: configs: Differentiate bootscript address from loadaddr
Bryan O'Donoghue [Wed, 8 May 2019 18:14:44 +0000 (19:14 +0100)]
warp7: include: configs: Differentiate bootscript address from loadaddr

Reusing the loadaddr to load the boot script breaks some of the logic we
want to have around the bootscript/FIT load addresses. Making a dedicated
bootscript address allows us to differentiate the bootscript load address
from the Linux Kernel or OPTEE load address, thus ensuring that no matter
what the load sequence the bootscript and Kernel/OPTEE binary load
addresses do not conflict.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agowarp7: include: configs: Specify image name of bootscript in FIT
Bryan O'Donoghue [Wed, 8 May 2019 18:14:43 +0000 (19:14 +0100)]
warp7: include: configs: Specify image name of bootscript in FIT

When obtaining the bootscript from a FIT image we need to specify the name
of the bootscript as defined inside of the FIT.

This patch makes a define that appends a "bootscr" parameter to the source
command when compiling up in FIT mode on warp7.

An environment variable is supplied to enable others to use a different
name than "bootscr" as the image name of the boot script in their FIT.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agowarp7_bl33: configs: Enable FIT as the boot.scr format
Bryan O'Donoghue [Wed, 8 May 2019 18:14:42 +0000 (19:14 +0100)]
warp7_bl33: configs: Enable FIT as the boot.scr format

This patch switches on FIT verification of boot.scr. After this commit your
boot.scr must be in the FIT format.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agoregulator: bd718x7: support ROHM BD71837 and BD71847 PMICs
Matti Vaittinen [Tue, 7 May 2019 07:45:55 +0000 (10:45 +0300)]
regulator: bd718x7: support ROHM BD71837 and BD71847 PMICs

BD71837 and BD71847 is PMIC intended for powering single-core,
dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847
is used for example on NXP imx8mm EVK.

Add regulator driver for ROHM BD71837 and BD71847 PMICs.
BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced
version containing 6 bucks and 6 LDOs. Voltages for DVS
bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted
when regulators are enabled. For other bucks and LDOs we may
have over- or undershooting if voltage is adjusted when
regulator is enabled. Thus this is prevented by default.

BD718x7 has a quirk which may leave power output disabled
after reset if enable/disable state was controlled by SW.
Thus the SW control is only allowed for BD71837  bucks
3 and 4 by default. The impact of this limitation must be
evaluated board-by board and restrictions may need to be
modified. (Linux driver get's these limitations from DT and we
may want to implement same on u-Boot driver).

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoimx: imx8dx/qxp: enable thermal
Peng Fan [Sun, 5 May 2019 13:24:00 +0000 (13:24 +0000)]
imx: imx8dx/qxp: enable thermal

Add thermal dts node
Enable thermal in defconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>
5 years agothermal: add i.MX8 thermal driver
Peng Fan [Sun, 5 May 2019 13:23:54 +0000 (13:23 +0000)]
thermal: add i.MX8 thermal driver

Add i.MX8 thermal driver to support get temperature from SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
5 years agomisc: imx8: add sc_misc_get_temp
Peng Fan [Sun, 5 May 2019 13:23:51 +0000 (13:23 +0000)]
misc: imx8: add sc_misc_get_temp

Add sc_misc_get_temp to support get temperature

Signed-off-by: Peng Fan <peng.fan@nxp.com>
5 years agoMAINTAINERS: Update lib/optee with my details
Bryan O'Donoghue [Sat, 4 May 2019 00:08:26 +0000 (01:08 +0100)]
MAINTAINERS: Update lib/optee with my details

Commit 32ce6179fb99 ("optee: Add lib entries for sharing OPTEE code across
ports") adds code into lib/optee but neglects to update MAINTAINERS to make
me buggable for questions and maintenance.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
5 years agowarp7: configs: bl33: Tidy up OPTEE defines
Bryan O'Donoghue [Sat, 4 May 2019 00:08:25 +0000 (01:08 +0100)]
warp7: configs: bl33: Tidy up OPTEE defines

When booting in BL33 mode i.e. with u-boot loaded by OP-TEE we get the
following print-out.

Board: WARP7 in secure mode OPTEE DRAM 0xa0000000-0xa0000000

This is incorrect the right range is 0x9e000000-0xa0000000. This patch
fixes the defines on the warp7_bl33_defconfig file to tidy up the output.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
5 years agooptee: Make TZDRAM config options contingent on CONFIG_OPTEE
Bryan O'Donoghue [Sat, 4 May 2019 00:08:23 +0000 (01:08 +0100)]
optee: Make TZDRAM config options contingent on CONFIG_OPTEE

Commit c7b3a7ee5351 ("optee: adjust dependencies and default values for
dram") makes the TZDRAM defines for OPTEE show up for all configs as a
side-effect. While not harmful its not what we really want.

This patch makes the following defines contingent on CONFIG_OPTEE=y

CONFIG_OPTEE_TZDRAM_BASE
CONFIG_OPTEE_TZDRAM_SIZE

Rightly, if you don't have CONFIG_OPTEE=y you don't care about the above
two defines.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Rui Miguel Silva <rui.silva@linaro.org>
Acked-by: Rui Miguel Silva <rui.silva@linaro.org>
5 years agospi: mxs: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion)
Lukasz Majewski [Wed, 19 Jun 2019 15:31:07 +0000 (17:31 +0200)]
spi: mxs: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion)

This patch converts mxs_spi driver to support DM/DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agopinctrl: mxs: Add support for i.MX2[38] mxs pinctrl driver
Lukasz Majewski [Wed, 19 Jun 2019 15:31:06 +0000 (17:31 +0200)]
pinctrl: mxs: Add support for i.MX2[38] mxs pinctrl driver

The code responsible for setting proper values in the MUX registers
(in the mxs_pinctrl_set_state()) has been ported from Linux kernel
- SHA1: 17bb763e7eaf tag v5.1.11 from linux-stable.

As the pinctrl node in the imx28.dtsi file has gpio pins nodes as subnodes,
it was necessary to use 'dm_scan_fdt_dev()' (as a .bind method) to also
make them 'visible' by the DM's "gpio_mxs" driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agogpio: mxs: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO)
Lukasz Majewski [Wed, 19 Jun 2019 15:31:05 +0000 (17:31 +0200)]
gpio: mxs: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO)

This patch adds support for DM/DTS in the mxs_gpio.c driver.
Information regarding per gpio controller pin number is passed via DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agoARM: dts: imx: Provide 'gpio-ranges' for mxs_gpio driver
Lukasz Majewski [Wed, 19 Jun 2019 15:31:04 +0000 (17:31 +0200)]
ARM: dts: imx: Provide 'gpio-ranges' for mxs_gpio driver

Those properties are U-Boot specific as the mxs gpio Linux driver (up to
version v5.1.11) is not supporting them.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agonet: fec: Enable support for i.MX28 DM_ETH in the fec_mxc.c driver
Lukasz Majewski [Wed, 19 Jun 2019 15:31:03 +0000 (17:31 +0200)]
net: fec: Enable support for i.MX28 DM_ETH in the fec_mxc.c driver

The fec_mxc.c driver can be reused by i.MX28 when DM_ETH is enabled.
One only needs to add proper compatible and dependency on FEC_MXC in the
Kconfig.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agoARM: dts: imx: Copy imx28 device tree related files from Linux kernel (v5.1.11)
Lukasz Majewski [Wed, 19 Jun 2019 15:31:02 +0000 (17:31 +0200)]
ARM: dts: imx: Copy imx28 device tree related files from Linux kernel (v5.1.11)

This patch copies from the Linux kernel stable (tag v5.1.11)
SHA1: 17bb763e7eaf i.MX28 related device tree files.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agoARM: imx6q_logic: With SPL_OF_CONTROL enabled, remove MMC init
Adam Ford [Thu, 23 May 2019 19:11:32 +0000 (14:11 -0500)]
ARM: imx6q_logic: With SPL_OF_CONTROL enabled, remove MMC init

Since the board uses SPL_OF_CONTROL now, we don't need to
explicitly initialize the MMC driver, but we still need to
pinmux the corresponding pins.  This patch removes the
initialization code and leave just the muxing behind.

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agoARM: imx6q_logic: Enable SPL_DM with SPL_OF_CONTROL
Adam Ford [Thu, 23 May 2019 19:11:31 +0000 (14:11 -0500)]
ARM: imx6q_logic: Enable SPL_DM with SPL_OF_CONTROL

With the spl code correctly returning either MMC1 or MMC2,
this board can not boot either from internal eMMC (MMC1) or
the uSD card on the baseboard (MMC2) using the device tree.

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agospl: imx6: Let spl_boot_device return USDHC1 or USDHC2
Adam Ford [Thu, 23 May 2019 19:11:30 +0000 (14:11 -0500)]
spl: imx6: Let spl_boot_device return USDHC1 or USDHC2

Currently, when the spl_boot_device checks the boot device, it
will only return MMC1 when it's either sd or eMMC regardless
of whether or not it's MMC1 or MMC2.  This is a problem when
booting from MMC2 if MMC isn't being manually configured like in
the DM_SPL case with SPL_OF_CONTROL.

This patch will check the register and return either MMC1 or MMC2.

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agodoc: imx: Add documentation for nandbcb command
Shyam Saini [Fri, 14 Jun 2019 07:35:35 +0000 (13:05 +0530)]
doc: imx: Add documentation for nandbcb command

Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
5 years agoi.MX6: nand: add nandbcb command for imx
Shyam Saini [Fri, 14 Jun 2019 07:35:33 +0000 (13:05 +0530)]
i.MX6: nand: add nandbcb command for imx

Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.

It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.

It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.

So, cmd_nandbcb implemented in arch/arm/mach-imx

BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.

On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
  1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocks

for nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.

Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.

Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
5 years agoclk: Add MAINTAINERS entry for clocks (./drivers/clk/)
Lukasz Majewski [Mon, 24 Jun 2019 13:50:52 +0000 (15:50 +0200)]
clk: Add MAINTAINERS entry for clocks (./drivers/clk/)

The clock subsystem needs active maintenance as it steadily grows.
I do offer my help for this task.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agodefconfig: sandbox: Enable SANDBOX_CLK_CCF to reuse generic CCF code
Lukasz Majewski [Mon, 24 Jun 2019 13:50:51 +0000 (15:50 +0200)]
defconfig: sandbox: Enable SANDBOX_CLK_CCF to reuse generic CCF code

Enable by default the Common Clock Framework [CCF] clock code for sandbox.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoclk: sandbox: Add sandbox test code for Common Clock Framework [CCF]
Lukasz Majewski [Mon, 24 Jun 2019 13:50:50 +0000 (15:50 +0200)]
clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]

This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.

In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.

Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoclk: sandbox: Adjust clk-mux.c to emulate reading divider value from HW
Lukasz Majewski [Mon, 24 Jun 2019 13:50:49 +0000 (15:50 +0200)]
clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HW

The generic mux clock code for CCF requires reading the clock multiplexer
value from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the mux structure (accessible only when sandbox is run)
has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoclk: sandbox: Adjust clk-divider to emulate reading its value from HW
Lukasz Majewski [Mon, 24 Jun 2019 13:50:48 +0000 (15:50 +0200)]
clk: sandbox: Adjust clk-divider to emulate reading its value from HW

The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agodts: sandbox: Add 'osc' clock for Common Clock Framework [CCF] testing
Lukasz Majewski [Mon, 24 Jun 2019 13:50:47 +0000 (15:50 +0200)]
dts: sandbox: Add 'osc' clock for Common Clock Framework [CCF] testing

This patch adds the 'osc' fixed clock to facilitate the CCF testing in
the sandbox U-Boot. It is a starting point for building CCF hierarchy of
clocks.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agodm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flag
Lukasz Majewski [Mon, 24 Jun 2019 13:50:46 +0000 (15:50 +0200)]
dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flag

If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate()
provides recalculated clock value without considering the cache setting.

This may be necessary for some clocks tightly coupled with power domains
(i.e. imx8), and prevents from reading invalid cached values.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoclk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)
Lukasz Majewski [Mon, 24 Jun 2019 13:50:45 +0000 (15:50 +0200)]
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)

This patch brings the files from Linux kernel (linux-stable/linux-5.1.y
SHA1: 5752b50477da)to provide clocks support as it is used on the Linux
kernel with Common Clock Framework [CCF] setup.

The directory structure has been preserved. The ported code only supports
reading information from PLL, MUX, Divider, etc and enabling/disabling
the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic
to the alias numbering as the information about the clock is read from the
device tree.

One needs to pay attention to the comments indicating necessary for U-Boot's
driver model changes.

If needed, the code can be extended to support the "set" part of the clock
management.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agodm: clk: Define clk_get_by_id() for clk operations
Lukasz Majewski [Mon, 24 Jun 2019 13:50:44 +0000 (15:50 +0200)]
dm: clk: Define clk_get_by_id() for clk operations

This commit adds the clk_get_by_id() function, which is responsible
for getting the udevice with matching clk->id. Such approach allows
re-usage of inherit DM list relationship for the same class (UCLASS_CLK).
As a result - we don't need any other external list - it is just enough
to look for UCLASS_CLK related udevices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agodm: clk: Define clk_get_parent_rate() for clk operations
Lukasz Majewski [Mon, 24 Jun 2019 13:50:43 +0000 (15:50 +0200)]
dm: clk: Define clk_get_parent_rate() for clk operations

This commit adds the clk_get_parent_rate() function, which is responsible
for getting the rate of parent clock.
Unfortunately, u-boot's DM support for getting parent is different
(the parent relationship is in udevice) than the one in Common Clock
Framework [CCF] in Linux.

To alleviate this problem - the clk_get_parent_rate() function has been
introduced to clk-uclass.c.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agodm: clk: Define clk_get_parent() for clk operations
Lukasz Majewski [Mon, 24 Jun 2019 13:50:42 +0000 (15:50 +0200)]
dm: clk: Define clk_get_parent() for clk operations

This commit adds the clk_get_parent() function, which is responsible
for getting the parent's struct clock pointer.

U-Boot's DM support for getting parent is different (the parent
relationship is in udevice) than the one in Common Clock Framework [CCF]
in Linux. To obtain the pointer to struct clk of parent the
pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoclk: Introduce clk-provider.h to store Common Clock Framework's internals
Lukasz Majewski [Mon, 24 Jun 2019 13:50:41 +0000 (15:50 +0200)]
clk: Introduce clk-provider.h to store Common Clock Framework's internals

This file now stores the dev_get_clk_ptr() wrapper on the dev_get_uclass_priv()
function.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoclk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)
Lukasz Majewski [Mon, 24 Jun 2019 13:50:40 +0000 (15:50 +0200)]
clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c)

Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK
without declaring struct clk. As a result it was only accessible by
iterating the udevice's uclass list.

This is a problem for clock code, which operates on pointers to struct
clk (like clk_get_rate()), not udevices.

After this change struct clk is accessible from udevice and udevice from
struct clk.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoclk: Extend struct clk to provide clock type agnostic flags
Lukasz Majewski [Mon, 24 Jun 2019 13:50:39 +0000 (15:50 +0200)]
clk: Extend struct clk to provide clock type agnostic flags

This commit extends the struct clk to provide information regarding the
flags related to this devices.

Those flags are clk device agnostic and indicate generic features
(like e.g. CLK_GET_RATE_NOCACHE - the need to always recalculate the rate).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoclk: Extend struct clk to provide information regarding clock rate
Lukasz Majewski [Mon, 24 Jun 2019 13:50:38 +0000 (15:50 +0200)]
clk: Extend struct clk to provide information regarding clock rate

This commit extends the struct clk to provide information regarding the
clock rate.
As a result the clock tree traversal is performed at most once, and further
reads are using the cached value.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoclk: Remove clock ID check in .get_rate() of clk_fixed_*
Lukasz Majewski [Mon, 24 Jun 2019 13:50:37 +0000 (15:50 +0200)]
clk: Remove clock ID check in .get_rate() of clk_fixed_*

This check requires the struct clk passed to .get_rate() to be always
cleared out as any clock with valid ID causes -EINVAL return value.

The return code of fixed clocks shall always be returned.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agodm: Fix documentation entry as there is no UCLASS_CLOCK uclass
Lukasz Majewski [Mon, 24 Jun 2019 13:50:36 +0000 (15:50 +0200)]
dm: Fix documentation entry as there is no UCLASS_CLOCK uclass

There is no UCLASS_CLOCK uclass defined. Instead we do use the UCLASS_CLK.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
5 years agoclk: doc: Add documentation entry for Common Clock Framework [CCF] (i.MX)
Lukasz Majewski [Mon, 24 Jun 2019 13:50:35 +0000 (15:50 +0200)]
clk: doc: Add documentation entry for Common Clock Framework [CCF] (i.MX)

This patch describes the design decisions considerations and taken approach
for porting in a separate documentation entry.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoMerge branch '2019-07-17-master-imports'
Tom Rini [Thu, 18 Jul 2019 15:31:37 +0000 (11:31 -0400)]
Merge branch '2019-07-17-master-imports'

- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support.

5 years agoRevert "test: Disable pci_ep test for now"
Tom Rini [Wed, 17 Jul 2019 13:58:24 +0000 (09:58 -0400)]
Revert "test: Disable pci_ep test for now"

We now have a proper fix for this test, stop disabling it in CI.

This reverts commit ae8d23a668755d804748a1cf848426b28338b3d5.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agopci_ep: fix wrong addressing to barno
Ramon Fried [Mon, 15 Jul 2019 20:04:41 +0000 (23:04 +0300)]
pci_ep: fix wrong addressing to barno

barno was mistakely readed from the target structure,
resulting in undefined behavious depending on the previous memory
content. fix that.

Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver")
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
[trini: Drop unused bar_idx]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoboard: Arcturus: ucp1020: Removing obsoleted stuff
Oleksandr Zhadan [Thu, 11 Jul 2019 15:52:49 +0000 (11:52 -0400)]
board: Arcturus: ucp1020: Removing obsoleted stuff

Removed one of the defconfig(obsoleted) file
and unused CONFIG_MMC_SPI definition to avoid confusion
about if this board using non-DM stuff or not.
uCP1020 is completely DM free board, tested and runs well.

Signed-off-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoblk: Invalidate block cache when switching hwpart
Weijie Gao [Thu, 11 Jul 2019 07:10:23 +0000 (15:10 +0800)]
blk: Invalidate block cache when switching hwpart

Some storage devices have multiple hw partitions and both address from
zero, for example eMMC.
However currently block cache invalidation only applies to block
write/erase.
This can cause a problem that data of current hw partition is cached
before switching to another hw partition. And the following read
operation of the latter hw partition will get wrong data when reading
from the addresses that have been cached previously.

To solve this problem, invalidate block cache after a successful
select_hwpart operation.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agoarm: dts: MediaTek: remove tick-timer from mt7629.dtsi
Weijie Gao [Thu, 11 Jul 2019 06:26:26 +0000 (14:26 +0800)]
arm: dts: MediaTek: remove tick-timer from mt7629.dtsi

This patch removes tick-timer as all mt7629 boards should use arch timer.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agoconfigs: mt7629_rfb: use arm arch timer instead of mtk timer
Weijie Gao [Thu, 11 Jul 2019 06:26:25 +0000 (14:26 +0800)]
configs: mt7629_rfb: use arm arch timer instead of mtk timer

This patch changes mt7629_rfb to use ARM's generic arch timer instead of
MediaTek's soc timer.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agoarm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi
Weijie Gao [Thu, 11 Jul 2019 06:26:24 +0000 (14:26 +0800)]
arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi

The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.

This patch reverses these two clocks to solve this issue.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agochromium: Update docs to clone vboot_reference directly
Simon Glass [Wed, 10 Jul 2019 17:04:13 +0000 (11:04 -0600)]
chromium: Update docs to clone vboot_reference directly

We don't need a full checkout of Chrome OS to build U-Boot with
Chromium OS verified boot. Update the instructions accordingly and fix a
typo which joins the output directory and defconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoarm: mediatek: add missing arch timer configuration for MT7629
Weijie Gao [Wed, 10 Jul 2019 09:35:42 +0000 (17:35 +0800)]
arm: mediatek: add missing arch timer configuration for MT7629

This patch sets CNTVOFF of ARM CP15 timer to zero to make sure the virtual
counter is fully usable for linux kernel.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agopower-domain.h: Fix typo
Anatolij Gustschin [Wed, 10 Jul 2019 08:03:13 +0000 (10:03 +0200)]
power-domain.h: Fix typo

%s/ot/to/

Signed-off-by: Anatolij Gustschin <agust@denx.de>
5 years agoCVE-2019-13106: ext4: fix out-of-bounds memset
Paul Emge [Mon, 8 Jul 2019 23:37:07 +0000 (16:37 -0700)]
CVE-2019-13106: ext4: fix out-of-bounds memset

In ext4fs_read_file in ext4fs.c, a memset can overwrite the bounds of
the destination memory region. This patch adds a check to disallow
this.

Signed-off-by: Paul Emge <paulemge@forallsecure.com>
5 years agoext4: gracefully fail on divide-by-0
Paul Emge [Mon, 8 Jul 2019 23:37:06 +0000 (16:37 -0700)]
ext4: gracefully fail on divide-by-0

This patch checks for 0 in several ext4 headers and gracefully
fails instead of raising a divide-by-0 exception.

Signed-off-by: Paul Emge <paulemge@forallsecure.com>
5 years agoCVE-2019-13104: ext4: check for underflow in ext4fs_read_file
Paul Emge [Mon, 8 Jul 2019 23:37:05 +0000 (16:37 -0700)]
CVE-2019-13104: ext4: check for underflow in ext4fs_read_file

in ext4fs_read_file, it is possible for a broken/malicious file
system to cause a memcpy of a negative number of bytes, which
overflows all memory. This patch fixes the issue by checking for
a negative length.

Signed-off-by: Paul Emge <paulemge@forallsecure.com>
5 years agoCVE-2019-13105: ext4: fix double-free in ext4_cache_read
Paul Emge [Mon, 8 Jul 2019 23:37:04 +0000 (16:37 -0700)]
CVE-2019-13105: ext4: fix double-free in ext4_cache_read

ext_cache_read doesn't null cache->buf, after freeing, which results
in a later function double-freeing it. This patch fixes
ext_cache_read to call ext_cache_fini instead of free.

Signed-off-by: Paul Emge <paulemge@forallsecure.com>
5 years agoCVE-2019-13103: disk: stop infinite recursion in DOS Partitions
Paul Emge [Mon, 8 Jul 2019 23:37:03 +0000 (16:37 -0700)]
CVE-2019-13103: disk: stop infinite recursion in DOS Partitions

part_get_info_extended and print_partition_extended can recurse infinitely
while parsing a self-referential filesystem or one with a silly number of
extended partitions. This patch adds a limit to the number of recursive
partitions.

Signed-off-by: Paul Emge <paulemge@forallsecure.com>
5 years agoqemu-riscv: enable VIRTIO_PCI
David Abdurachmanov [Wed, 3 Jul 2019 12:50:44 +0000 (15:50 +0300)]
qemu-riscv: enable VIRTIO_PCI

libvirt v.5.3.0 with QEMU 4.0.0 or above uses PCI automatically and
thus devices (network, storage, etc) are connected via PCI.

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoarm: qemu: fix failure in flash initialization if booting from TF-A
AKASHI Takahiro [Wed, 3 Jul 2019 01:44:40 +0000 (10:44 +0900)]
arm: qemu: fix failure in flash initialization if booting from TF-A

If U-Boot is loaded and started from TF-A (you need to change
SYS_TEXT_BASE to 0x60000000), it will hang up at flash initialization.

If secure mode is off (default, or -machine virt,secure=off) at qemu,
it will provide dtb with two flash memory banks:
flash@0 {
bank-width = <0x4>;
reg = <0x0 0x0 0x0 0x4000000 0x0 0x4000000 0x0 0x4000000>;
compatible = "cfi-flash";
};
If secure mode is on, on the other hand, qemu provides dtb with 1 bank:
flash@0 {
bank-width = <0x4>;
reg = <0x0 0x4000000 0x0 0x4000000>;
compatible = "cfi-flash";
};

As a result, flash_init()/flash_get_size() will eventually fail.
With this patch applied, relevant CONFIG values are modified.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoarm: move CONFIG_TFABOOT to generic Kconfig
AKASHI Takahiro [Wed, 3 Jul 2019 01:44:39 +0000 (10:44 +0900)]
arm: move CONFIG_TFABOOT to generic Kconfig

Currently, CONFIG_TFABOOT is located in armv8/fsl-layerscape Kconfig,
but it will be also useful for other targets if some additional
configuration are necessary.
So move it to arch/arm/Kconfig.

Please note that CONFIG_TFABOOT still depends on
CONFIG_ARCH_SUPPORT_TFABOOT and so the menu won't come up
if any target doesn't need its own customization for TF-A boot.
This will maintain the compatibility.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Sriram Dash <sriram.dash@nxp.com>
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Peng Ma <peng.ma@nxp.com>
Cc: Yuantian Tang <andy.tang@nxp.com>
Cc: Pankit Garg <pankit.garg@nxp.com>
5 years agodoc: Move fastboot protocol doc to android dir
Sam Protsenko [Tue, 2 Jul 2019 18:14:57 +0000 (21:14 +0300)]
doc: Move fastboot protocol doc to android dir

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
5 years agocmd: mem: Add a command to fill the memory with random data
Jean-Jacques Hiblot [Tue, 2 Jul 2019 12:23:26 +0000 (14:23 +0200)]
cmd: mem: Add a command to fill the memory with random data

This command fills the memory with data produced by rand().

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
5 years agotools: mkenvimage: Always consider non-regular files
Andre Przywara [Sun, 30 Jun 2019 01:45:01 +0000 (02:45 +0100)]
tools: mkenvimage: Always consider non-regular files

At the moment mkenvimage has two separate read paths: One to read from
a potential pipe, while dynamically increasing the buffer size, and a
second one using mmap(2), using the input file's size. This is
problematic for two reasons:
- The "pipe" path will be chosen if the input filename is missing or
  "-".  Any named, but non-regular file will use the other path, which
  typically will cause mmap() to fail:
  $ mkenvimage -s 256 -o out <(echo "foo=bar")
- There is no reason to have *two* ways of reading a file, since the
  "pipe way" will always work, even for regular files.

Fix this (and simplify the code on the way) by always using the method
of dynamically resizing the buffer. The existing distinction between
the two cases will merely be used to use the open() syscall or not.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
5 years agotools: mkenvimage: Fix reading from slow pipe
Andre Przywara [Sun, 30 Jun 2019 01:45:00 +0000 (02:45 +0100)]
tools: mkenvimage: Fix reading from slow pipe

It is perfectly fine for the read(2) syscall to return with less than
the requested number of bytes read (short read, see the "RETURN VALUE"
section of the man page). This typically happens with slow input
(keyboard, network) or with complex pipes.

So far mkenvimage expects the exact number of requested bytes to be
read, assuming an end-of-file condition otherwise. This wrong behaviour
can be easily shown with:
$ (echo "foo=bar"; sleep 1; echo "bar=baz") | mkenvimage -s 256 -o out -
The second line will be missing from the output.

Correct this by checking for any positive, non-zero return value.

This fixes a problem with a complex pipe in one of my scripts, where
the environment consist of two parts.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Alexander Dahl <ada@thorsis.com>
5 years agotest/py: gpt: Use long options for sgdisk
Sam Protsenko [Tue, 2 Jul 2019 18:20:32 +0000 (21:20 +0300)]
test/py: gpt: Use long options for sgdisk

sgdisk 0.8.10.2 from AOSP doesn't support short options, failing with
errors like this:

    sgdisk: invalid option -- 'U'

Test fails due to that error. Let's use long options to make the test
work with any sgdisk version.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
5 years agoenv: mmc: add erase-function
Frank Wunderlich [Sat, 29 Jun 2019 09:36:20 +0000 (11:36 +0200)]
env: mmc: add erase-function

this adds erase environment for mmc storage

squashed fixes:
 - add CONFIG_CMD_ERASEENV
 - env: erase redundant offset if defined
 - changes mentioned by Simon
 - fix whitespaces around errmsg

Suggested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
5 years agoenv: register erase command
Frank Wunderlich [Sat, 29 Jun 2019 09:36:19 +0000 (11:36 +0200)]
env: register erase command

this patch adds basic changes for adding a erase-subcommand to env

with this command the environment stored on non-volatile storage written
by saveenv can be cleared.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
squashed fixes
 - start message with "Erasing"
 - mark erase-function as optional
 - env: separate eraseenv from saveenv

Suggested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
5 years agocommon: Fix autocompletion with CONFIG_CMDLINE_PS_SUPPORT
Marek Vasut [Wed, 26 Jun 2019 22:17:27 +0000 (00:17 +0200)]
common: Fix autocompletion with CONFIG_CMDLINE_PS_SUPPORT

The autocompletion did not work if CONFIG_CMDLINE_PS_SUPPORT was enabled
because U-Boot was comparing the prompt string with CONFIG_SYS_PROMPT .
While this works if CONFIG_CMDLINE_PS_SUPPORT is disabled, this no longer
works if it's enabled because user can override the PS1 . Fix this by
checking prompt string against the current PS1 value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
5 years agoregulator: Allow enabling GPIO regulator
Sven Schwermer [Mon, 24 Jun 2019 11:03:34 +0000 (13:03 +0200)]
regulator: Allow enabling GPIO regulator

Drivers need to be able to enable regulators that may be implemented as
GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is
commonly implemented as a GPIO regulator in order to switch between I/O
voltage levels.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
5 years agoregulator: Factor out common enable code
Sven Schwermer [Mon, 24 Jun 2019 11:03:33 +0000 (13:03 +0200)]
regulator: Factor out common enable code

In preparation of being able to enable/disable GPIO regulators, the
code that will be shared among the two kinds to regulators is factored
out into its own source files.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
5 years agoARM: correct detection of thumb mode
Heinrich Schuchardt [Sun, 23 Jun 2019 10:59:31 +0000 (12:59 +0200)]
ARM: correct detection of thumb mode

When a crash occurs in thumb mode the crash dump is incorrect. This is due
to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in
the definition of macro thumb_mode(regs).

Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been
compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt.

With the patch crash dumps indicate thumb mode correctly.

On a system with thumb mode:

=> exception unaligned
data abort
pc : [<8f7a2b52>]          lr : [<8f7ab1ef>]
reloc pc : [<1780cb52>]    lr : [<178151ef>]
sp : 8ed8c3f8  ip : 8f7a2b4d     fp : 00000002
r10: 8f7f8228  r9 : 8ed95ea8     r8 : 8ed99488
r7 : 8f7ab141  r6 : 00000000     r5 : 8ed8c3f9  r4 : 8f7f6390
r3 : 8ed9948c  r2 : 00000001     r1 : 00000000  r0 : 8f7f6390
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32 (T)
Code: 8f7e 466d f105 0501 (e9d5) 6700

The Flags line has '(T)' and in the Code line the output is in u16 groups.

On a system without thumb mode:

=> exception breakpoint
prefetch abort
pc : [<7ff5a5c8>]          lr : [<7ff675ec>]
reloc pc : [<0000e5c8>]    lr : [<0001b5ec>]
sp : 7ee0ad80  ip : 7ff5a5cc     fp : 7ff674cc
r10: 00000002  r9 : 7ef0bed8     r8 : 7ffd6214
r7 : 7ef0e080  r6 : 00000000     r5 : 7ffd4090  r4 : 00000000
r3 : 7ef0e084  r2 : 00000001     r1 : 00000000  r0 : 7ffd4090
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e)

The Flags line does not show '(T)' and in the Code line the output is in
u32 groups.

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agoext4: add support for filesystems without JOURNAL
Marek Szyprowski [Fri, 21 Jun 2019 13:35:35 +0000 (15:35 +0200)]
ext4: add support for filesystems without JOURNAL

JOURNAL is optional for EXT4 (and EXT3) filesystems, so add support for
skipping it. This fixes corrupting EXT4 volumes without JOURNAL after
using uboot's 'ext4write' command.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>