Kumar Gala [Tue, 1 Feb 2011 02:36:02 +0000 (20:36 -0600)]
powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Mon, 31 Jan 2011 21:51:20 +0000 (15:51 -0600)]
powerpc: Move cpu specific lmb reserve to arch_lmb_reserve
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Li Yang [Mon, 24 Jan 2011 17:09:52 +0000 (17:09 +0000)]
powerpc/85xx: Update P2020DS default env settings
Read MAC address from EEPROM. Add hwconfig settings.
Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.
Also cleanup some of the boot commands.
Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang [Mon, 24 Jan 2011 17:09:53 +0000 (17:09 +0000)]
powerpc/85xx: Add eSDHC support on P2020DS
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9
respectively).
We enable EXT2, FAT, and parition support for both MMC & USB configs.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 25 Jan 2011 05:36:17 +0000 (23:36 -0600)]
powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init
Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Fri, 21 Jan 2011 22:03:57 +0000 (16:03 -0600)]
p1022ds: allow for board-specific ngPIXIS functions
The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC
SOCs. Although programming the ngPIXIS is mostly standard on all boards that
have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in
"indirect" mode whenever the video display (DIU) is active.
To support indirect mode, and to make it easier to support other quirks on
future reference boards, the low-level ngPIXIS functions are all marked as
weak, so that board-specific code can override any of them. We take advantage
of this feature on the P1022DS, so that we can properly reset the board when
the DIU is active.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Dipen Dudhat [Thu, 20 Jan 2011 10:59:35 +0000 (16:29 +0530)]
powerpc/85xx: Add support for Integrated Flash Controller (IFC)
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.
Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
configurable
page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
availble at
boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
e.g. SRAM, ROM
- External clock is supported with programmable division
ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
on I/O bus
- 32 bit I/O: AD
- 16 bit I/O: AADD
- 8 bit I/O : AAAADDDD
- Configurable Even/Odd Parity on Address/Data bus
supported
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
If NCE is hooked up to NCS3, we don't need to (and can't)
explicitly set the state of the NCE pin. Instead, the
controller asserts it automatically as part of a
command/data access. Only "CE don't care"-type NAND chips
can be used in this manner.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
Florian Fainelli [Fri, 25 Feb 2011 00:01:34 +0000 (00:01 +0000)]
NAND: add support for reading ONFI page table
This patch adds support for reading an ONFI page parameter from a NAND
device supporting it. If this is the case, struct nand_chip onfi_version
member contains the supported ONFI version, 0 otherwise.
This allows NAND drivers past nand_scan_ident to set the best timings for the
NAND chip.
Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
Wolfgang Denk [Thu, 31 Mar 2011 21:26:29 +0000 (16:26 -0500)]
Fix build issues cause by LDFLAGS_FINAL changes
Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a
number of Makefiles in a way that broke out-of-tree builds. The
problem was that $(nandobj) was used before it got defined.
Fix this.
Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
Wolfgang Denk [Tue, 29 Mar 2011 12:34:50 +0000 (14:34 +0200)]
Fix build problems caused by "_end" -> "__bss_end__" rename
Commit 44c6e65 "rename _end to __bss_end__ broke building of a large
number of systems (at least all PowerPC?):
libstubs.o: In function `app_startup':
examples/standalone/stubs.c:197: undefined reference to `__bss_end__'
The rename should not be done for the files in the
examples/standalone/ directory, as these are not using the code from
start.S, but do their own BSS clearing, and either use their own
linker scripts or the ones provided by the compilers.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Martin Krause [Mon, 21 Mar 2011 17:07:56 +0000 (18:07 +0100)]
cfi_flash: fix bug with flash banks with different sector numbers
The function find_sector() does not take into account if the flash bank
has changed since the last call. This could lead to illegal accesses inside
and beyond the flash_info_t info strcture. For example if the current
flash bank has less sectors than the last used flash bank.
This patch adds two cheks. One that insures, that the current sector does
not exceed the allowed maximum (which is always a good idea). And one that
checks if the current access is to the same flash bank as the last access.
If not, the search loop will start with sector 0.
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chander Kashyap [Tue, 22 Mar 2011 01:40:50 +0000 (01:40 +0000)]
S5P: mmc: Resolved interrupt error during mmc_init
Blocksize was hardcoded to 512 bytes. But the blocksize varies
depeding on various mmc subsystem commands (between 8 and 512).
This hardcoding was resulting in interrupt error during data
transfer.
It is now calculated based upon the request sent by mmc subsystem.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Chander Kashyap [Tue, 22 Mar 2011 01:29:38 +0000 (01:29 +0000)]
ARMV7: S5P: Fixed register offset in mmc.h
The MMC registers are accessed through struct s5p_mmc member
variables. MMC controller "control4" register offset is set
to 0x8C as per data sheet. The size of struct s5p_mmc is also
corrected.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
Donghwa Lee [Mon, 7 Mar 2011 21:11:42 +0000 (21:11 +0000)]
ARM: S5P: pwm driver support
This is common pwm driver of S5P.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:13 +0000 (10:06 +0000)]
SMDK6400: Disable LED function in start.s on the nand booting
Since nand boot have some limit for the first 4KB, We only
disable the LED function to reduce the code space. At the
same time, Fix the compile error for LED function undefined
in the compile time of nand_spl.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:11 +0000 (10:06 +0000)]
SMDK6400: Fix the mutiple link error
The first, the cpu_init.o have already been link for cmd_link_o_target
atfer compile, But, The link script re-link the point file. So the link
machine will generate multiple definition error information.
The second, Since the first 4kB of nand boot featue code move to nand_spl,
So It is not necessary to force the cpu_init.o in non-nand boot.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:10 +0000 (10:06 +0000)]
SMDK6400: Fix some label undefined in build error
Modify Makefile for cpu_init.c and Start.s use some label,this defined
u-boot.lds of arch/arm/cpu/arm1176. But SMDK6400 use the link script
board/samsung/smdk6400/u-boot-nand.lds. So add some label form u-boot.lds
to u-boot-nand.lds
Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Po-Yu Chuang [Tue, 1 Mar 2011 23:02:04 +0000 (23:02 +0000)]
arm: fix incorrect monitor protection region in FLASH
Monitor protection region in FLASH did not cover .rel.dyn
and .dynsym sections, because it uses __bss_start to compute
monitor_flash_len. Use _end instead.
Add _end to linker scripts for end of u-boot image
Add _end_ofs to all the start.S.
powerpc/85xx: Fix PCI memory map setup on P1_P2_RDB
Update the PCIe address map to match standard FSL memory map.
Additionally, fix the TLBs so the cover the PCIe address space properly
so cards plugged in like an e1000 work correctly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --gc-sections to each uboot image.
To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace
PLATFORM_LDFLAGS in the Makefile of each nand_spl board.
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Peter Barada [Mon, 21 Mar 2011 23:05:20 +0000 (19:05 -0400)]
Fix hash table deletion to prevent lost entries
Use negative used value to mark deleted entry. Search keeps probing
past deleted entries. Adding an entry uses first deleted entry when
it hits end of probe chain.
Initially found that "ramdiskimage" and "preboot" collide modulus 347,
causing "preboot" to be inserted at idx 190, "ramdiskimage" at idx 191.
Previous to this fix when "preboot" is deleted, "ramdiskimage" is
orphaned.
Signed-off-by: Peter Barada <peter.barada@logicpd.com> Tested-by: Wolfgang Denk <wd@denx.de>
Heiko Schocher [Fri, 21 Jan 2011 06:23:35 +0000 (07:23 +0100)]
mpc52xx, digsy_mtc_rev5: Fix Linux crash, if no Flash in bank 2
If no Flash is connected to cs1, Linux crashes, because
reg entries are not correct adapted.
Following fix is needed:
- swap base addresses in CONFIG_SYS_FLASH_BANKS_LIST, as
flash bank 1 is on chipselect 0 and flash bank 2 on
chipselect 1
- call fdt_fixup_nor_flash_size() from ft_board_setup()
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <hs@denx.de>
cc: Werner Pfister <Pfister_Werner@intercontrol.de>
cc: Detlev Zundel <dzu@denx.de>
Stefan Roese [Mon, 14 Mar 2011 13:34:21 +0000 (14:34 +0100)]
UBI: Fix error code handling in ubi commands
Some ubi commands returned negative error codes, resulting in
the following error message on the prompt:
"exit not allowed from main input shell."
Negative error codes are not allowed.
This patch now changes the UBI code to return positive error codes.
Additionally "better" error codes are used, for example "ENOMEM" when
no memory is available for the UBI volume creation any more.
Also the output of some commands is enhanced:
Before:
=> ubi read 100000 testvol 100000
Volume testvol found at volume id 0
read 1048576 bytes from volume 0 to 100000(buf address)
=> ubi write 100000 testvol 1000
Volume testvol found at volume id 0
After:
=> ubi read 100000 testvol 100000
Read 1048576 bytes from volume testvol to 00100000
=> ubi write 100000 testvol 1000
4096 bytes written to volume testvol
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Kumar Gala [Sun, 13 Mar 2011 15:55:53 +0000 (10:55 -0500)]
powerpc/85xx: Fix synchronization of timebase on MP boot
There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0. We can simply just read back the value to
synchronizatize the write, before we set TB to 0.
Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
John Schmoller [Thu, 10 Mar 2011 22:09:26 +0000 (16:09 -0600)]
mpc8[5/6]xx: Ensure POST word does not get reset
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors. When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word. To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Timeout counter value is set as DTOCV bits in SYSCTL register
For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should
cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Wed, 19 Jan 2011 23:37:33 +0000 (15:37 -0800)]
corenet_ds: pick the middle value for all tested timing parameters
For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.
York Sun [Wed, 2 Mar 2011 22:24:11 +0000 (14:24 -0800)]
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Po-Yu Chuang [Tue, 15 Feb 2011 22:54:35 +0000 (22:54 +0000)]
arm: get_sp() should always be compiled
get_sp() was incorrectly excluded if none of
CONFIG_SETUP_MEMORY_TAGS
CONFIG_CMDLINE_TAG
CONFIG_INITRD_TAG
CONFIG_SERIAL_TAG
CONFIG_REVISION_TAG
were defined.
Lei Wen [Wed, 9 Feb 2011 12:47:47 +0000 (18:17 +0530)]
Pantheon: Add Board Support for Marvell dkb board
DKB is a Development Board for PANTHEON TD/TTC(pxa920/pxa910) with
* Processor upto 806Mhz
* LPDDR1/2
* x8/x16 SLC/MLC NAND
* Footprints for eMMC & MMC x8 card
With Peripherals:
* Parallel LCD I/F
* Audio codecs (88PM8607)
* MIPI CSI-2 camera
* Marvell 88W8787 802.11n/BT module
* Marvell 2G/3G RF
* Dual analog mics & speakers, headset jack, LED, ambient
* USB2.0 HS host, OTG (mini AB)
* GPIO, GPIO expander with DIP switches for easier selection
* UART serial over USB, CIR
This patch adds basic board support with DRAM and UART functionality
Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Lei Wen [Wed, 9 Feb 2011 12:36:58 +0000 (18:06 +0530)]
ARM: Add Support for Marvell Pantheon Familiy SoCs
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
Lei Wen [Wed, 9 Feb 2011 12:36:58 +0000 (18:06 +0530)]
mv: seperate kirkwood and armada from common setting
Since there are lots of difference between kirkwood and armada series,
it is better to seperate them but still keep the most common file
shared by all marvell platform in the mv-common configure file.
This patch move the kirkwood only driver definitoin in mv-common to
the <soc_name>/config.h.
This patch is tested with compilation for armada100 and guruplug.
Wolfgang Denk [Fri, 11 Feb 2011 12:25:48 +0000 (12:25 +0000)]
ARM: fix write*() I/O accessors
Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb
and friends." introduced I/O accessors with memory barriers.
Unfortunately the new write*() accessors introduced a bug:
The problem is that the argument "v" gets evaluated twice. This
breaks code like used here (from "drivers/net/dnet.c"):
for (i = 0; i < wrsz; i++)
writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
Use auxiliary variables to avoid such problems.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Alexander Holler <holler@ahsoftware.de> Cc: Dirk Behme <dirk.behme@googlemail.com>
Vitaly Kuzmichev [Fri, 11 Feb 2011 15:18:31 +0000 (18:18 +0300)]
USB-CDC: handle interrupt after dropped pullup
Disconnecting USB gadget with pending interrupt may cause its wrong
handling in the next time when interface will be started again
(especially actual for RNDIS). This interrupt may force the gadget
to queue unexpected response before setup stage.
Despite the fact that such interrupt handled after dropped pullup
also may add pending response, this will not bring to any issues due to
usb_ep_disable (which clears the queue) called on gadget unregistering.
Simon Glass [Wed, 16 Feb 2011 19:14:33 +0000 (11:14 -0800)]
Add USB host ethernet adapter support
This adds support for using USB Ethernet dongles in host mode. This is just
the framework - drivers will come later. A new config option called
CONFIG_USB_HOST_ETHER can be defined in board config files to switch this
on.
The was originally written by NVIDIA and was cleaned up for release by the
Chromium authors.
projects / u-boot.git / log