Teddy Reed [Fri, 10 Jun 2016 02:18:44 +0000 (19:18 -0700)]
verified-boot: Minimal support for booting U-Boot proper from SPL
This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.
The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256
In this example, SHA256 is the only selected hashing algorithm.
And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y
Signed-off-by: Teddy Reed <teddy.reed@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Sumit Garg <sumit.garg@nxp.com>
Andrew F. Davis [Wed, 8 Jun 2016 15:19:14 +0000 (10:19 -0500)]
ti_armv7_common: env: Remove no longer needed mem_reserve
The kernel can now use DT to reserve memory carveouts and
these areas are now the default for drivers that need reserved
memory, so reserving more here is unneeded and any memory reserved
this way will be wasted.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Keerthy [Tue, 7 Jun 2016 10:35:25 +0000 (16:05 +0530)]
arm: dra7xx: Assign omap_vcores based on board type
Currently omap_vcores which holds pmic data is being assigned based
on the SoC type. PMIC is not a part of SoC. It is logical to
to assign omap_vcores based on board type. Hence over ride the
vcores_init function and assign omap_vcores based on the board type.
Bin Meng [Wed, 8 Jun 2016 12:07:38 +0000 (05:07 -0700)]
x86: Probe pinctrl driver in cpu_init_r()
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:
- Pin's PADs only gets configured when GPIO driver is probed, which
is not done by default. This leaves the board in a partially
functional state as we must initialize PADs correctly to get
perepherals fully working.
- The probe routine of pinctrl driver is called multiple times, as
normally there are multiple GPIO controllers. It should really
be called just once.
Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com>
Bin Meng [Wed, 8 Jun 2016 12:07:35 +0000 (05:07 -0700)]
x86: baytrail: Configure card detect pin of the SD controller
As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD controller (bit 16 & bit 18 are always zero).
Add a configuration for this pin in the pinctrl node.
Note I've checked the PAD configuration for all the pins in all the
3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get
initialized to correct mode by FSP. With fsp,emmc-boot-mode set to
2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set
fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3
which is correct according to datasheet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 8 Jun 2016 12:07:34 +0000 (05:07 -0700)]
x86: baytrail: Change fsp, emmc-boot-mode to "auto"
At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
provides a config option fsp,emmc-boot-mode which tells FSP which
eMMC controller it initializes. Instead of hardcoded to 2, now
we change it to 1 which means "auto".
With this change, MinnowMax board (with a D0 stepping BayTrail SoC)
can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot
'pci' command.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
An accumulated length was incorrectly added to current each pass
through the loop. On system with more than 2 cores this caused a
corrupt MADT to be generated.
Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Yuan Yao [Wed, 8 Jun 2016 10:25:00 +0000 (18:25 +0800)]
armv8: ls2080aqds: Enable QSPI boot support
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Yuan Yao [Wed, 8 Jun 2016 10:24:59 +0000 (18:24 +0800)]
configs: ls2080aqds_nand_defconfig: Enable QSPI
The Freescale QSPI driver has been converted to Driver Model.
This patch enables FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Yuan Yao [Wed, 8 Jun 2016 10:24:54 +0000 (18:24 +0800)]
armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux. Enable I2C QIXIS access and I2C
early init to read the sysclk and ddrclk.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Yuan Yao [Wed, 8 Jun 2016 10:24:53 +0000 (18:24 +0800)]
configs: ls2080a_common: Remove duplicate NOR configs
The NOR flash related configure options appear in ls2080aqds.h and
ls2080ardb.h, and the two files both includ ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
board: ls2080a: Add "mcinitcmd" env for MC & DPL deployment
Environment variable mcinitcmd is defined to initiate MC and DPL
deployment from the location where it is stored (NOR, NAND, SD, SATA,
USB) during booting. If this variable is not defined then macro
MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will
not be applied during U-boot booting.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Yunhui Cui [Wed, 8 Jun 2016 02:31:42 +0000 (10:31 +0800)]
armv8/ls2080a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS2080A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80
Since the SRAM C corruption issue is now resolved on Allwinner
A64, it is possible to move the stack top to the address 0x1A000
on both A64 and A80. The boot ROM can load SPL binaries with
up to 32 KiB size on A64 (the 24 KiB SPL size limitation only
affects A10/A20), and this patch also ensures the availability
of 8 KiB stack.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently the AHB1 clock speed is configured as 200MHz by
the SPL, but this causes a subtle and hard to reproduce data
corruption in SRAM C (for example, this can't be easily
detected with a trivial memset/memcmp test).
For what it's worth, the Allwinner's BSP configures AHB1
as 200MHz, as can be verified by running the devmem2 tool
in the system running the Allwinner's kernel 3.10.x:
It is yet to be confirmed whether faster AHB1/AHB2 clock settings
can be used safely if we initialize the AXP803 PMIC instead of
using reset defaults. But in order to resolve the data corruption
problem right now, it's best to downclock AHB1 to a safe level.
Note that this issue only affects the SPL, which is not fully
supported on Allwinner A64 yet and it should not affect the boot0
usage (unless somebody can confirm SRAM C corruption with the
boot0 too).
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
spi: pic32_spi: add SPI master driver for PIC32 SoC.
This driver implements SPI protocol in master mode to communicate
with the SPI device connected on SPI bus. It handles /CS explicitly
by controlling respective pin as gpio ('cs-gpios' property in dt node)
and uses PIO mode for SPI transaction. It is configurable based
on driver-model only.
Cc: Jagan Teki <jteki@openedev.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Paul Burton [Thu, 9 Jun 2016 12:09:52 +0000 (13:09 +0100)]
MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex
For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: 372286217f05 ("MIPS: Split I & D cache line size config")
Paul Burton [Thu, 9 Jun 2016 12:09:51 +0000 (13:09 +0100)]
MIPS: Fix invalidate_dcache_range to operate on L1 Dcache
Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
Hans de Goede [Sun, 5 Jun 2016 14:53:04 +0000 (16:53 +0200)]
sunxi: musb: Properly turn of musb controller before booting
Turn of the clock and assert the reset when musb_stop gets called, so that
the os gets the musb controller in a pristine state. This fixes a spurious
VBus error interrupt triggering as soon as the Linux musb driver loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Thu, 2 Jun 2016 16:46:09 +0000 (18:46 +0200)]
sunxi: Enable ALDO3 and ALDO4 in Wobo_i5_defconfig
These are used for the usb wifi and if we leave the enabling up to the
kernel, we get hit by the axp209 issues with enabling ldo3 or 4 post boot
and the systems hangs as soon as it is enabled.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Heiko Schocher [Tue, 7 Jun 2016 06:55:45 +0000 (08:55 +0200)]
siemens,am33x: add draco etamin board
In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Move BOOTDELAY into defconfig, just always be 3 now] Signed-off-by: Tom Rini <trini@konsulko.com>
Heiko Schocher [Tue, 7 Jun 2016 06:55:44 +0000 (08:55 +0200)]
dfu, nand, ubi: fix erasing after write finish
writting to ubi nand partitions need after write ends an erase
of the remaining sectors. This fail, if dfu write size was not
a multiple of erasesize, example log:
Heiko Schocher [Tue, 7 Jun 2016 06:55:41 +0000 (08:55 +0200)]
nand: add nand mtd concat support
add for nand devices mtd concat support. Generic MTD concat
support is already ported to mainline, and used in the cfi_mtd
driver. This patch adds it similiar for nand devices.
Heiko Schocher [Tue, 7 Jun 2016 06:31:24 +0000 (08:31 +0200)]
doc, spl, am335x: update am335x-network
on the shc board we see when booting in net boot mode,
that the ROM bootloader sends "AM335x ROM" as
vendor-class-identifier. U-Boots doc says "DM814x ROM".
So, add the info to the doc, that there is also
"AM335x ROM" possible.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Heiko Schocher [Tue, 7 Jun 2016 06:31:18 +0000 (08:31 +0200)]
am335x: add some missing CM_CLKMODE_DPLL_SSC macros
add missing CM_CLKMODE_DPLL_SSC_ACK_MASK,
CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and
CM_CLKMODE_DPLL_SSC_TYPE_MASK
defines. Used for enabling spread spectrum.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Heiko Schocher [Tue, 7 Jun 2016 06:31:15 +0000 (08:31 +0200)]
tests: py: disable main_signon check for printenv cmd
if CONFIG_VERSION_VARIABLE is set, the U-Boot environment
contains a "vers" variable with the current U-Boot version
string. If now "printenv" is called, test/py fails as it
detects the main_sign string, which is in this case correct.
So check only the main_sign as an error, if CONFIG_VERSION_VARIABLE
is not set.
Simon Glass [Thu, 9 Jun 2016 02:55:15 +0000 (20:55 -0600)]
tiny-printf: Correct the snprintf() implementation
This current code passes the variable arguments list to sprintf(). This is
not correct. Fix it by calling _vprintf() directly.
This makes firefly-rk3288 boot again.
Fixes: abeb272 ("tiny-printf: Support snprintf()") Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Wed, 8 Jun 2016 09:02:32 +0000 (18:02 +0900)]
ARM: uniphier: insert dsb barrier to ensure visibility of store
I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.
The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.
Masahiro Yamada [Tue, 7 Jun 2016 12:03:44 +0000 (21:03 +0900)]
ARM: uniphier: do not overwrite fdt_file environment
This code auto-detects the best-match FDT file name, but it should
respect the user's choice if "fdt_file" environment is found in a
saved set of environments.
Masahiro Yamada [Sat, 4 Jun 2016 13:39:08 +0000 (22:39 +0900)]
ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20
The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
from an eMMC device. They are useful to reduce the memory footprint
of SPL, rather than compiling the whole MMC framework.
Kimmo Surakka [Tue, 24 May 2016 13:56:23 +0000 (15:56 +0200)]
board: ge: bx50v3: add missing partnum variable
Add missing ${partnum} to set rootdev correctly when
booting from USB or MMC.
Signed-off-by: Kimmo Surakka <kimmo.surakka@ge.com>
[Rebased against v2016.05 and adjusted the variable name] Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>
Andrew Shadura [Tue, 24 May 2016 13:56:18 +0000 (15:56 +0200)]
board: ge: bx50v3: make CONFIG_VIDEO optional and disabled by default
The kernel already knows how to initialise the display, and initialising
the display from U-boot is only useful for debugging and isn't necessary
in production, so no need to have it enabled in U-boot by default.
Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>
Andre Przywara [Tue, 31 May 2016 17:45:06 +0000 (10:45 -0700)]
arm/arm64: implement a boot header capability
Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.
Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
.space 1000
.word 0x12345678
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Steve Rae <srae@broadcom.com>
Commit Notes:
Please note that the current code:
start.S (arm64) and
vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).
For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.
[1] https://github.com/apritzel/pine64/tree/master/tools
END Reviewed-by: Tom Rini <trini@konsulko.com>
Chris Packham [Tue, 31 May 2016 08:30:59 +0000 (20:30 +1200)]
lib: make strmhz available in SPL
When setting up a DDR controller it is useful to be able to display
frequencies in a readable form. Make the strmhz() function available in
SPL builds provided there is full vsprintf available.
Reviewed-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com>
Alexander Graf [Fri, 27 May 2016 10:25:03 +0000 (12:25 +0200)]
efi_loader: Don't allocate from memory holes
When a payload calls our memory allocator with the exact address hint, we
happily allocate memory from completely unpopulated regions. Payloads however
expect this to only succeed if they would be allocating from free conventional
memory.
This patch makes the logic behind those checks a bit more obvious and ensures
that we always allocate from known good free conventional memory regions if we
want to allocate ram.
Reported-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 2 Jun 2016 09:38:27 +0000 (11:38 +0200)]
efi_loader: Move to normal debug infrastructure
We introduced special "DEBUG_EFI" defines when the efi loader
support was new. After giving it a bit of thought, turns out
we really didn't have to - the normal #define DEBUG infrastructure
works well enough for efi loader as well.
So this patch switches to the common debug() and #define DEBUG
way of printing debug information.
Alexander Graf [Fri, 20 May 2016 21:28:23 +0000 (23:28 +0200)]
efi_loader: Add exit support
Some times you may want to exit an EFI payload again, for example
to default boot into a PXE installation and decide that you would
rather want to boot from the local disk instead.
This patch adds exit functionality to the EFI implementation, allowing
EFI payloads to exit.
Alexander Graf [Fri, 20 May 2016 21:28:22 +0000 (23:28 +0200)]
arm: Introduce setjmp/longjmp
To quit an EFI application we will need logic to jump to the caller
of a function without returning from the function we called into,
so we need setjmp/longjmp functionality.
This patch introduces a trivial implementation of these that I
verified works on armv7, thumb2 and aarch64.
Ed Swarthout [Wed, 1 Jun 2016 13:11:24 +0000 (08:11 -0500)]
dm: scsi: if_typename should be scsi
Fixes:
=> ext2ls scsi 0:1
** Bad device scsi 0:1 **
for boards which use the scsi legacy driver (such as ls1043ardb).
Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Tested-by: George McCollister <george.mccollister@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 22 Apr 2016 12:28:54 +0000 (14:28 +0200)]
ARM64: zynqmp: Add support for standard distro boot commands
Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.
Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 1 Jun 2016 20:41:54 +0000 (22:41 +0200)]
ARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP
When the CONFIG_BOOTP_SERVERIP option is set, we ignore all
dhcp values for the tftp server and use our own serverip and
file name instead.
This is usually not what we want and I doubt it's set for a
good reason on ZynqMP. It definitely hurts if we want to support
uEFI PXE boot on it. So just remove the option for now.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / u-boot.git / log