Johan Jonker [Wed, 18 Oct 2023 14:01:59 +0000 (16:01 +0200)]
rockchip: test: dm: add rkmtd test
Add Rockchip rkmtd test:
Create/attach/detach RKMTD device.
Send/read data with Rockchip boot block header.
Test that reusing the same label should work.
Basic test of 'rkmtd' commands.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Wed, 18 Oct 2023 14:01:40 +0000 (16:01 +0200)]
rockchip: cmd: add rkmtd command
The command rkmtd creates a virtual block device to transfer
Rockchip boot block data to and from NAND with block orientated
tools like "ums" and "rockusb".
It uses the Rockchip MTD driver to scan for boot blocks and copies
data from the first block in a GPT formated virtual disk.
Data must be written in U-boot "idbloader.img" format and start at
partition "loader1" offset 64. The data header is parsed
for length and offset. When the last sector is received
it erases up to 5 erase blocks on NAND and writes bootblocks
in a pattern depending on the NAND ID. Data is then verified.
When a block turns out bad the block header is discarded.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Wed, 18 Oct 2023 14:00:56 +0000 (16:00 +0200)]
rockchip: block: add rkmtd class and drivers
Add rkmtd class and drivers to create a virtual block device
to transfer Rockchip boot block data to and from NAND with
block orientated tools like "ums" and "rockusb".
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
On Rockchip SoCs the first boot stages are written on NAND
with help of manufacturer software that uses a different format
then the MTD framework. Skip the automatic BBT scan with the
NAND_SKIP_BBTSCAN option to be able to pass the driver probe
function and to let the original data unchanged.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 21:40:22 +0000 (21:40 +0000)]
board: rockchip: Add Xunlong Orange Pi 5 Plus
Xunlong Orange Pi 5 Plus is a single-board computer based on the
Rockchip RK3588 SoC. The board provides abundant interfaces, including
two HDMI output ports, one HDMI input port, two 2.5G Ethernet ports,
M.2 M-Key slot, M.2 E-Key slot, two USB 3.0, two USB 2.0, and two Type-C.
Features tested on a Orange Pi 5 Plus 4GB v1.2:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet
Device tree is imported from linux v6.7-rockchip-dts64-1 tag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 21:40:21 +0000 (21:40 +0000)]
board: rockchip: Add Xunlong Orange Pi 5
Xunlong Orange Pi 5 is a single-board computer based on the Rockchip
RK3588S SoC. The board provides abundant interfaces, HDMI output, GPIO
interface, M.2 PCIe2.0, Type-C, Gigabit LAN port, 2*USB2.0, 1*USB3.0,
etc.
Features tested on a Orange Pi 5 4GB v1.2:
- SD-card boot
- SPI Flash boot
- PCIe/NVMe
- USB 2.0 host
- Ethernet
Device tree is imported from linux v6.7-rockchip-dts64-1 tag.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 17:02:11 +0000 (17:02 +0000)]
rockchip: rk3588-rock-5b: Sync USB3 nodes from mainline linux patches
The device tree for rk3588 and rock-5b contain usb3 nodes that have
deviated too much from current state of submitted mainline linux usb3
patches, see [1].
Sync usb3 related nodes from latest patches and collaboras rk3588 tree
so that dwc3-generic driver can be updated to include support for the
rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3
compatible until final node is merged in linux maintainer tree.
Jonas Karlman [Tue, 17 Oct 2023 17:02:10 +0000 (17:02 +0000)]
rockchip: rk3588-rock-5b: Enable support for PCIe SATA cards
Enable support for PCIe SATA cards and the on-board SATA controller.
This also revert use of CONFIG_PCI_INIT_R in order to speed up boot from
eMMC or SD-cards. Standard boot will initialize pci after faster boot
media have been enumerated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Tested-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 17 Oct 2023 17:02:08 +0000 (17:02 +0000)]
rockchip: rk3588: Sync device tree from v6.7-rockchip-dts64-1 tag
Sync rk3588 device tree from v6.7-rockchip-dts64-1 tag.
Adds PCIe, button and led nodes to rk3588-evb1-v10 and rk3588-rock-5b
boards. Also remove includes from u-boot.dtsi-files that is no longer
needed.
Linux commits: 42145b7a8235 ("arm64: dts: rockchip: add PCIe network controller to rock-5b") 199cbd5f195a ("arm64: dts: rockchip: add PCIe for M.2 M-key to rock-5b") da447ec38780 ("arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b") 86a2024d95e2 ("arm64: dts: rockchip: add PCIe2 network controller to rk3588-evb1") 46bb398ea1d8 ("arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1") 1c9a53ff7ece ("arm64: dts: rockchip: Add sdio node to rock-5b") 3eaf2abd11aa ("arm64: dts: rockchip: Add sfc node to rk3588s") bf012368bb0a ("arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s") 3d77a3e51b0f ("arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s") 0002c377e862 ("arm64: dts: rockchip: Remove duplicate regulator vcc3v3_wf from rock-5b") a6169ab36923 ("arm64: dts: rockchip: Enable UART6 on rock-5b") dd6dc0c4c126 ("arm64: dts: rockchip: Add AV1 decoder node to rk3588s") afa933c208e5 ("arm64: dts: rockchip: add ADC buttons to rk3588-evb1") 7952cbbda301 ("arm64: dts: rockchip: add status LED to rock-5b")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Thu, 12 Oct 2023 10:18:28 +0000 (18:18 +0800)]
clk: rockchip: rk3588: fix up the frac pll calculation
rk3588 frac pll:
FFVCO = ((m + k / 65536) * FFIN) / p
FFOUT = ((m + k / 65536) * FFIN) / (p * 2s)
k is the original code, but the K[15:0] is complement code
(6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111),
need to be converted.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Paul Barker [Thu, 19 Oct 2023 14:30:44 +0000 (15:30 +0100)]
serial: sh: Add RZ/G2L SCIF support
Extend the existing driver to support the SCIF serial ports on the
Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that if
there is a reset signal defined in the device tree, it is de-asserted
before we try to talk to the SCIF module.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
Paul Barker [Thu, 19 Oct 2023 14:30:43 +0000 (15:30 +0100)]
serial: sh: Fix error handling
The current SCIF error handling is broken for the RZ/G2L. After a break
condition has been triggered, the current code is unable to clear the
error and serial port output never resumes.
The RZ/G2L datasheet says that most error conditions are cleared by
resetting the relevant error bits in the FSR & LSR registers to zero.
To clear framing errors on SCIF ports, the invalid data also needs to be
read out of the receive FIFO.
After reviewing datasheets for RZ/G2{H,M,N,E}, R-Car Gen4, R-Car Gen3
and even SH7751 SoCs, it's clear that this is the way to clear errors
for all of these SoCs.
While we're here, annotate the handle_error() function with a couple of
comments as the reads and writes themselves don't immediately make it
clear what we're doing.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Tested-by: Chris Paterson <chris.paterson2@renesas.com> # HiHope RZ/G2M board Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # R-Car H3 Salvator-XS
This patch adds ISA string to the -march to generate zbb instructions
for U-Boot binaries, along with optimized string functions introduced
from Linux kernel.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Randolph [Thu, 12 Oct 2023 06:35:09 +0000 (14:35 +0800)]
riscv: spl: andes: Move the DTB in front of kernel
Originally, u-boot SPL will place the DTB directly after the kernel,
but the size of the kernel does not include the BSS section, This
means that u-boot SPL places the DTB in the kernel BSS section causing
the DTB to be cleared by the kernel BSS initialisation.
Moving the DTB in front of the kernel can avoid this error.
Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Randolph [Thu, 12 Oct 2023 06:35:07 +0000 (14:35 +0800)]
spl: riscv: add os type for next booting stage
If SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled, the function
spl_invoke_opensbi should change the target OS type to IH_OS_LINUX.
OpenSBI will load the Linux image as the next boot stage.
The os_takes_devicetree function returns a value of true or false
depending on whether or not SPL_LOAD_FIT_OPENSBI_OS_BOOT is enabled.
Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Randolph [Thu, 12 Oct 2023 06:35:05 +0000 (14:35 +0800)]
riscv: dts: binman: add condition for opensbi os boot
Add condition for OpenSBI OS boot mode, by default it is not enabled.
By default, binman creates the output file u-boot.itb.
If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created
after compilation instead of the default u-boot.itb.
Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Randolph [Thu, 12 Oct 2023 06:35:04 +0000 (14:35 +0800)]
riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol
Introduce common Kconfig symbol for riscv architecture.
This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM,
the Falcon boot is a shortcut boot method for SD/eMMC targets. It
skips the loading the RAM version U-Boot. Instead, it will loads
the FIT image and boots directly to Linux.
When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after
compilation instead of the default u-boot.itb. It initialises memory
with the U-Boot SPL at the first stage, just as a normal boot process
does at the beginning. Instead of jumping to the U-Boot proper from
OpenSBI before booting the Linux kernel, the RISC-V falcon mode
process jumps directly to the Linux kernel to gain shorter booting time.
Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Mayuresh Chitale [Wed, 11 Oct 2023 15:30:20 +0000 (21:00 +0530)]
riscv: binman: Fix compilation error
Some platforms may not have any DDR memory below 4G and for such platforms
the TEXT_BASE and LOAD addresses etc are all 64 bit addresses due to
which the u-boot build fails with below error:
u-boot/arch/riscv/dts/binman.dtsi:30.14-25
Value out of range for 32-bit array element
u-boot/arch/riscv/dts/binman.dtsi:43.14-25
Value out of range for 32-bit array element
u-boot/arch/riscv/dts/binman.dtsi:44.15-26
Value out of range for 32-bit array element
FATAL ERROR: Syntax error parsing input tree
Fix by setting the address-cells property to 2 and converting load
addresses to 64 bit values.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 1fc45d6483d ("watchdog: add pulse support to gpio watchdog driver") Reviewed-by: Stefan Roese <sr@denx.de>
To quote the author:
This series adds some tests for various SPL load methods, with the
intent of helping debug v6 of [1]. With that in mind, notable omissions
include NAND and ROMAPI, which both lack sandbox implementations, and
OS_BOOT, which I have deferred due to its complexity. Semihosting is
also omitted, but I think we can test that with qemu.
In order to test all of these methods, we must first generate suitable
images, possibly on filesystems. While other tests have historically
generated these images using external tools (e.g. mkimage, mkfs, etc.),
I have chosen to generate them on the fly. This is for a few reasons:
- By removing external dependencies on pytest to create certain files,
the tests become self-contained. This makes them easier to iterate on
and debug.
- By generating tests at runtime, we can dynamically vary the content.
This helps detect test failures, as even if tests are loaded to the
same location, the expected content will be different.
- We are not testing the image parsers themselves (e.g.
spl_load_simple_fit or fs_read) but rather the load methods (e.g.
spl_mmc_load_image). It is unnecessary to exercise full functionality
or generate 100% correct images.
- By reducing functionality to only what is necessary, the complexity of
various formats can often be greatly reduced.
This series depends on [2-3], which are small fixes identified through
this patch set. The organization of patches in this series is as
follows:
- General fixes for bugs which are unlikely to be triggered outside of
this series
- Changes to IMX8 container images to facilitate testing
- General prep. work, particularly regarding linker issues
- The tests themselves
Sean Anderson [Sat, 14 Oct 2023 20:48:05 +0000 (16:48 -0400)]
test: spl: Add a test for the SPI load method
Add test for the SPI load method. This one is pretty straightforward. We
can't enable FIT_EXTERNAL with LOAD_FIT_FULL because spl_spi_load_image
doesn't know the total image size and has to guess from fdt_totalsize. This
doesn't include external data, so loading it will fail.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:48:04 +0000 (16:48 -0400)]
test: spl: Add a test for the NOR load method
Add a test for the NOR load method. Since NOR is memory-mapped we can
substitute a buffer instead. The only major complication is testing LZMA
decompression. It's too complex to implement LZMA compression in a test, and we
have no in-tree compressor, so we just include some pre-compressed data. This
data was generated through something like
Sean Anderson [Sat, 14 Oct 2023 20:48:03 +0000 (16:48 -0400)]
test: spl: Add a test for the NET load method
Add a test for loading U-Boot over TFTP. As with other sandbox net
routines, we need to initialize our packets manually since things like
net_set_ether and net_set_udp_header always use "our" addresses. We use
BOOTP instead of DHCP, since DHCP has a tag/length-based format which is
harder to parse. Our TFTP implementation doesn't define as many constants
as I'd like, so I create some here. Note that the TFTP block size is
one-based, but offsets are zero-based.
In order to avoid address errors, we need to set up/define some additional
address information settings. dram_init_banksize would be a good candidate
for settig up bi_dram, but it gets called too late in board_init_r.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:48:02 +0000 (16:48 -0400)]
test: spl: Add a test for the MMC load method
Add a test for the MMC load method. This shows the general shape of tests
to come: The main test function calls do_spl_test_load with an appropriate
callback to write the image to the medium.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:48:01 +0000 (16:48 -0400)]
test: spl: Add a test for spl_blk_load_image
Add a test for spl_blk_load_image, currently used only by NVMe. Because
there is no sandbox NVMe driver, just use MMC instead. Avoid falling back
to raw images to make failures more obvious.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:48:00 +0000 (16:48 -0400)]
test: spl: Add functions to create filesystems
Add some functions for creating fat/ext2 filesystems with a single file and
a test for them. Filesystems require block devices, and it is easiest to
just use MMC for this. To get an MMC, we must also pull in the test device
tree. SPL_TIMER is necessary for SPL_MMC, perhaps because it uses a timeout.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:59 +0000 (16:47 -0400)]
test: spl: Add functions to create images
This add some basic functions to create images, and a test for said
functions. This is not intended to be a test of the image parsing
functions, but rather a framework for creating minimal images for testing
load methods. That said, it does do an OK job at finding bugs in the image
parsing directly.
Since we have two methods for loading/parsing FIT images, add LOAD_FIT_FULL
as a separate CI run.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:58 +0000 (16:47 -0400)]
test: spl: Fix spl_test_load not failing if fname doesn't exist
Returning a negative value from a unit test doesn't automatically fail the
test. We have to fail an assertion. Modify the test to do so.
This now causes the test to count as a failure on VPL. This is because the
fname of SPL (and U-Boot) is generated with make_exec in os_jump_to_image.
The original name of SPL is gone, and we can't determine the name of U-Boot
from the generated name.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:57 +0000 (16:47 -0400)]
test: spl: Split tests up and use some configs
In order to make adding new spl unit tests easier, especially when they may
have many dependencies, add some Kconfigs for the existing image test.
Split it into the parts which are generic (such as callbacks) and the
test-specific parts.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:55 +0000 (16:47 -0400)]
spl: Use map_sysmem where appropriate
All "physical" addresses in SPL must be converted to virtual addresses
before access in order for sandbox to work. Add some calls to map_sysmem in
appropriate places. We do not generally call unmap_sysmem, since we need
the image memory to still be mapped when we jump to the image. This doesn't
matter at the moment since unmap_sysmem is a no-op.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:54 +0000 (16:47 -0400)]
spl: Add callbacks to invalidate cached devices
Several SPL functions try to avoid performing initialization twice by
caching devices. This is fine for regular boot, but does not work with
UNIT_TEST, since all devices are torn down after each test. Add some
functions to invalidate the caches which can be called before testing these
load methods.
Sean Anderson [Sat, 14 Oct 2023 20:47:53 +0000 (16:47 -0400)]
net: bootp: Fall back to BOOTP from DHCP when unit testing
If we sent a DHCP packet and get a BOOTP response from the server, we
shouldn't try to send a DHCPREQUEST packet, since it won't be DHCPACKed.
Transition straight to BIND. This is only enabled for UNIT_TEST to avoid
bloat, since I suspect the number of BOOTP servers in the wild is
vanishingly small.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:51 +0000 (16:47 -0400)]
net: Fix compiling SPL when fastboot is enabled
When fastboot is enabled in U-Boot proper and SPL_NET is enabled, we will
try to (unsuccessfully) reference it in SPL. Fix these linker errors by
conditioning on SPL_UDP/TCP_FUNCTION_FASTBOOT.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Sean Anderson [Sat, 14 Oct 2023 20:47:50 +0000 (16:47 -0400)]
fs: ext4: Add some defines for testing
Add various defines which are not necessary for reading/writing
filesystems, but which are useful for creating them. These mostly come from
Linux v6.5-rc2 (what I had checked out).
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:46 +0000 (16:47 -0400)]
spl: Allow enabling SPL_OF_REAL and SPL_OF_PLATDATA at the same time
Sandbox unit tests in U-Boot proper load a test device tree to have some
devices to work with. In order to do the same in SPL, we must enable
SPL_OF_REAL. However, we already have SPL_OF_PLATDATA enabled. When
generating platdata from a devicetree, it is expected that we will not need
devicetree access functions (even though SPL_OF_CONTROL is enabled). This
expectation does not hold for sandbox, so allow user control of
SPL_OF_REAL.
There are several places in the tree where conditions involving OF_PLATDATA
or OF_REAL no longer function correctly when both of these options can be
selected at the same time. Adjust these conditions accordingly.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 14 Oct 2023 20:47:44 +0000 (16:47 -0400)]
arm: imx: Check header before calling spl_load_imx_container
Make sure we have an IMX header before calling spl_load_imx_container,
since if we don't it will fail with -ENOENT. This allows us to fall back to
legacy/raw images if they are also enabled.
This is a functional change, one which likely should have been in place
from the start, but a functional change nonetheless. Previously, all
non-IMX8 images (except FITs without FIT_FULL) would be optimized out if
the only image load method enabled supported IMX8 images. With this change,
support for other image types now has an effect.
There are seven boards with SPL_LOAD_IMX_CONTAINER enabled: three with
SPL_BOOTROM_SUPPORT:
imx93_11x11_evk_ld imx93_11x11_evk imx8ulp_evk
and four with SPL_MMC:
deneb imx8qxp_mek giedi imx8qm_mek
All of these boards also have SPL_RAW_IMAGE_SUPPORT and
SPL_LEGACY_IMAGE_FORMAT enabled as well. However, none have FIT support
enabled. Of the six load methods affected by this patch, only SPL_MMC and
SPL_BOOTROM_SUPPORT are enabled with SPL_LOAD_IMX_CONTAINER.
spl_romapi_load_image_seekable does not support legacy or raw images, so
there is no growth. However, mmc_load_image_raw_sector does support loading
legacy/raw images. Since these images could not have been booted before, I
have disabled support for legacy/raw images on these four boards. This
reduces bloat from around 800 bytes to around 200.
There are no in-tree boards with SPL_LOAD_IMX_CONTAINER and AHAB_BOOT both
enabled, so we do not need to worry about potentially falling back to
legacy images in a secure boot scenario.
Future work could include merging imx_container.h with imx8image.h, since
they appear to define mostly the same structures.
Sean Anderson [Sat, 14 Oct 2023 20:47:38 +0000 (16:47 -0400)]
spl: nor: Don't allocate header on stack
spl_image_info.name contains a reference to legacy_img_hdr. If we allocate
the latter on the stack, it will be clobbered after we return. This was
addressed for NAND back in 06377c5a1fc ("spl: spl_legacy: Fix NAND boot on
OMAP3 BeagleBoard"), but that commit didn't fix NOR.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Sean Anderson [Sat, 14 Oct 2023 20:47:37 +0000 (16:47 -0400)]
spl: legacy: Fix referencing _image_binary_end
On non-arm architectures, _image_binary_end is defined as a ulong and not a
char[]. Take the address of it when accessing it, which is correct for
both.
Fixes: 1b8a1be1a1f ("spl: spl_legacy: Fix spl_end address") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 30 Sep 2023 20:42:46 +0000 (16:42 -0400)]
Revert "fs: ext4: check the minimal partition size to mount"
This check breaks small partitions (under 1024 blocks) because part_length
is in units of part.blksz and not bytes. Given the purpose of this
function, we really want to make sure the partition is SUPERBLOCK_START +
SUPERBLOCK_SIZE (2048) bytes so we can call ext4_read_superblock without
error.
The obvious solution is to convert callers from things like
ext4fs_mount(part_info.size)
to
ext4fs_mount(part_info.size * part_info.blksz);
However, I'm not really a fan of the bloat that would cause, especially
since the error is now suppressed. I think the best course of action here
is to just revert the patch.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Sean Anderson [Sun, 8 Oct 2023 01:47:48 +0000 (21:47 -0400)]
spl: mmc: Fix subsequent calls to spl_mmc_load with CONFIG_BLK
MMC devices do not have uclass platdata containing blk_descs, only their
child block devices do. Fortunately, we have a function just for this
purpose. This fixes subsequent calls to spl_mmc_load.
Fixes: bf28d9a6599 ("spl: mmc: Use correct MMC device when loading image") Signed-off-by: Sean Anderson <seanga2@gmail.com>
Paul Barker [Mon, 16 Oct 2023 09:25:43 +0000 (10:25 +0100)]
board: rzg2l: Add RZ/G2L SMARC EVK board
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car gen3/gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on and
this is used to select the appropriate device tree to load.
The configuration renesas_rzg2l_smarc_defconfig is added to support
building for this target. In the future this defconfig will be extended
to support other SoCs and evaluation boards from the RZ/G2L family.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Mon, 16 Oct 2023 09:25:42 +0000 (10:25 +0100)]
arm: dts: Import RZ/G2L SMARC EVK device tree
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
Paul Barker [Mon, 16 Oct 2023 09:25:41 +0000 (10:25 +0100)]
arm: rmobile: Support RZ/G2L memory map
The memory map for the RZ/G2L family differs from that of previous R-Car
Gen3/Gen4 SoCs.
A high level memory map can be seen in figure 5.2 (section 5.2.1) of the
RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included
here (note that this is a 34-bit address space):
* 0x0_0000_0000 - 0x0_0002_FFFF SRAM area
* 0x0_0003_0000 - 0x0_0FFF_FFFF Reserved area
* 0x0_1000_0000 - 0x0_1FFF_FFFF I/O register area
* 0x0_2000_0000 - 0x0_2FFF_FFFF SPI Multi area
* 0x0_3000_0000 - 0x0_3FFF_FFFF Reserved area
* 0x0_4000_0000 - 0x1_3FFF_FFFF DDR area (4 GiB)
* 0x1_4000_0000 - 0x3_FFFF_FFFF Reserved area
Within the DDR area, the first 128 MiB are reserved by TrustedFirmware.
The region from 0x43F00000 to 0x47DFFFFF inclusive is protected for use
in TrustedFirmware/OP-TEE, but all other memory is included in the
memory map. This reservation is the same as used in R-Car
Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs.
DRAM information is initialised based on the data in the fdt.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Mon, 16 Oct 2023 09:25:40 +0000 (10:25 +0100)]
arm: rmobile: Add CPU detection for RZ/G2L
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car Gen3/Gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on.
We do this as reading the DEVID & PRR registers from u-boot is not
sufficient to differentiate between the R9A07G044L (RZ/G2L) and
R9A07G044C (RZ/G2LC) SoCs. An additional read from offset 0x11861178 is
needed but this address is in the OTP region which can only be read from
the secure world (i.e. TrustedFirmware). So we have to rely on
TrustedFirmware to determine the SoC and pass this information to u-boot
via an fdt blob.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Mon, 16 Oct 2023 09:25:38 +0000 (10:25 +0100)]
mmc: renesas-sdhi: Initialize module on RZ/G2L
On the Renesas RZ/G2L SoC family, we must ensure that the required clock
signals are enabled and the reset signal is de-asserted before we try to
communicate with the SDHI module.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Paul Barker [Mon, 16 Oct 2023 09:25:37 +0000 (10:25 +0100)]
mmc: renesas-sdhi: Refactor probe function
Move the assignment of priv->quirks earlier in the function. This allows
us to drop the quirks local variable and makes it easier to maintain
clean error handling when we add RZ/G2L support in the next patch.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Sun, 15 Oct 2023 22:41:14 +0000 (00:41 +0200)]
arm64: dts: imx8mp: Make GPIO3 available early in U-Boot proper on i.MX8MP DHCOM
The GPIO3 has to be available early during U-Boot proper start up for
DRAM size detect to work correctly. The GPIO3 is currently available in
SPL and late in U-Boot proper, which is insufficient. Add the missing
bootph-all to make the GPIO3 available also early in U-Boot proper.
The current imx8mp-dhcom-som.dtsi describes production rev.200 SoM,
add DT overlay which reinstates rev.100 SoM description to permit
prototype rev.100 SoMs to be used until they get phased out.
Marek Vasut [Thu, 21 Sep 2023 18:44:19 +0000 (20:44 +0200)]
arm64: dts: imx8mp: Drop i.MX8MP DHCOM rev.100 PHY address workaround from PDK3 DT
In case the i.MX8MP DHCOM rev.100 has been populated on the PDK3
carrier board, the on-SoM PHY PHYAD1 signal has been pulled high
by the carrier board and changed the PHY MDIO address from 5 to 7.
This has been fixed on production rev.200 SoM by additional buffer
on the SoM PHYAD/LED signals, remove the workaround.
Marek Vasut [Thu, 21 Sep 2023 18:44:18 +0000 (20:44 +0200)]
arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200
The current imx8mp-dhcom-som.dtsi describes prototype rev.100 SoM,
update the DT to describe production rev.200 SoM which brings the
following changes:
- Fast SoC GPIOs exposed on the SoM edge connector
- Slow GPIOs like component resets moved to I2C GPIO expander
- ADC upgraded from TLA2024 to ADS1015 with conversion interrupt
- EEPROM size increased from 256 B to 4 kiB
Marek Vasut [Thu, 21 Sep 2023 18:44:17 +0000 (20:44 +0200)]
arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM
Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100
population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3
carrier boards.
Use SPL DTO support to apply matching SoM specific DTO to cater
for the SoM differences. Remove ad-hoc patching of control DT from
fdtdec_board_setup().
Marek Vasut [Thu, 21 Sep 2023 18:44:16 +0000 (20:44 +0200)]
spl: fit: Add board level function to decide application of DTO
Add board-specific function used to indicate whether a DTO from fitImage
configuration node 'fdt' property DT and DTO list should be applied onto
the base DT or not applied.
This is useful in case of DTOs which implement e.g. different board revision
details, where such DTO should be applied on one board revision, and should
not be applied on another board revision.
projects / u-boot.git / log