- Convert GoFlex Home Ethernet and SATA to Driver Model (Tony)
- mvebu: Automatically detect CONFIG_SYS_TCLK (Pavel)
- mvebu: sata_mv: Fix HDD identication during cold start (Tony)
- a37xx: pci: Fix handling PIO config error responses (Pavel)
- Other minor misc changes and board maintainer updates
Tom Rini [Wed, 11 Aug 2021 12:31:13 +0000 (08:31 -0400)]
Merge tag 'u-boot-amlogic-20210810' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- odroid-n2: fix fdtfile suffix for n2-plus
- sei610 & meson64_android cleanups to prepare android 11 boot support
- use Android BCB mechanism for reboot reason instead of HW reboot flag
- Switch meson64_android boot flow to use abootimg for A/B, AVB and DTBO support
Pali Rohár [Mon, 9 Aug 2021 15:44:35 +0000 (17:44 +0200)]
arm: mvebu: Hang if ddr3_init() fails
If ddr3_init() fails then DDR was not initialized and we cannot load and
execute U-Boot. We cannot continue, we cannot do anything in this case, so
hang.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Mon, 9 Aug 2021 07:53:13 +0000 (09:53 +0200)]
arm: a37xx: pci: Fix handling PIO config error responses
Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to OS is
allowed only for 4-byte PCI_VENDOR_ID config read request and only when
CRSSVE bit in Root Port PCIe device is enabled. In all other error PCIe
Root Complex must return all-ones.
So implement this logic in pci-aardvark.c driver properly.
aardvark HW does not have Root Port PCIe device and U-Boot does not
implement emulation of this device. So expect that CRSSVE bit is set as
U-Boot can already handle CRS value for PCI_VENDOR_ID config read request.
More callers of pci_bus_read_config() function in U-Boot do not check for
return value, but check readback value. Therefore always fill readback
value in pcie_advk_read_config() function. On error fill all-ones of
correct size as it is required for PCIe Root Complex.
And also correctly propagates error from failed config write request to
return value of pcie_advk_write_config() function. Most U-Boot callers
ignores this return value, but it is a good idea to return correct value
from function.
These issues about return value of failed config read requests, including
special handling of CRS were reported by Lorenzo and Bjorn for Linux kernel
driver pci-aardvark together with quotes from PCIe r4.0 spec, see details:
https://lore.kernel.org/linux-pci/20210624213345.3617-1-pali@kernel.org/t/#u
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Sun, 1 Aug 2021 03:29:35 +0000 (20:29 -0700)]
arm: mvebu: sata_mv failed to identify HDDs during cold start
During cold start, with some HDDs, mv_sata_identify() does not populate
the ID words on the 1st ATA ID command. In fact, the first ATA ID
command will only power up the drive, and then the ATA ID command
processing is lost in the process.
- The Seagate ST9250320AS 250GB took about 3 seconds to spin up.
- The Seagate ST4000DM004-2CV104 4TB took about 8 seconds to spin up.
- mv_sata_identify() did not populate the ID words after the call to
mv_ata_exec_ata_cmd_nondma().
- Attempt to insert a long delay of 30 seconds, ie. mdelay(30_000), after
the call to ata_wait_register() inside mv_ata_exec_ata_cmd_nondma() did
not help with the 4TB drive. The ID words were still empty after that 30s
delay.
Patch Description:
- Added a second ATA ID command in mv_sata_identify(), which will be
executed if the 1st ATA ID command did not return with valid ID words.
- Use the HDD drive capacity in the ID words as a successful indicator of
ATA ID command.
- In the scenario where a box is rebooted, the 1st ATA ID command is always
successful, so there is no extra time wasted.
- In the scenario where a box is cold started, the 1st ATA command is the
power up command. The 2nd ATA ID command alleviates the uncertainty of
how long we have to wait for the ID words to be populated by the SATA
controller.
Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files
to correct SOC/platform value. So do not overwrite it in board config
include files.
Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses
200 MHz TCLK.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove
useless default CONFIG_SYS_TCLK value from the end of soc.h file.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Fri, 30 Jul 2021 03:02:43 +0000 (20:02 -0700)]
arm: kirkwood: GoFlex Home: Use Ethernet PHY name and address from device tree
In DM Ethernet, the old "egiga0" name is no longer valid,
so replace these with Ethernet PHY names from device tree. Also, read
Ethernet PHY address from device tree.
Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
configs: sei510/610: android bootflow via abootimg
Activate the following Kconfig options:
* AVB for Android Verified Boot support
* ADTIMG for merging DTBOs
* ABOOTIMG for extracting Android boot image
Also rework the partitioning tables:
- add a misc partition to handle BCB messages
- add a dtbo partition to store various DTBOs
- add a vbmeta partition for AVB hashes
- Merge vendor and system into the "super" partition
Note: avb support is disables by default. To activate it:
=> setenv force_avb 1;
=> saveenv;
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
configs: sei510/sei610: don't use hard-coded gpt uuids
doc/README.gpt states:
> The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
> enabled. A random uuid will be used if omitted or they point to an empty/
> non-existent environment variable. The environment variable will be
> set to the generated UUID. The 'gpt guid' command reads the current
> value of the uuid_disk from the GPT.
Since we have CONFIG_RANDOM_UUID=y, remove the hard-coded uuids
and use meaningful variable names instead.
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
configs: meson64_android: boot android via abootimg
Since Android 10, we are required to use a "dtbo" partition which
includes the various device-tree overlays [1].
It's also possible to provide a "dtb" partition.
This is supported via the "abootimg" command.
On Yukawa, the assumption is that we have only a "dtbo" partition, which
includes all board dtbs and their dtbos [2]
[1] https://source.android.com/devices/architecture/dto/partitions
[2] https://android.googlesource.com/device/amlogic/yukawa/+/refs/heads/master/build/tasks/dtimages.mk#16 Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
configs: meson64_android: increase SYS_MALLOC_LEN to 128M for AVB
To prepare for AVB support, increase SYS_MALLOC_LEN to 128M.
This value has been found by testing the following on khadas vim3l:
=> avb init
=> avb verify
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
board: amlogic: odroid-n2: fix fdtfile suffix for n2-plus
The N2+ dtb is meson-g12b-odroid-n2-plus.dtb, not n2_plus, so
correct the suffix provided in the board file. Also align the
board ident string shown during boot to match.
Fixes: 8bc780106c13 ("board: amlogic: odroid: add runtime detection of the N2/N2+/C4/HC4 variants") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
- new SOC: add support for imx8ulp
- Toradex fixes for colibri (vf / imx6 / imx7 / imx8x)
- convert to DM for mx28evk
- Fixes for Gateworks ventana boards
Peng Fan [Sat, 7 Aug 2021 08:01:13 +0000 (16:01 +0800)]
arm: imx: add i.MX8ULP EVK support
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART
Log as below: I would keep some debug info for now, and after we move
to be stable and production launch, we could drop that.
U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800)
Normal Boot
upower_init: soc_id=48
upower_init: version:11.11.6
upower_init: start uPower RAM service
user_upwr_rdy_callb: soc=b
user_upwr_rdy_callb: RAM version:12.6
Turn on switches ok
Turn on memories ok
Clear DDR retention ok
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F0 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
Poll for freq_chg_req on SIM register and change to F1 frequency.
Poll for freq_chg_req on SIM register and change to F2 frequency.
complete
De-Skew PLL is locked and ready
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x3a800 by ROM_API
NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94
NOTICE: BL31: Built : 01:56:58, Jun 29 2021
NOTICE: upower_init: start uPower RAM service
NOTICE: user_upwr_rdy_callb: soc=b
NOTICE: user_upwr_rdy_callb: RAM version:12.6
CPU: Freescale i.MX8ULP rev1.0 at 744 MHz
Reset cause: POR
Boot mode: Single boot
Model: FSL i.MX8ULP EVK
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... ***
Warning - bad CRC, using default environment
In: serial@293a0000
Out: serial@293a0000
Err: serial@293a0000
Net:
Warning: ethernet@29950000 (eth0) using random MAC address -
96:35:88:62:e0:44
eth0: ethernet@29950000
Hit any key to stop autoboot: 0
Ye Li [Sat, 7 Aug 2021 08:01:07 +0000 (16:01 +0800)]
imx8ulp: Use DGO_GP5 to get boot config
Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian,
it does not connect to low 16 bits for RTD. So we can't get the correct
boot mode.
Change to use DGO_GP5 of SEC_SIM which is set by ROM.
Peng Fan [Sat, 7 Aug 2021 08:00:58 +0000 (16:00 +0800)]
arm: imx8ulp: release trdc and assign lpav from RTD to APD
Rlease LPAV from RTD to APD
Release gpu2D/3D to APD
Set TRDC MBC2 MEM1 for iomuxc0 access
Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c
and MODE pins. we have to open iomuxc0 access for A35 core (domain 7)
in single boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:55 +0000 (16:00 +0800)]
arm: imx8ulp: release and configure XRDC at early phase
Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.
1. Set the parameters save/restore only for u-boot, not for SPL. to
avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 7 Aug 2021 08:00:48 +0000 (16:00 +0800)]
arm: imx8ulp: Enable full L2 cache in SPL
SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.
So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 7 Aug 2021 08:00:35 +0000 (16:00 +0800)]
arm: imx: basic i.MX8ULP support
Add basic i.MX8ULP support
For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Select CONFIG_IMX_HAB so that the "hab_status" command
becomes available, which is useful for checking if the
chip has been correctly setup to run in secure boot mode.
Tim Harvey [Tue, 27 Jul 2021 22:19:41 +0000 (15:19 -0700)]
board: gateworks: venice: add imx8mm-gw7902 support
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- LTE CAT M1 modem
- USB 2.0 HUB
- M.2 Socket with USB2.0, PCIe, and dual-SIM
- IMX8M FEC
- PCIe based GbE
- RS232/RS485/RS422 serial transceiver
- GPS
- CAN bus
- WiFi / Bluetooth
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- PMIC
Do the following to add support for it:
- add dts
- add PMIC config
Tim Harvey [Tue, 27 Jul 2021 22:19:39 +0000 (15:19 -0700)]
board: gateworks: venice: add board model/serial# to env
Add board model/serial# strings to env. Move the creation of the strings
to gsc_read() and the display of the info into gsc_info() so they are
available to U-Boot proper.
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties
not supported by U-Boot drivers/net/phy/dp83867.c with the proper
'ti,fifo-depth' property.
Tim Harvey [Tue, 27 Jul 2021 22:19:34 +0000 (15:19 -0700)]
arm: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12
is the power-enable to the TPS25821 Source controller and power switch
responsible for monitoring the CC pins and enabling VBUS. Therefore
GPIO1_12 must always be enabled and the vbus output enable from the
IMX8MM can be ignored.
To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the
TPS25821 and change the regulator output to GPIO1_10 which is
unconnected.
The intention of commit d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT
with CONFIG_IMX_HAB") was to convert from CONFIG_SECURE_BOOT to
CONFIG_IMX_HAB, but it replaced with an extra "_" character.
Fix it by using the correct CONFIG_IMX_HAB symbol.
Tim Harvey [Sat, 24 Jul 2021 17:40:46 +0000 (10:40 -0700)]
imx: ventana: add support for GW54xx-G revision
The GW54xx-G revision has the foolowing changes:
- replaces the EOL GbE PHY with an updated part (requires an enable pin)
- replaces the EOL analog video decoder with an updated part
(requires dt prop)
- add power control to miniPCIe socket
Tim Harvey [Sat, 24 Jul 2021 17:40:45 +0000 (10:40 -0700)]
imx: ventana: add support for GW53xx-G revision
The GW53xx-G revision has the foolowing changes:
- replaces the EOL GbE PHY with an updated part (requires an enable pin)
- replaces the EOL analog video decoder with an updated part
(requires dt prop)
- add power control to miniPCIe socket
Tim Harvey [Sat, 24 Jul 2021 17:40:44 +0000 (10:40 -0700)]
imx: ventana: add GW5913 support
The GW5913 is a Single Board Computer based on the NXP i.MX6Q/DL SoC
with the following features:
- DDR3 DRAM
- NAND FLASH (256MiB or 2048MiB)
- Gateworks System Periperhal Controller
- front panel LED's
- front panel pushbutton
- Digital I/O connector (I2C/GPIO/UART)
- u-blox Zoe-M8Q GPS
- 1x RJ45 GbE
- 1x MiniPCIe socket with PCIe USB 2.0 and nanoSIM socket
- Passive PoE and wide-range DC power supply
Tim Harvey [Sat, 24 Jul 2021 17:40:43 +0000 (10:40 -0700)]
imx: ventana: add GW5912 support
The GW5912 is a Single Board Computer based on the NXP i.MX6Q/DL SoC
with the following features:
- DDR3 DRAM
- NAND FLASH (256MiB or 2048MiB)
- microSD socket
- Gateworks System Periperhal Controller
- front panel LED's
- front panel pushbutton
- RS232 connector (2x UARTs)
- CAN/RS485 connector
- Digital I/O connector (I2C/GPIO)
- SPI connector
- u-blox Zoe-M8Q GPS
- LIS2DE12 Accellerometer
- 1x FEC GbE RJ45 with 802.3at Active PoE
- 1x PCI GbE RJ45 with Passive PoE
- 5x MiniPCIe socket with PCIe/USB 2.0
- 1x MiniPCIe socket with PCIe/USB 2.0 and SIM socket
- Aux power input with wide-range DC power supply
Tim Harvey [Sat, 24 Jul 2021 17:40:42 +0000 (10:40 -0700)]
imx: ventana: add GW5910 support
The GW5910 is a Single Board Computer based on the NXP i.MX6Q/DL SoC
with the following features:
- DDR3 DRAM
- NAND FLASH (256MiB or 2048MiB)
- microSD socket
- Gateworks System Periperhal Controller
- front panel LED's
- front panel pushbutton
- RS232 connector (2x UARTs)
- Digital I/O connector (I2C/GPIO)
- SPI connector
- u-blox Zoe-M8Q GPS
- LIS2DE12 Accellerometer
- TI CC1352 ARM Cortex-M4 multiprotocol sub-1GHz / 2.4GHz wireless MCU
- On-board brcmfmac WiFi and BT module
- RGMII RJ45 GbE
- 1x MiniPCIe socket with PCIe/USB 2.0
- 1x MiniPCIe socket with USB 2.0 and nanoSIM socket
- Passive PoE and wide-range DC power supply
Tim Harvey [Sat, 24 Jul 2021 17:40:36 +0000 (10:40 -0700)]
imx: ventana: fix UMS support
The Gateworks Ventana boards have always had usb0=usbh1 and usb1=usbotg
because OTG is often subloaded on these boards and a bit in the EEPROM
which flagging that OTG is subloaded is used to remove the dt node via the
alias.
U-Boot DM_USB UMS requires the usb0 alias be assigned to the usbotg
so fix the usb0 alias in order for UMS to work.
Fixes 72c46327f03f: ("imx: ventana: enable dm support for USB")
projects / u-boot.git / log