Miquel Raynal [Wed, 28 Feb 2018 19:51:55 +0000 (20:51 +0100)]
spl: nand: sunxi: use PIO instead of DMA
SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.
Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.
There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.
The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:52 +0000 (20:51 +0100)]
spl: nand: sunxi: make the reset column helper more generic
Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:51 +0000 (20:51 +0100)]
spl: nand: sunxi: ensure enough time has passed after changing the column
When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:50 +0000 (20:51 +0100)]
spl: nand: sunxi: create an helper to handle command execution
Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it with the new
command.
* Clearing the status register.
* Writing the command in the FIFO.
* Waiting for the command to finish.
Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:48 +0000 (20:51 +0100)]
spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper
One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.
Add this sanity check before starting any new command.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:47 +0000 (20:51 +0100)]
spl: nand: sunxi: introduce the nand_wait_int() helper
The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:45 +0000 (20:51 +0100)]
spl: nand: sunxi: fix second case of modulo by zero error
In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).
This situation turns out to lead to a run time freeze with certain
toolchains.
Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73e3 ("nand: sunxi: Fix modulo
by zero error").
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:44 +0000 (20:51 +0100)]
mtd: nand: sunxi: fix ECC strength choice
When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.
For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.
Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Miquel Raynal [Wed, 28 Feb 2018 19:51:43 +0000 (20:51 +0100)]
spl: fix binman_sym output check
A previous commit introduced the use of binman in the SPL.
After the binman_sym call over the 'pos' symbol, the output value is
checked against BINMAN_SYM_MISSING (-1UL). According to the
documentation (tools/binman/README), when it comes to the 'pos'
attribute:
pos:
This sets the position of an entry within the image. The first
byte of the image is normally at position 0. If 'pos' is not
provided, binman sets it to the end of the previous region, or
the start of the image's entry area (normally 0) if there is no
previous region.
So instead of checking if the return value is BINMAN_SYM_MISSING, we
should also check if the value is not null.
The failure happens when using both the SPL file and the U-Boot file
independently instead of the concatenated file (SPL + padding + U-Boot).
This is because the U-Boot binary file alone does not have the U-Boot
header while it is present in the concatenation file. Not having the
header forces the SPL to discover where it should load U-Boot. The
binman_sym call is supposed to do that but fails. Because of the wrong
check, the destination address was set to 0 while it should have been
somewhere in RAM. This, obviously, stalls the board.
Fixes: 8bee2d251afb ("binman: Add binman symbol support to SPL") Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Patrick Delaunay [Mon, 12 Mar 2018 08:22:44 +0000 (09:22 +0100)]
post: remove reference to power functions
The 2 functions board_power_mode and board_poweroff
are no more existing in U-Boot code (check with grep)
This patch updates the documentation and removes
the unnecessary prototypes.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add a new file init.h with the prototype for arch_cpu_init
Add a prototype for mach_cpu_init() to avoid a warning:
no previous prototype for ‘mach_cpu_init’
It is a first step to move all the functions prototype
used during U-Boot initialization (board_f.c / board_r.c)
from common.h to init.h
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Wed, 7 Mar 2018 00:02:27 +0000 (19:02 -0500)]
Convert all of CONFIG_CONS_INDEX to Kconfig
This converts the following to Kconfig:
CONFIG_CONS_INDEX
We have existing entries for this option in a number of places, with
different guards on them. They're also sometimes used for things not
directly inside of the serial driver. First, introduce a new symbol to
guard the use of CONFIG_CONS_INDEX, so that in the case where we don't
need this for the serial driver, but for some other use, we can still do
it. Next, consolidate all of these into the single entry in
drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that
we can imply a correct value here to make the defconfig side of this
smaller.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rework a lot of the logic here, such that I took authorship from
Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 7 Mar 2018 00:02:26 +0000 (19:02 -0500)]
dra7xx: Always enable UART1 and UART3 in early_padconf
It is safe to always setup the pinmux for UART1 and UART3 to be used in
early_padconf and then if these pins are needed later on, they will be
re-muxed. This allows us to drop the usage of CONFIG_CONS_INDEX here.
Jagan Teki [Wed, 14 Mar 2018 13:28:03 +0000 (18:58 +0530)]
dm: MIGRATION: Add migration plan for DM_SPI & DM_SPI_FLASH
Due to adding various new functionalities with SPI and SPI-FLASH
subsystems which are rounding in Mailing list for year these long
term supporting spi driver which never seen any update with
driver-model conversion.
So added migration plan for DM_SPI and DM_SPI_FLASH with
deadline v2018.09
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Madan Srinivas [Tue, 6 Mar 2018 16:10:10 +0000 (11:10 -0500)]
defconfig: k2l_hs_evm: Add k2l_hs_evm_defconfig
Adds a dedicated defconfig to build TI K2L secure
devices and updates MAINTAINERS.
k2l_hs_evm_defconfig is created from the k2l_evm_defconfig
and removes support for SPL, as SPL is not supported on K2
HS devices. Corrects SYS_TEXT_BASE for HS devices.
Also adds TI_SECURE_DEVICE and FIT_IMAGE_POST_PROCESS to
include support for secure image creation and authentication
Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Andrew F. Davis <afd@ti.com>
Ruslan Bilovol [Thu, 1 Mar 2018 01:15:48 +0000 (03:15 +0200)]
watchdog: omap_wdt: improve watchdog reset path
Remove busy looping during watchdog reset.
Each polling of W_PEND_WTGR bit ("finish posted
write") after watchdog reset takes 120-140us
on BeagleBone Black board. Current U-Boot code
has watchdog resets in random places and often
there is situation when watchdog is reset
few times in a row in nested functions.
This adds extra delays and slows the whole system.
Instead of polling W_PEND_WTGR bit, we skip
watchdog reset if the bit is set. Anyway, watchdog
is in the middle of reset *right now*, so we can
just return.
This noticeably increases performance of the
system. Below are some measurements on BBB:
- DFU upload over USB 15% faster
- fastboot image upload 3x times faster
- USB ep0 transfers with 4k packets 20% faster
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
Sam Protsenko [Tue, 27 Feb 2018 22:26:15 +0000 (00:26 +0200)]
board: am335x: Set serial# variable
serial# variable is needed to show the device correctly in "fastboot
devices" output. It's useful when we have several devices (in fastboot
mode) connected to single host and want to choose which one to flash.
We can't use omap_die_id_serial() for this, because AM335x lacks
DIE_ID, as can be seen from AM335x TRM. Let's do next:
- reuse board_serial variable (obtained from EEPROM in
set_board_info_env() function) to set serial#
- if board_serial is "unknown", reuse ethaddr variable to set serial#
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Wenyou Yang [Fri, 9 Feb 2018 03:34:51 +0000 (11:34 +0800)]
clk: at91: add PLLADIV driver
As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Masahiro Yamada [Thu, 22 Feb 2018 10:00:08 +0000 (19:00 +0900)]
ARM: uniphier: change load addresses for bigger kernel image
The kernel size is getting bigger and bigger. Because the Android
common kernel is even bigger than the vanilla one, so images overlap
in the current memory layout.
Adjust the load address for a bigger kernel image.
Adam Ford [Wed, 7 Mar 2018 11:23:10 +0000 (05:23 -0600)]
omap3_logic: Enable DM_SPI
With the introduction of ("Boards,Need,to,Switch,DM] spi: omap3_spi:
Full dm conversion"), Driver Model for McSPI is now available on the
omap3. This enables the config by default on omap3_logic boards.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Jagan Teki [Wed, 14 Mar 2018 17:37:31 +0000 (23:07 +0530)]
spi: omap3: Fix redeclared error
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol
struct udevice *bus = dev->parent;
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Sat, 3 Mar 2018 23:49:02 +0000 (23:49 +0000)]
sunxi: move CONFIG_SYS_TEXT_BASE out of defconfigs
Commit 278b90ce786f ("configs: Migrate CONFIG_SYS_TEXT_BASE") made
CONFIG_SYS_TEXT_BASE a proper Kconfig variable, with the consequence
of moving the common definition shared by almost every sunxi board
into 123 individual defconfig files. But the U-Boot start address
for Allwinner boards is a platform decision which has been around for
ages, so defining it in each *board* config file seems a bit over the
top.
Define the standard values (160MB into DRAM for most SoCs, with two
SoC exceptions) if ARCH_SUNXI is selected, and delete the lines from
the individual defconfigs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Sam Protsenko [Tue, 27 Feb 2018 21:45:03 +0000 (23:45 +0200)]
omap: Fix AM335x build with enabled fastboot flash
When enabling CONFIG_FASTBOOT_FLASH in am335x_boneblack_defconfig, next
build errors and warnings occur:
arch/arm/mach-omap2/utils.c: In function ‘omap_set_fastboot_cpu’:
arch/arm/mach-omap2/utils.c:26:16: warning: implicit declaration of
function ‘omap_revision’ [-Wimplicit-function-declaration]
u32 cpu_rev = omap_revision();
^~~~~~~~~~~~~
arch/arm/mach-omap2/utils.c:29:7: error: ‘DRA762_ES1_0’ undeclared
(first use in this function)
Include asm/omap_common.h explicitly to avoid those.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
ARM: dts: dra7x: Make pinctrl and IOdelays for MMC2 available in SPL
The SPL can't use high speed MMC modes if the associated pinctrl and
IOdelays are described in the DTS.
Make them available in SPL by tagging the nodes with 'u-boot,dm-spl;'
configs: dra7xx_evm: Enable support for the HS200 mmc mode in the SPL
Beside enabling the support for HS200 in mmc core, enabling the HS200
support in the SPL requires multi-dtb support in the SPL because pinctrl
and IOdelays vary across SOCs.
Also we need to make sure that the pinctrl properties arenot removed from
the dts by setting CONFIG_OF_SPL_REMOVE_PROPS to remove only clocks and
interrupts properties.
ARM: dts: dra76-evm: shift to using common IOdelay data
Now that we have a device-tree include file with common
MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree
file to using that.
Also fix the name of the IO voltage regulator for mmc1.
Derald D. Woods [Mon, 26 Feb 2018 23:52:59 +0000 (17:52 -0600)]
ARM: omap3: evm: Sync with omap3_beagle configuration
This commit does the following for OMAP3 EVM:
- Track omap3_beagle changes where possible
- Remove CONFIG_SYS_MPUCLK and CONFIG_MTD which are not needed for the
default board configuration to work.
- Remove CONFIG_SPL_SYS_MALLOC_SIMPLE and CONFIG_SYS_MALLOC_F_LEN from
default config. CONFIG_SYS_MALLOC_F_LEN=0x400 is set by configuration
automatically. [allows board to boot with SERIAL_SEARCH_ALL=y]
- Use updated NAND layout:
Derald D. Woods [Mon, 26 Feb 2018 23:52:57 +0000 (17:52 -0600)]
ARM: omap3: beagle: Set 'mtdids' and 'mtdparts' in board file
BeagleBoard 'xM' does not really have NAND. CONFIG_MTDIDS_DEFAULT and
CONFIG_MTDPARTS_DEFAULT can/should be empty for 'xM'. This commit sets
the defined values if they exist.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Sam Protsenko [Mon, 26 Feb 2018 21:18:01 +0000 (23:18 +0200)]
env: ti: boot: Get rid of magic numbers
Get the start address and the size of partitions using partition names
rather than partition numbers. This way we can change the partition
table further without changing the boot code.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Sam Protsenko [Mon, 26 Feb 2018 21:17:59 +0000 (23:17 +0200)]
cmd: part: Allow passing partition name to start and size
Allow passing the partition name to "part start" and "part size"
commands, so we can avoid magic numbers in the environment.
Consider one real use-case: in include/environment/ti/boot.h we have
commands like these:
setenv boot_part 9
part start mmc ${mmcdev} ${boot_part} boot_start
part size mmc ${mmcdev} ${boot_part} boot_size
mmc read ${loadaddr} ${boot_start} ${boot_size}
Now suppose that we have changed the partition table and boot_part now
is 10. We will need to fix commands above. And anyone who relies on
these boot commands, will need to change them accordingly, too (this was
an actual case in our lab while testing Linux boot on Android
environment).
By providing the option to pass partition name instead, we fix mentioned
issue, by eliminating the necessity to use magic numbers.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Stephen Warren [Tue, 20 Feb 2018 19:51:55 +0000 (12:51 -0700)]
test/py: highlight warnings in the log summary
Currently, if a test emits a warning message but otherwise passes, there's
no indication of this in the log summary, which can lead to warnings being
missed. Enhance the test logic to explicitly mention warnings in otherwise
passing tests, and not to collapse the log sections for tests with
warnings, so that they're more easily seen when scanning the log.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Tue, 20 Feb 2018 19:51:54 +0000 (12:51 -0700)]
test/py: add MMC/SD block read test
Add a standalone MMC block read test. This allows direct testing of MMC
access rather than relying on doing so as a side-effect of e.g. DFU or
UMS testing, which may not be enabled on all platforms.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Kever Yang [Sat, 10 Feb 2018 09:55:38 +0000 (17:55 +0800)]
disk: part: use common api to lookup part driver
Do not need to scan disk every time when we get part info
by name.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[trini: Fix build in !CONFIG_HAVE_BLOCK_DEVICE case] Signed-off-by: Tom Rini <trini@konsulko.com>
Kever Yang [Sat, 10 Feb 2018 09:55:37 +0000 (17:55 +0800)]
disk: part: scan the disk if the part_type is unknown
If a DUT do not have partition table, and we write one with 'gpt write'
cmd, we should able to list the partition with 'part list' cmd.
It's reasonable to scan the disk again if the initial part_type is
unknown in case we just write a new one into disk.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Patrice Chotard [Wed, 28 Feb 2018 16:15:00 +0000 (17:15 +0100)]
mach-stm32: Use default memory map as background region
On linux kernel side, on STM32F7 and STM32H7 SoCs, DMA requires
uncachable regions. These regions are defined in DT.
Since kernel linux v4.15, on ARMv7-M Cortex, kernel is able
to configure MPU regions depending on DT settings.
As kernel is able to configure MPU, this allows to remove
MPU region settings in bootloader.
On Cortex M processors, MPU allows to use a default memory map.
(see B3.5.4 MPU Control Register, MPU_CTRL in
https://developer.arm.com/products/architecture/m-profile/docs/ddi0403/latest/armv7-m-architecture-reference-manual)
Use the default memory map as background region for all STM32 SoCs
family with an additional MPU region corresponding to the SDRAM area.
Patrice Chotard [Fri, 16 Feb 2018 12:27:03 +0000 (13:27 +0100)]
ARM: dts: Add support for stm32f746-evaluation board support
This board offers:
_ STM32F746NGH6 microcontroller with 1 Mbyte Flash and 320+4 Kbytes RAM
_ Six 5 V power supply options:
Power jack
ST-LINK/V2-1 USB connector
User USB HS connector
User USB FS1 connector
User USB FS2 connector
Daughterboard
_ SAI Audio DAC, stereo audio jack which supports headset with microphone
_ Stereo digital microphone, audio jack connector used to connect
external speakers
_ 2 Gbytes (or more) SDMMC interface microSD card
_ RF-EEPROM on I2C compatible serial interface
_ RS-232 communication
_ IrDA transceiver
_ JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded
_ IEEE-802.3-2002 compliant Ethernet connector
_ Camera module
_ 8Mx32 bit SDRAM, 1Mx16 bit SRAM & 8Mx16 bit Nor Flash
_ 512 Mbits QuadSPI Nor Flash
_ 5.7 inch 640x480 pixel TFT color LCD with capacitive touch panel
_ Joystick with 4-direction control and selector
_ Reset, WakeUp/Tamper or key button
_ 4 color user LEDs
_ Extension connectors & memory connectors for daughterboard or
wrapping board
_ USB OTG HS and FS with Micro-AB connectors
_ RTC with backup battery
_ CAN 2.0A/B compliant connection
_ Potentiometer
_ Motor control connector
More detailed information are available here :
http://www.st.com/en/evaluation-tools/stm32746g-eval.html
To compile stm32f746-eval board, use same defconfig as
stm32f746-disco, the only difference is to pass
"DEVICE_TREE=stm32746g-eval".
Patrice Chotard [Thu, 8 Feb 2018 16:25:19 +0000 (17:25 +0100)]
ARM: dts: stm32: limit sdio frequency to 14Mhz for stm32f429i-eval
This avoids the following errors while reading on mmc:
Read data bytes CRC error: 0x2
switch to partitions #0, OK
mmc0 is current device
Read data bytes CRC error: 0x82002
** Unrecognized filesystem type **
mmc: stm32: sdmmc2: add support for st, pin-ckinsdmmc_ckin
This patch adds "st,pin-ckin" support to activate sdmmc_ckin feature.
When using an external driver (a voltage switch transceiver),
it's advised to select SDMMC_CKIN feedback clock input to sample
the received data.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
mmc: stm32: sdmmc2: add hardware flow control support
The hardware flow control functionality is used to avoid
FIFO underrun (TX mode) and overrun (RX mode) errors.
The behavior is to stop SDMMC_CK during data transfer and
freeze the SDMMC state machines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
projects / u-boot.git / log