Tom Rini [Mon, 8 Jul 2024 14:45:02 +0000 (08:45 -0600)]
Merge tag 'u-boot-imx-master-
20240706' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21504
- Fixes for i.MX8M and i.MX93 clk-composite.
- Set CAN oscillator frequency based on model on verdin-imx8mm.
- Enable CAAM for phycore-imx8mp_defconfig.
- Miscellaneous improvements for Gateworks i.MX8M boards.
- Fix initramfs boot on msc_sm2s_imx8mp.
- Fixe EQoS on imx8mp-beacon-kit.
- Fix error message in fsl_esdhc_imx.
Tom Rini [Mon, 8 Jul 2024 14:44:26 +0000 (08:44 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Mon, 8 Jul 2024 14:43:56 +0000 (08:43 -0600)]
Merge branch 'next-clk-sync' of https://source.denx.de/u-boot/custodians/u-boot-sh
Michael Trimarchi [Fri, 5 Jul 2024 07:19:52 +0000 (09:19 +0200)]
clk: imx: add mux ops for i.MX8M composite clk
Upstream Linux commit
f90b68d6c8b0.
The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
It support target(smart) interface and normal interface. Target interface
is exported for programmer easy to configure ccm root. Normal interface
is also exported, but we not use it in our driver, because it will
introduce more complexity compared with target interface.
The normal interface simplified as below:
SEL_A GA
+--+ +-+
| +->+ +------+
CLK[0-7]--->+ | +-+ |
| | | +----v---+ +----+
| +--+ |pre_diva+----> | +---------+
| +--------+ |mux +--+post_div |
| +--+ |pre_divb+--->+ | +---------+
| | | +----^---+ +----+
+--->+ | +-+ |
| +->+ +------+
+--+ +-+
SEL_B GB
The mux in the upper pic is not the target interface MUX, target
interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7],
you are actually writing SEL_A or SEL_B depends on the internal
counter which will also control the internal "mux".
The target interface simplified as below which is used by Linux Kernel:
CLK[0-7]--->MUX-->Gate-->pre_div-->post_div
A requirement of the Target Interface's software is that the
target clock source is active, it means when setting SEL_A, the
current input clk to SEL_A must be active, same to SEL_B.
We touch target interface, but hardware logic actually also need
configure normal interface.
There will be system hang, when doing the following steps:
The initial state:
SEL_A/SEL_B are both sourcing from clk0, the internal counter
choose SEL_A.
1. switch mux from clk0 to clk1
The hardware logic will choose SEL_B and configure SEL_B to clk1.
SEL_A no changed.
2. gate off clk0
Disable clk0, then the input to SEL_A is off.
3. switch from clk1 to clk2
The hardware logic will choose SEL_A and configure SEL_A to clk2,
however the current SEL_A input clk0 is off, the system hang.
The solution to fix the issue is in step 1, write twice to
target interface MUX, it will make SEL_A/SEL_B both sources
from clk1, then no need to care about the state of clk0. And
finally system performs well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Michael Trimarchi [Fri, 5 Jul 2024 07:19:51 +0000 (09:19 +0200)]
clk: clk-mux: Make public the clk_fetch_parent_index
Make public the clk_fetch_parent_index and rename it. This allow
us to be reused in driver specialization
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Alexander Stein [Fri, 5 Jul 2024 13:27:24 +0000 (15:27 +0200)]
mmc: fsl_esdhc_imx: Fix error message
Add missing newline character and also add the return code of
regulator_set_value() to the output.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Leonard Anderweit [Fri, 5 Jul 2024 12:11:21 +0000 (14:11 +0200)]
configs: phycore-imx8mp_defconfig: Initialize caam
Initialize the Cryptographic Accelerator and Assurance Module.
Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Adam Ford [Thu, 4 Jul 2024 21:22:46 +0000 (16:22 -0500)]
ARM: dts: imx8mp-beacon-kit-u-boot: Drop EQoS clock work-around
Since commit
ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock"),
the clocks for the DWMAC driver can be configured, and removing
them breaks operation.
Fixes: ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock")
Suggested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Thu, 4 Jul 2024 12:03:37 +0000 (09:03 -0300)]
msc_sm2s_imx8mp: Adjust the initrd_addr location
Booting an initramfs with the current initrd_addr address may lead to
initramfs corruption and boot failure.
Fix the initramfs problem by applying the following layout
suggested by Tom Rini:
loadaddr=0x40480000 --> Gets moved to 0x40600000 in run-time:
Uncompressing Kernel Image
Moving Image from 0x40480000 to 0x40600000, end=
41e80000
fdt_addr_r= moved loadaddr + 128 MiB = 0x48600000
initrd_addr=fdt_addr_r + 512 KiB = 0x48680000
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Tue, 18 Jun 2024 22:54:20 +0000 (00:54 +0200)]
pinctrl: renesas: Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.9.3
Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.9.3,
commit
1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 18 Jun 2024 22:54:19 +0000 (00:54 +0200)]
clk: renesas: Synchronize R-Car R8A779H0 V4M clock tables with Linux 6.9.3
Synchronize R-Car R8A779H0 V4M clock tables with Linux 6.9.3,
commit
1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 18 Jun 2024 22:54:18 +0000 (00:54 +0200)]
clk: renesas: Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.9.3
Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.9.3,
commit
1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 18 Jun 2024 22:54:17 +0000 (00:54 +0200)]
clk: renesas: Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.9.3
Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.9.3,
commit
1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 18 Jun 2024 22:54:16 +0000 (00:54 +0200)]
clk: renesas: Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.9.3
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.9.3,
commit
1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 18 Jun 2024 22:54:15 +0000 (00:54 +0200)]
clk: renesas: Synchronize R-Car R8A77951 H3 clock tables with Linux 6.9.3
Synchronize R-Car R8A77951 H3 clock tables with Linux 6.9.3,
commit
1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Philip Oberfichtner [Tue, 4 Jun 2024 10:18:11 +0000 (12:18 +0200)]
usb: Assimilate usb_get_descriptor() to linux
Before this commit, usb_get_descriptor() failed for some flakey USB
devices. We hereby adopt the more robust linux implementation [1].
For instance, for the "Alcor Micro Corp. Flash Drive" (VID 0x058f, PID
0x6387), the following behavior occurs from time to time:
=> usb start
starting USB...
Bus xhci_pci: Register
10000840 NbrPorts 16
Starting the controller
USB XHCI 1.20
scanning bus xhci_pci for devices... usb_new_device: Cannot read configuration, skipping device 058f:6387
Signed-off-by: Philip Oberfichtner <pro@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
[1] From
a38297e3fb012 (Linux 6.9), see
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/usb/core/message.c?h=v6.9#n781
Marek Vasut [Wed, 22 Nov 2023 23:50:52 +0000 (00:50 +0100)]
usb: xhci: Replace terrible formatting with different terrible formatting
Replace one type of terrible code formatting with a different
type of terrible code formatting. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Hector Martin <marcan@marcan.st>
Michael Trimarchi [Tue, 2 Jul 2024 10:26:18 +0000 (12:26 +0200)]
clk: imx: Fix wrong flags assignment clk-composite-93
The mux flags (u8), div flags (u8), and gate flags (u8) are not the clk
flags (unsigned long). They have different meanings
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Michael Trimarchi [Tue, 2 Jul 2024 10:26:17 +0000 (12:26 +0200)]
clk: imx: Fix wrong flags assignment clk-composite-8m
The mux flags (u8), div flags (u8), and gate flags (u8) are not the clk
flags (unsigned long). They have different meanings
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Marek Vasut [Thu, 27 Jun 2024 00:13:16 +0000 (02:13 +0200)]
ARM: imx: Update Fast ethernet PHY MDIO addresses to match DH i.MX8MP DHCOM rev.200
The production DH i.MX8MP DHCOM SoM rev.200 uses updated PHY MDIO addresses
for the Fast ethernet PHYs. Update the base SoM DT and SoM rev.100 backward
compatibility DTO to cater for this change.
Since the MDIO address adjustment is now also in the rev.100 SoM DTO, not
only in the rev.100 PDK3 DTO, update Makefile accordingly as well, else the
DTC would complain about the DTO overriding the 'reg' property without also
updating the node unit-address, which is not doable without duplicating the
entire PHY node in the DTO, which leads to large amount of duplication with
no gain.
Fixes: 9de599ec3d59 ("arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200")
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 27 Jun 2024 00:13:15 +0000 (02:13 +0200)]
ARM: imx: Enable PCA953x driver on DH i.MX8MP DHCOM PDK2
Enable PCA953x GPIO expander driver in DH i.MX8MP DHCOM PDK2 configuration.
The PCA9539 GPIO expander is used on production DH i.MX8MP DHCOM SoM rev.200.
This is already enabled in DH i.MX8MP DHCOM PDK3 configuration so align the
two configurations.
Fixes: 9de599ec3d59 ("arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200")
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 27 Jun 2024 00:01:21 +0000 (02:01 +0200)]
ARM: imx: Enable cat and xxd commands on DH i.MX8M Plus DHCOM
Enable 'cat' command to print file from filesystem to stdout.
Enable 'xxd' command to hexdump file from filesystem to stdout.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 25 Jun 2024 08:26:15 +0000 (10:26 +0200)]
ARM: imx: verdin-imx8mm: Set CAN oscillator frequency based on model
The older i.MX8M Mini Verdin SoMs may came with 20 MHz SPI CAN controller
oscillator, the newer SoMs always use 40 MHz oscillator. Handle both by
overriding the oscillator frequency just before booting the kernel.
These are the known variants with 20 MHz oscillator:
- 0055, V1.1A, V1.1B, V1.1C and V1.1D, use a 20MHz oscillator
- 0059, V1.1A and V1.1B, use a 20MHz oscillator
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tom Rini [Fri, 5 Jul 2024 22:36:43 +0000 (16:36 -0600)]
Merge branch '2024-07-05-assorted-updates'
- Re-instate the zlib update, so we can fix it for this release,
assorted whitespace cleanups, allow mkimage to 'auto-conf' signing of
scripts, enhance ELF image support, add more HW rev support to e1000
driver, update am64x_evm config, correct mpc8xxx watchdog, update
phycore-am6 docs.
Tom Rini [Fri, 5 Jul 2024 15:44:54 +0000 (09:44 -0600)]
Revert "Revert "Merge patch series "zlib: Address CVE-2016-9841"""
Now that the release has happened, bring back the update to zlib.
This reverts commit
bbacdd3ef7762fbdeab43ceea5205d1fd0f25bbd.
Signed-off-by: Tom Rini <trini@konsulko.com>
Christophe Leroy [Thu, 27 Jun 2024 08:26:08 +0000 (10:26 +0200)]
watchdog: mpc8xxx: Fix timer value
Timer value is a 16 bits calculated from the wanted timeout and the
system clock. On powerpc/8xx, a timeout of 2s gives a value which
is over U16_MAX so U16_MAX shall be used. But the calculation is
casted to u16 so at the end the result is 63770 instead of 128906.
So the timer gets loaded with 63770 instead of 65535. It is not
a big difference in that case, but lets make the code correct and
cast to u32 instead of u16.
Fixes: 26e8ebcd7cb7 ("watchdog: mpc8xxx: Make it generic")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Marjolaine Amate [Mon, 24 Jun 2024 19:49:07 +0000 (19:49 +0000)]
pci_ids: fix i225 unprogrammed value
This patch fixes the I225 hardware default value
at 0x15FD meaning empty flash image
or the NVM configuration loading failed
Signed-off-by: Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
Marjolaine Amate [Mon, 24 Jun 2024 19:15:32 +0000 (19:15 +0000)]
e1000: add support for i226
This patch adds support for Intel Foxville I226
devices LM,V,I,K in e1000 driver.
Signed-off-by: Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
Anand Moon [Sun, 23 Jun 2024 17:40:21 +0000 (23:10 +0530)]
Fix Kconfig coding style from spaces to tab
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */Kconfig
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Roger Quadros [Sun, 23 Jun 2024 07:41:19 +0000 (10:41 +0300)]
configs: am64x_evm_a53_defconfig: Enable I2C GPIO drivers
The board has the TCA9554 I2C GPIO expander chip for expansion
board presence detection logic.
Enable the relevant I2C GPIO drivers.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Maxim Moskalets [Fri, 21 Jun 2024 11:42:10 +0000 (14:42 +0300)]
cmd: bootm: add ELF file support
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets <maximmosk4@gmail.com>
Alexander Dahl [Thu, 20 Jun 2024 14:20:59 +0000 (16:20 +0200)]
mkimage: Allow 'auto-conf' signing of scripts
U-Boot configured for verified boot with the "required" option set to
"conf" also checks scripts put in FIT images for a valid signature, and
refuses to source and run such a script if the signature for the
configuration is bad or missing. Such a script could not be packaged
before, because mkimage failed like this:
% tools/mkimage -T script -C none -d tmp/my.scr -f auto-conf -k tmp -g dev -o sha256,rsa4096 my.uimg
Failed to find any images for configuration 'conf-1/signature'
tools/mkimage Can't add hashes to FIT blob: -1
Error: Bad parameters for FIT image type
This is especially unfortunate if LEGACY_IMAGE_FORMAT is disabled as
recommended.
Listing the script configuration in a "sign-images" subnode instead,
would have added even more complexity to the already complex auto fit
generation code.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Wadim Egorov [Thu, 20 Jun 2024 12:05:54 +0000 (14:05 +0200)]
doc: board: phytec: phycore-am6: Describe UART based boot
Describe how to boot via UART.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Marek Vasut [Sun, 16 Jun 2024 15:19:11 +0000 (17:19 +0200)]
configs: Remove duplicate newlines
Drop all duplicate newlines from config headers.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Fri, 5 Jul 2024 16:22:53 +0000 (10:22 -0600)]
Merge branch 'qcom-main' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
Various minor fixes and improvements:
* Fix Qualcomm SPMI v5 support
* Move default environment to a file
* Add support for special pins (e.g ufs/mmc reset/data pins)
* IPQ moves to OF_UPSTREAM and receives some cleanup and MAINTAINERS
changes
* Add a reset driver for devices without PSCI
* msm8916 USB clock improvements for mobile devices
Tom Rini [Fri, 5 Jul 2024 14:09:23 +0000 (08:09 -0600)]
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Branch contains minor improvemets for existing tegra devices along
with bring up of 4 new devices (ASUS Transformers T20, Microsoft
Surface RT, Lenovo Ideapad Yoga 11 and WEXLER Tab 7t).
Tom Rini [Fri, 5 Jul 2024 14:07:00 +0000 (08:07 -0600)]
Revert "CI Changes"
This change was brought in by accident, revert.
This reverts commit
51aabf50e57f5139de31a4850347edbad8bb338b.
Signed-off-by: Tom Rini <trini@konsulko.com>
Caleb Connolly [Mon, 24 Jun 2024 02:23:29 +0000 (04:23 +0200)]
spmi: msm: correct max_channels for v5 controllers
Commit
ee1d8aa5ecf7 ("spmi: msm: support controller version 7") broke
support for channels > 128 on v5 controllers, resulting in some
peripherals (like the power button / pon) working but others (like
gpios) reading bogus data.
Correct max_channels for v5 controllers.
Fixes: ee1d8aa5ecf7 ("spmi: msm: support controller version 7")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 24 Jun 2024 12:31:59 +0000 (14:31 +0200)]
mach-snapdragon: move default environment to a file
Make use of CONFIG_DEFAULT_ENV_FILE and move the default qcom
environment to a file under board/qualcomm.
This is much cleaner and means we don't need to recompile on changing
the environment.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 24 Jun 2024 12:46:27 +0000 (14:46 +0200)]
spmi: msm: demote to debug()
Most devices have buttons exposed via the PMIC, the button polling
therefore triggers a log spam if debug logging is enabled.
Demote these to debug() so that they aren't printed unless LOG_DEBUG is
defined explicitly for this file.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Tue, 28 May 2024 08:31:57 +0000 (10:31 +0200)]
pinctrl: qcom: sm8650: add special pins pins configuration data
Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8650 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Neil Armstrong [Tue, 28 May 2024 08:31:56 +0000 (10:31 +0200)]
pinctrl: qcom: sm8550: add special pins pins configuration data
Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8550 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Neil Armstrong [Tue, 28 May 2024 08:31:55 +0000 (10:31 +0200)]
pinctrl: qcom: add support setting pin configuration for special pins
Use the previously introduced msm_special_pin_data to setup the special
pins configuration if the SoC driver have them specified.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Neil Armstrong [Tue, 28 May 2024 08:31:54 +0000 (10:31 +0200)]
arm: mach-snapdragon: gpio: introduce msm_special_pin_data
In order to help setup pin configuration for special pins (UFS, SDCard),
introduce the msm_special_pin_data struct largely inspired from the
Linux conterpart but with only U-Boot required fields.
This struct is added to the pins_data to allow specifying the special
pins data for each SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Neil Armstrong [Tue, 28 May 2024 08:31:53 +0000 (10:31 +0200)]
pinctrl: qcom: add support for bias-pull-down
Add support for bias-pull-down as an alternate of bias-pull-up.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Robert Marko [Tue, 28 May 2024 12:31:04 +0000 (14:31 +0200)]
clock: qcom: ipq4019: add I2C clocks
I2C clocks are not initialized by the SBL, so lets add support for clocks
required by both of the QUP I2C controllers.
BLSP1 AHB clock is already initialized by SBL, but QUP I2C driver is
requesting it so we have to add it to the enable list.
Based off QCS404 clock driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko [Wed, 24 Apr 2024 09:46:25 +0000 (11:46 +0200)]
MAINTAINERS: IPQ40XX: add pinctrl driver
Pinctrl drivers were moved to a dedicated directory but the entry was never
updated, so add the pinctrl-ipq4019 driver entry.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko [Wed, 24 Apr 2024 09:46:24 +0000 (11:46 +0200)]
MAINTAINERS: IPQ40XX: add clock-ipq4019 instead of reset driver
The reset handling was added to the clock drivers but the entry was never
updated, so add the clock-ipq4019 driver instead.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko [Wed, 24 Apr 2024 09:46:23 +0000 (11:46 +0200)]
MAINTAINERS: IPQ40XX: update GCC dt-bindings
The separate clock and reset dt-bindings for IPQ40XX were merged into one
recently, but the entry was not updated so do it now.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko [Wed, 24 Apr 2024 09:46:22 +0000 (11:46 +0200)]
MAINTAINERS: IPQ40XX: remove Luka Kovacic as maintainer
Luka Kovacic is no longer at Sartura, so remove him as one of IPQ40xx
maintainers.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko [Tue, 14 May 2024 10:17:52 +0000 (12:17 +0200)]
arm: dts: drop downstream IPQ4019 DTSI
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
lets drop our downstream DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Tue, 14 May 2024 10:17:51 +0000 (12:17 +0200)]
mach-ipq40xx: use OF_UPSTREAM
Now that drivers are compatible enough with the upstream DTS, there is no
reason to not use the upstream DTS, so imply OF_UPSTREAM by default.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Tue, 14 May 2024 10:17:50 +0000 (12:17 +0200)]
mach-ipq40xx: add CPU specific code
Provide basic DRAM info population from DT, cache setting and the
board_init stub.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Tue, 14 May 2024 10:15:02 +0000 (12:15 +0200)]
sysreset: add Qualcomm PSHOLD reset driver
Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sam Day [Mon, 6 May 2024 10:26:58 +0000 (10:26 +0000)]
ehci: msm: bring up iface + core clocks
This seems to be necessary on my samsung-a5. Without this patch, the
first access of EHCI registers causes a bus stall and subsequent reset.
I am unsure why this wasn't already necessary for db410c, perhaps those
clocks are already enabled on boot.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sam Day [Mon, 6 May 2024 10:26:54 +0000 (10:26 +0000)]
clk/qcom: apq8016: add support for USB_HS clocks
The newer "register map for simple gate clocks" support added for qcom
clocks is used. As a result gcc_apq8016 now has a mixture of the old and
new styles. I didn't (and still don't!) feel comfortable enough in this
area to update the existing code.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 7 May 2024 18:46:54 +0000 (18:46 +0000)]
qcom_defconfig: enable msm8916 and msm8996
Enable the clock/pinctrl drivers for these two SoCs. Previously left out
due to only being used on the db410c and db820c respectively which both
have their own board code. We can still boot these with most features
working without that board code.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Jonas Schwöbel [Sat, 2 Apr 2022 20:04:00 +0000 (22:04 +0200)]
board: lenovo: ideapad-yoga-11: add Lenovo Ideapad Yoga 11 support
The Lenovo IdeaPad Yoga 11 is a hybrid laptop/tablet Windows RT-based
computer released in late 2012. The device uses a 1.3 GHz quad-core
Nvidia Tegra 3 chipset with 2 GB of RAM, features a 11.6 inch 1366x768
screen and 32/64 GB of internal memory that can be supplemented with
a microSDXC card slot, full size SD card slot and 2 full size USB 2.0
ports.
Tested-by: Jethro Bull <jethrob@hotmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Jonas Schwöbel [Mon, 24 Jan 2022 17:06:33 +0000 (18:06 +0100)]
board: microsoft: surface-rt: add Microsoft Surface RT support
Surface RT is a hybrid tablet computer developed and manufactured
by Microsoft and shipped with Windows RT. The tablet uses a 1.3 GHz
quad-core Nvidia Tegra 3 chipset with 2 GB of RAM, features 10.8
inch 1366x768 screen and 32/64 GB of internal memory that can be
supplemented with a microSDXC card giving up to 200 GB of
additional storage.
Tested-by: Jethro Bull <jethrob@hotmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Tue, 11 Jul 2023 10:47:02 +0000 (13:47 +0300)]
board: wexler: qc750: add WEXLER Tab 7t support
WEXLER Tab 7t is a mini tablet computer developed by WEXLER that
runs the Android operating system. The device features a 7.0-inch
(180 mm) HD display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM,
8, 16 or 32 GB of storage that can be supplemented with a microSDXC
card giving up to 64 GB of additional storage and a full size USB
port.
Tested-by: Maksim Kurnosenko <asusx2@mail.ru>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Thu, 27 Jan 2022 17:42:04 +0000 (19:42 +0200)]
board: asus: transformer: add ASUS Transformer T20 family support
The Asus Eee Pad Transformer family are 2-in-1 detachable/slider
tablets developed by Asus that run the Android operating system.
The Eee Pad Transformers feature a 10.1-inch (260 mm) display,
an Nvidia Tegra 2 dual-core chip, 1 GB of RAM, and 16/32 GB of storage.
Transformers board derives from Nvidia Ventana development board.
This patch brings support for all 3 known T20 Transformers:
- Asus Eee Pad Transformer TF101
- Asus Eee Pad Transformer TF101G
- Asus Eee Pad Slider SL101
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # ASUS TF101
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Fri, 5 Jul 2024 07:16:48 +0000 (10:16 +0300)]
arm: tegra20: bct: add missing <vsprintf.h>
Fixes implicit declaration of function 'hextoul'
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Thu, 27 Jun 2024 15:31:41 +0000 (18:31 +0300)]
configs: transformer: simplify boot command
Drop boot device sequence re-definition since now it is default.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Tue, 18 Jun 2024 10:07:57 +0000 (13:07 +0300)]
include: configs: tegra-common-post: make usb first boot target
This ensures that the device can boot from a USB device prior to MMC. Useful
cases are when installing a new OS from USB while MMC still has a working OS
configuration or if the OS configuration is broken in late boot stages
(kernel boots but the system does not start).
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Tue, 14 May 2024 06:05:00 +0000 (09:05 +0300)]
video: tegra20: dc: use nvidia,head property to identify DC controller
Use existing nvidia,head device tree property to get DC controller id.
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Sun, 2 Jun 2024 13:26:39 +0000 (16:26 +0300)]
configs: paz00: enable EDID support
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tom Rini [Thu, 4 Jul 2024 22:11:08 +0000 (16:11 -0600)]
Merge patch series "xtensa: Enable qemu-xtensa board"
Jiaxun Yang <jiaxun.yang@flygoat.com> says:
Hi all,
This series enabled qemu-xtensa board.
For dc232b CPU it needs to be built with toolchain[1].
This is a side product of me investigating architectures
physical address != virtual address in U-Boot. Now we can
get it covered under CI and regular tests.
VirtIO devices are not working as expected, due to U-Boot's
assumption on VA == PA everywhere, I'm going to get this fixed
later.
My Xtensa knowledge is pretty limited, Xtensa people please
feel free to point out if I got anything wrong.
Thanks
[1]: https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc232b-elf.tar.gz
Jiaxun Yang [Tue, 18 Jun 2024 13:56:12 +0000 (14:56 +0100)]
CI Changes
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:11 +0000 (14:56 +0100)]
ci: Wire up qemu_xtensa_dc233c
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:10 +0000 (14:56 +0100)]
doc: New documentation for qemu-xtensa
Introduce the board and provide instructions on how to get
it work.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:09 +0000 (14:56 +0100)]
board: emulation: New board qemu-xtensa
Introduce the new board, define every bits.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:08 +0000 (14:56 +0100)]
dts/upsteam: Add Makefile for xtensa
It is required to get it xtensa OF_UPSTREAM work.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:07 +0000 (14:56 +0100)]
drivers: cpu: Add xtensa CPU driver
Implement various CPU related functions.
I'm actually just using it to get cpu clock frequency.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:06 +0000 (14:56 +0100)]
drivers: serial: Add xtensa semihosting driver
Add xtensa semihosting driver.
It can't use regular semihosting driver as Xtensa's has it's own
semihosting ABI.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:05 +0000 (14:56 +0100)]
xtensa: Bring in semihosting headers and config options
They are all directly imported from Linux kernel.
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:04 +0000 (14:56 +0100)]
xtensa: Define PLATFORM_ELFFLAGS
u-boot.elf target requires it to work.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:03 +0000 (14:56 +0100)]
xtensa: Implement phys virt conversion for PTP_MMU
For PTP_MMU our physical address is not directly mapped
into virtual address space, we need to access physical
memory from those fixed map segments.
Implement phys_to_virt and virt_to_phys hook to reflect
this setting.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:02 +0000 (14:56 +0100)]
xtensa: Correct define of _end symbol
So U-Boot is using _end symbol to detect location of devicetree
appended at the end of the ROM.
It needs to be calculated based on end of .data load address,
as in our lds .current address is address in RAM.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Tue, 18 Jun 2024 13:56:01 +0000 (14:56 +0100)]
xtensa: Move dram_init to xtfpga board file
This is a board level stuff.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tom Rini [Thu, 27 Jun 2024 13:43:20 +0000 (07:43 -0600)]
CI: Make pytest export JUnitXML
Both GitLab and Azure (and other CI systems) have native support for
displaying JUnitXML test report results. The pytest framework that we
use can generate these reports. Change our CI tests so that they will
generate these reports and then have the respective CI platform pick
them up. We write to different locations because of where each CI is
(and isn't) able to easily pass things along.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 18 Jun 2024 20:23:43 +0000 (14:23 -0600)]
test/py/tests: Update some network dependencies
On tests which require "tftpboot" we need to depend not on cmd_net but
rather cmd_tftpboot. And on tests which require cmd_pxe we do not need
to also depend on cmd_net as this should be handled already via Kconfig
logic.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 4 Jul 2024 15:25:51 +0000 (09:25 -0600)]
Merge patch series "testb: Various tweaks and fixes for Labgrid"
Simon Glass <sjg@chromium.org> says:
This series includes a number of mostly unrelated changes which are in
service of running U-Boot on a lab using Labgrid.
Simon Glass [Sun, 23 Jun 2024 20:30:33 +0000 (14:30 -0600)]
smbios: Correct error handling when writing tables
Since write_smbios_table() returns an address, we cannot use it to
return and error number. Also, failing on sysinfo_detect() breaks
existing boards, e.g. chromebook_link
Correct this by logging and swallowing the error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: a5a57562856 ("lib: smbios: Detect system properties via...")
Simon Glass [Sun, 23 Jun 2024 20:30:31 +0000 (14:30 -0600)]
test: Check help output
The current test doesn't check anything about the output. If a bug
results in junk before the output, this is not currently detected.
Add a check for the first line being the one expected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:30 +0000 (14:30 -0600)]
test: Decode exceptions only with sandbox
When a real board fails we don't want to decode the exception. Reserve
that behaviour for sandbox. Also avoid raising a new exception on
failure - just re-raise the existing one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:29 +0000 (14:30 -0600)]
test: dm: Show failing driver name
When a driver is not registered properly it is not clear which one it
is. Adjust test_dm_compat() to show this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:28 +0000 (14:30 -0600)]
log: Allow tests to pass with CONFIG_LOGF_FUNC_PAD set
This setting pads out the function names. Adjust the test to handle
this, since some boards use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:27 +0000 (14:30 -0600)]
test: Make bootstd init run only on sandbox
Tests for standard boot need disks to be set up, which can only be done
on sandbox, since adjusting disks on real hardware is not currently
supported. Mark the init function as sandbox-only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:25 +0000 (14:30 -0600)]
google: Disable TPMv2 on most Chromebooks
This feature is not present on older Chromebooks, so disable the
setting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Simon Glass [Sun, 23 Jun 2024 20:30:24 +0000 (14:30 -0600)]
sunxi: Mark scp as optional
This binary does not prevent the system from booting. Mark it optional
so that U-Boot can be built without it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Simon Glass [Sun, 23 Jun 2024 20:30:23 +0000 (14:30 -0600)]
am33xx: Provide a function to set up the debug UART
Since commit
0dba45864b2a ("arm: Init the debug UART") the debug UART is
set up in _main() before early_system_init() is called.
Add a suitable board_debug_uart_init() function to set up the UART in
SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:22 +0000 (14:30 -0600)]
initcall: Correct use of relocation offset
The relocation offset can change in some initcall sequences. Handle
this and make sure it is used for all debugging statements in
init_run_list()
Update the trace test to match.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Simon Glass [Sun, 23 Jun 2024 20:30:21 +0000 (14:30 -0600)]
dm: core: Enhance comments on bind_drivers_pass()
This part of driver model is a little subtle, so add some more comments
to promote better understanding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 23 Jun 2024 20:30:20 +0000 (14:30 -0600)]
trace: Update test to tolerate different trace-cmd version
Some versions of trace-cmd (or some machines?) show one less dot in the
CPU list.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 3 Jul 2024 20:44:12 +0000 (14:44 -0600)]
Merge patch series "cmd: avoid duplicate weak functions"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:
[trini: Patch 1/3 was replaced by my series merged just prior to this,
Heinrich's cover letter is lightly edited and any mistakes are my own]
If we have multiple weak implementations of functions, the linker might
choose any of these.
The EFI sub-systems uses invalidate_icache_all() after loading binaries.
Both the EFI sub-system and cmd/cache.c provide a weak
invalidate_icache_all() function. Remove the EFI instance.
For ARM11 functional implementation of invalidate_icache_all is missing.
Add it.
Heinrich Schuchardt [Sun, 16 Jun 2024 17:31:05 +0000 (19:31 +0200)]
efi_loader: avoid duplicate weak invalidate_icache_all()
If multiple weak implementations of a weak function exist, it is unclear
which one the linker should chose. cmd/cache.c already defines a weak
invalidate_icache_all().
We don't need a call to invalidate_icache_all() on x86.
ARM, RISC-V, and Sandbox provide an implementation.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Heinrich Schuchardt [Sun, 16 Jun 2024 17:31:04 +0000 (19:31 +0200)]
arm: implement invalidate_icache_all on ARM11
In EFI sub-system we rely on invalidate_icache_all() to invalidate the
instruction cache after loading binaries. Add the missing implementation on
ARM1136, ARM1176.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Wed, 3 Jul 2024 20:42:11 +0000 (14:42 -0600)]
Merge patch series "m68k: Implement a default flush_dcache_all"
Tom Rini <trini@konsulko.com> says:
Prior to this series we had some de-facto required cache functions that
were either unimplemented on some architectures or differently named.
This would lead in some cases to having multiple "weak" functions
available as well. Rework things so that an architecture must provide
these functions and it is up to that architecture if a "weak" default
function makes sense, or not.
Tom Rini [Wed, 19 Jun 2024 21:27:59 +0000 (15:27 -0600)]
cmd: cache: Remove weak functions
It should be up to an architecture to decide how to implement cache
functions, and if they need to use weak functions or not. Allowing the
cache command to be built without cache functionality implemented is
unhelpful. Further, guard the call to noncached_set_region with
CONFIG_SYS_NONCACHED_MEMORY as that's when it's implemented and again is
an architecture specific detail.
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 19 Jun 2024 21:27:58 +0000 (15:27 -0600)]
powerpc: Add the old invalidate_icache_all function
Add the old invalidate_icache_all function that prints a warning that
was previously found in cmd/cache.c
Signed-off-by: Tom Rini <trini@konsulko.com>