Bin Meng [Mon, 31 Jul 2023 13:56:02 +0000 (07:56 -0600)]
x86: Change testing logic of mtrr commit
On Coral U-Boot SPL programs some MTRRs and FSPv2 in U-Boot proper
needs to program MTRRs too. With current testing logic of mtrr
commit in init_cache_f_r(), the mtrr commit is skipped which won't
work as the queued mtrr requests include setup for DRAM regions.
Change the logic to allow such configuration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tweak to put back CONFIG_FSP_VERSION2 at top: Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 31 Jul 2023 15:31:26 +0000 (11:31 -0400)]
Merge tag 'u-boot-rockchip-20230731' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Update dwc3 generic driver and update support for rk3568/rk3328;
- Add boards:
rk3566: Pine64 Quartz64-A/B, SOQuartz on Model A/Blade/CM4-IO
rk3568: Radxa E25 Carrier Board
rk3588: Radxa ROCK5A
- Fixes and updates for chromebook veryon/jerry/speedy;
- SPI support fixes for rk3399/rk3568/rk3588;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
Jonas Karlman [Sun, 30 Jul 2023 12:30:26 +0000 (12:30 +0000)]
board: rockchip: Add Radxa E25 Carrier Board
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header.
Features tested on a Radxa E25 v1.4:
- SD-card boot
- eMMC boot
- USB host
- PCIe/Ethernet adapters is detected
- SATA
Jagan Teki [Tue, 6 Jun 2023 17:09:18 +0000 (22:39 +0530)]
configs: rockchip: Enable USB2PHY for RK3328 boards
Enable USB2PHY for all RK3328 boards.
=> usb start
starting USB...
Bus usb@ff5c0000: USB EHCI 1.00
Bus usb@ff5d0000: USB OHCI 1.0
Bus usb@ff600000: generic_phy_get_bulk : no phys property
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@ff580000: USB DWC2
scanning bus usb@ff5c0000 for devices... 2 USB Device(s) found
scanning bus usb@ff5d0000 for devices... 1 USB Device(s) found
scanning bus usb@ff600000 for devices... 2 USB Device(s) found
scanning bus usb@ff580000 for devices... 2 USB Device(s) found
scanning usb for storage devices... 2 Storage Device(s) found
=> usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Mass Storage (480 Mb/s, 500mA)
TS-RDF5A Transcend 000000000009
Jagan Teki [Tue, 6 Jun 2023 17:09:17 +0000 (22:39 +0530)]
clk: rockchip: rk3328: Handle usb480m phy clock
Handle USB480M clock ID in set_rate() and set_parent()
to allow the dt assigned-clocks and assigned-clock-parents
work on rk3328.dtsi
Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 6 Jun 2023 17:09:15 +0000 (22:39 +0530)]
configs: Enable DWC3 USB 3.0 on RK3328 boards
Enable USB 3.0 in all RK3328 boards.
=> usb start
starting USB...
Bus usb@ff5c0000: ehci_generic usb@ff5c0000: Failed to get clocks (ret=-19)
Port not available.
Bus usb@ff5d0000: USB OHCI 1.0
Bus usb@ff600000: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@ff580000: 1 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
1 Hub (12 Mb/s, 0mA)
U-Boot Root Hub
Jagan Teki [Tue, 6 Jun 2023 17:09:12 +0000 (22:39 +0530)]
arm64: dts: rockchip: Drop unused rk3328-xhci node
rk3328-xhci has been added due to the fact that the upstream
dwc3 is unsupported. Moreover, the driver for rk3328-xhci is
not added to the code tree.
By considering these facts and unsupported rk3328-xhci this
patch is dropping all related code from DT. However, the DWC3
is fixed now in dwc3-generic and RK3328 USB 3.0 is functional
in upcoming patches.
Let's drop it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 2 Jul 2023 12:41:15 +0000 (12:41 +0000)]
power: regulator: rk8xx: Add 500us delay after LDO regulator is enabled
A quick power cycle of a LDO regulator during dw-mmc signal voltage
change has shown that SD-card does not always get recognized.
Linux driver use an enable_time of 400us for LDO regulators. Apply a
500us delay when a LDO regulator is enabled to fix possible issues.
Fixes: 94afc1cb466a ("power: regulator: rk8xx: update the driver for rk808 and rk818") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: elaine.zhang<elaine.zhang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Tue, 4 Jul 2023 19:05:12 +0000 (22:05 +0300)]
board: rockchip: add Radxa ROCK5A Rk3588 board
ROCK 5A is a Rockchip RK3588S based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specifications:
Rockchip Rk3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
4-lane MIPI DSI connector
Audio – 3.5mm earphone jack
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x micro HDMI 2.1 ports, one up to 8Kp60, the other up to 4Kp60
Gigabit Ethernet RJ45 with optional PoE support
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 56mm (Raspberry Pi 4 form factor)
Kernel commits: d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board") 991f136c9f8d ("arm64: dts: rockchip: Update sdhci alias for rock-5a") 304c8a759953 ("arm64: dts: rockchip: Remove empty line from rock-5a") cda0c2ea65a0 ("arm64: dts: rockchip: Fix RX delay for ethernet phy on rk3588s-rock5a")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Tue, 4 Jul 2023 19:05:11 +0000 (22:05 +0300)]
ARM: dts: rockchip: rk3588: Move bootph-all props to common file
Move bootph-all prop to common SoC dt file, because they are typically used
by multiple boards.
Unreferenced nodes are removed from the SPL device tree during a
normal build.
Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 31 Jul 2023 04:28:34 +0000 (04:28 +0000)]
rockchip: rk3568-rock-3a: Fix pcie2x1 and pcie3x2 pinctrl override
The pcie pinctrl override added in the commit a76aa6ffa6cd ("rockchip:
rk3568-rock-3a: Enable PCIe and NVMe support") is causing a pinmux issue
on linux when using a EFI boot flow.
The pcie reset-gpios must however be configured with gpio function, or
the device will freeze running pci enum and nothing is connected.
Adjust the pinctrl override in u-boot.dtsi to fix this issue. PCIe/NVMe
continues to work in both U-Boot and linux after this change.
Also revert disable of sdmmc2 and uart1 to fix use of wifi in linux when
using a EFI boot flow.
Fixes: a76aa6ffa6cd ("rockchip: rk3568-rock-3a: Enable PCIe and NVMe support") Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Jonas Karlman [Fri, 28 Jul 2023 12:05:41 +0000 (12:05 +0000)]
rockchip: rk3588-rock-5b: Fix SPI Flash alias
The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") enabled SPI flash support by adding a spi0 alias.
Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and
SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.
Fixes: fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 12:05:40 +0000 (12:05 +0000)]
rockchip: rk3568-rock-3a: Fix SPI Flash alias
The commit 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI
NOR flash") enabled SPI flash support by overriding the spi0 alias.
Correct this by adding a new spi4 alias in rk356x-u-boot.dtsi and
SF_DEFAULT_BUS=4 and SPL_DM_SEQ_ALIAS=y in defconfig. Also enabled
support for parsing and auto discovery of parameters, SFDP.
Fixes: 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 11:38:40 +0000 (11:38 +0000)]
doc: rockchip: Update SPI flashing instruction
Update documentation on how to write a bootable u-boot-rockchip-spi.bin
image into SPI flash. This removes the reference to a hardcoded and now
obsolete 0x60000 payload offset.
Also remove an obsolete reference to pad_cat.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 11:38:38 +0000 (11:38 +0000)]
rockchip: rk3399-roc-pc: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB
Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.
Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 11:38:37 +0000 (11:38 +0000)]
rockchip: rk3399-pinephone-pro: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB
Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.
Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 11:38:35 +0000 (11:38 +0000)]
rockchip: rk3399-pinebook-pro: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB
Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.
Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash
image, u-boot-rockchip-spi.bin.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 11:38:34 +0000 (11:38 +0000)]
rockchip: rk3399-rockpro64: Fix SPL max size and SPI flash payload offset
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is
loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only
reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for
TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB
Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows
for a payload of 3168 KB before env offset start to overlap.
Also remove CONFIG_LTO=y now that there is sufficient space for SPL in
SPI flash, and to fix a build issue reported by Peter Robinson.
Fixes: 5713135ecc75 ("rockchip: rockpro64: Build u-boot-rockchip-spi.bin") Reported-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 28 Jul 2023 11:53:07 +0000 (11:53 +0000)]
rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes
Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and
UART2 that are typically used by multiple boards. Unreferenced nodes are
removed from the SPL device tree during a normal build.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Jul 2023 12:26:48 +0000 (12:26 +0000)]
board: rockchip: Add Pine64 SOQuartz on CM4-IO
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi
CM4 form factor. Therefore, it can slot into the official Raspberry Pi
CM4 IO carrier board. Add this configuration to U-Boot.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Jul 2023 12:26:47 +0000 (12:26 +0000)]
board: rockchip: Add Pine64 SOQuartz on Blade
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz
CM4-compatible compute module. It features PoE, an M.2 slot, an SD card
slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Jul 2023 12:26:45 +0000 (12:26 +0000)]
board: rockchip: Add Pine64 SOQuartz on Model A
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz
CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI,
CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Jul 2023 12:26:44 +0000 (12:26 +0000)]
board: rockchip: Add Pine64 Quartz64-B Board
The Pine64 Quartz64 Model B is a credit-card sized single-board
computer based on the Rockchip RK3566 SoC. The board features an M.2
PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a
40 pin GPIO header and a DSI and CSI port, as well as on-board Wi-Fi.
Features tested on a Quartz64-B 4GB v1.4 2022-06-06:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Jul 2023 12:26:42 +0000 (12:26 +0000)]
board: rockchip: Add Pine64 Quartz64-A Board
The Pine64 Quartz64 Model A is a single-board computer based on the
Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0,
CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a
20 pin GPIO header.
Features tested on a Quartz64-A 8GB v2.0 2021-04-27:
- SD-card boot
- eMMC boot
- PCIe/NVMe/AHCI
- USB host
Device tree is imported from linux v6.4.
Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Also use CONFIG_IS_ENABLED(USB_HOST) and change switch to if statements
to improve readability of the code.
Fixes: 446e3a205b87 ("dwc3-generic: Handle the PHYs, the clocks and the reset lines") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Marek Vasut <marex@denx.de>
Jonas Karlman [Sun, 30 Jul 2023 22:59:54 +0000 (22:59 +0000)]
Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb"
Remove regulator-boot-on prop from regulators now that the phy core has
support for phy-supply after the commit c57e0dcd9384 ("phy: add support
for phy-supply").
Commit ec107f04b619 ("rockchip: chromebook_minnie: Enable sound") and
commit 2d0c01b8f0ad ("sound: rockchip: Add sound support for jerry")
enable audio support for chromebook_minnie and chromebook_jerry. Enable
it for chromebook_speedy as well, but put the non-upstream sound node
in the board -u-boot.dtsi instead.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sound support for chromebook_jerry needs the MAX98090 codec driver. This
was enabled in commit 2d0c01b8f0ad ("sound: rockchip: Add sound support
for jerry"), but apparently lost in commit 7ae2729401bb ("configs:
Resync with savedefconfig"). Enable it again.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Commit 815ed79d8338 ("video: rockchip: Use TrueType fonts with jerry")
enables makes chromebook_jerry use TrueType fonts. Make other veyron
boards switch to it as well.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: veyron: Add serial, logging, silent console support
Commit eba768c54587 ("rockchip: jerry: Add serial support") enables
ROCKCHIP_SERIAL for chromebook_jerry to make the serial console work
correctly. Enable it also for other veyron boards.
Also enable logging and disable scrolling multiple lines at once as in
chromebook_jerry, and enable silent console as chromebook_minnie does.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288-veyron-speedy-u-boot.dtsi file duplicates the bootphase dts
fragments from rk3288-veyron-u-boot.dtsi even though it #inclues that.
Deduplicate these into the latter file, which should also make the eMMC
available to the other veyron boards' SPL.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Commit 9b312e26fc77 ("rockchip: Enable building a SPI ROM image on
jerry") produces a u-boot.rom file for chromebook_jerry, intended to be
written to SPI flash. Build this file for other veyron boards as well,
especially because they are already configured only to boot from SPI.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Commit 70e351bdfeee ("rockchip: jerry: Enable RESET driver") enables
DM_RESET for chromebook_jerry to fix its display as required by changes
to the Rockchip video drivers. Enable it for other veyron boards as
well.
configs: rockchip: drop useless DEBUG_UART_SKIP_INIT
DEBUG_UART_SKIP_INIT feature is implemented only by s5p (DEBUG_UART_S5P)
and pl01x (DEBUG_UART_PL010 or DEBUG_UART_PL011) serial drivers, but all
ARCH_ROCKCHIP configs rely on default DEBUG_UART_NS16550. The ns16550
serial driver does not depends on DEBUG_UART_SKIP_INIT, so drop it from
rockchip configs.
Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Boot devices defined in rk3308.c and in rk3308.dtsi do not match, causing
'same-as-spl' feature not to work. Update DTS definitions, aligning to
Linux kernel DTS and to other Rockchip DTS files, i.e. from dwmmc to mmc.
Add rk3308-rock-pi-s.dtb in dtb-y targets for CONFIG_ROCKCHIP_RK3308.
Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some ROCK Pi S SKU/models are not equipped with SD-NAND (eMMC),
therefore SPL needs access to sdmmc: add it to rk3308-u-boot.dtsi
with bootph-all property.
Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: rk3308: no DEBUG_UART_BOARD_INIT for ROCK Pi S
Call to board_debug_uart_init() is useless, as mainline U-Boot can
not build TPL for rk3308, and proprietary ddr.bin to be used as TPL
is responsible to init debug uart. Moreover current implementation
of board_debug_uart_init() is not compatible with ROCK Pi S, as it
sets pins for UART2 channel 1 breaking access to sdmmc due to pinmux
conflict. Debug uart for ROCK Pi S is UART0.
Thus, avoid ROCKCHIP_RK3308 to select DEBUG_UART_BOARD_INIT and allow
to deselct it in rock-pi-s-rk3308_defconfig. The DEBUG_UART_BOARD_INIT
is already implied by ARCH_ROCKCHIP, therefore other boards based on
rk3308 chip are not affected by change.
Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Definition of function board_debug_uart_init() must be under
CONFIG_DEBUG_UART_BOARD_INIT and not under CONFIG_DEBUG_UART,
as it was: see debug_uart.h. In this way the debug uart can
be used but its board-specific initialization skipped by
configuration, if useless.
Signed-off-by: Massimo Pegorer <massimo.pegorer@vimar.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
spl: CONFIG_SPL_PCI_PNP should depend on CONFIG_SPL_PCI
CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense.
Fixes: 32f5e9e5c1a7 ("nvme: pci: Enable for SPL") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 28 Jul 2023 14:25:50 +0000 (10:25 -0400)]
Merge branch '2023-07-27-TI-K2-K3-updates'
- Resync some of the K3 DTS files with the kernel, and pull in some
required related updates to keep drivers in sync with the dts files
now. Bring in some incremental fixes on top of one of the series I
applied recently as well as updating the iot2050 platform. Also do a
few small updates to the K2 platforms.
Tom Rini [Fri, 28 Jul 2023 14:13:46 +0000 (10:13 -0400)]
Merge tag 'u-boot-rockchip-20230728' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Enable pcie support for rk3568;
- Add boards:
rk3399: Radxa ROCK 4SE;
rk3328: Orange Pi R1 Plus, Orange Pi R1 Plus LTS
rk3568: FriendlyARM NanoPi R5S/R5C, Hardkernel ODROID-M1
rk3588: Edgeble Neu6B
- support OP-TEE with binman;
- support Winbond SPI flash;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
This is more complex than it needs to be and makes converting these
boards over to plain text env files more difficult. Remove setting
mtdparts as the DTS already contain the partitions. While here also
drop the conflicting definitions from the K2 defconfigs.
Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
mach-k3: security: improve the checks around authentication
The following checks are more reasonable as the previous logs were a bit
misleading as we could still get the logs that the authetication is
being skipped but still authenticate. Move the debug prints and checks
to proper locations.
This was regressed by the following commit and is required to build with
additional configs enabled.
Fixes: 14439cd71c1a ("configs: k3: make consistent bootcmd across all k3 socs") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Tested-by: Nikhil M Jain <n-jain1@ti.com>
Jan Kiszka [Thu, 27 Jul 2023 04:34:54 +0000 (06:34 +0200)]
boards: siemens: iot2050: Unify PG1 and PG2/M.2 configurations again
This avoids having to maintain to defconfigs that are 99% equivalent.
The approach is to use binman to generate two flash images,
flash-pg1.bin and flash-pg2.bin. With the help of a template dtsi, we
can avoid duplicating the common binman image definitions.
Suggested-by: Andrew Davis <afd@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Thu, 27 Jul 2023 04:34:53 +0000 (06:34 +0200)]
iot2050: Use binman in signing script
The underlying issue was fixed in the meantime. Also signing the U-Boot
proper fit image now works. Just supporting custom cert templates
remains a todo.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Thu, 27 Jul 2023 04:34:52 +0000 (06:34 +0200)]
boards: siemens: iot2050: Fix boot configuration
The common env bits now come via ti_armv7_common.env, include it.
Furthermore restore the board-specific boot targets and their ordering
that is now enforced k3-wide differently. Finally, enable
CONFIG_LEGACY_IMAGE_FORMAT explicitly which got lost while turning
FIT_SIGNATURE on by default for k3 devices.
Fixes: 53873974 ("include: armv7: Enable distroboot across all configs") Fixes: 4ae1a247 ("env: Make common bootcmd across all k3 devices") Fixes: 86fab110 ("Kconfig: Enable FIT_SIGNATURE if ARM64") Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Update the am62 and am625 device-trees from linux v6.5-rc1. This needed
the following tweaks to the u-boot specific dtsi as well:
- Switch tick-timer to the main_timer as it's now defined in the main dtsi
- Secure proxies are defined in SoC dtsi
- Drop duplicate nodes - u-boot.dtsi is includes in r5-sk, no need for
either the definitions from main.dtsi OR duplication from u-boot.dtsi
Reviewed-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Maxime Ripard <mripard@kernel.org> Tested-by: Maxime Ripard <mripard@kernel.org> Cc: Francesco Dolcini <francesco@dolcini.it> Cc: Sjoerd Simons <sjoerd@collabora.com> Cc: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Nishanth Menon <nm@ti.com>
Jonas Karlman [Sat, 22 Jul 2023 14:02:15 +0000 (14:02 +0000)]
board: rockchip: Add Hardkernel ODROID-M1
Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC,
a slightly modified version of the RK3568 SoC.
Features tested on a ODROID-M1 8GB v1.0 2022-06-13:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe/AHCI
- SATA port
- USB host
Device tree is imported from linux v6.4.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 22 Jul 2023 14:02:12 +0000 (14:02 +0000)]
ata: dwc_ahci: Fix support for other platforms
The dwc_ahci driver use platform specific defines, place the platform
specific code behind a ifdef CONFIG_ARCH_OMAP2PLUS to allow build and
use of the driver on Rockchip platform.
Fixes: 02a4b4297901 ("drivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
rockchip: px30: Define variables for compressed image support
The standard boot path expects the kernel_comp_addr_r and kernel_comp_size
variables for booting compressed kernel images. Define them using the previous
kernel_addr_c value (likely initially meant for this purpose) and usual size.
This was tested on the PX30 EVB to successfully boot compressed Linux kernel
images.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 22 Jul 2023 13:30:23 +0000 (13:30 +0000)]
rockchip: rk3568-rock-3a: Enable PCIe and NVMe support
Add missing pinctrl and defconfig options to enable PCIe and NVMe
support on Radxa ROCK 3 Model A.
Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1.
The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is
restored to the perstn pin, a workaround to avoid having to define
a new rockchip,pins.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 22 Jul 2023 13:30:21 +0000 (13:30 +0000)]
regulator: fixed: Add support for gpios prop
The commit 12df2c182ccb ("regulator: dt-bindings: fixed-regulator: allow
gpios property") in linux v6.3-rc1 added support for use of either a
gpios or gpio prop with a fixed-regulator.
This adds support for the new gpios prop to the fixed-regulator driver.
gpios prop is used by vcc3v3-pcie-regulator on Radxa ROCK 3 Model A.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jon Lin [Sat, 22 Jul 2023 13:30:20 +0000 (13:30 +0000)]
pci: pcie_dw_rockchip: Disable unused BARs of the root complex
The Root Complex BARs default to claim the full 1 GiB memory region on
RK3568, leaving no space for any attached device.
Fix this by disable the unused BAR 0 and BAR 1 of the RC.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 22 Jul 2023 13:30:18 +0000 (13:30 +0000)]
pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed
The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.
Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 22 Jul 2023 13:30:15 +0000 (13:30 +0000)]
core: read: add dev_read_addr_size_index_ptr function
Add dev_read_addr_size_index_ptr function with the same functionality as
dev_read_addr_size_index, but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some veyron boards seem to have Winbond SPI flash chips instead of
GigaDevice ones. At the very least, coreboot builds for veyron boards
have them enabled [1]. Enable support for them here as well.
[1] https://review.coreboot.org/c/coreboot/+/9719
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE
board. This board offers similar peripherals in a similar form-factor to
the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor
(which has different OPP table than the RK3399) and other minimal hardware
changes.
To prepare for ROCK 4 SE support, changes are needed to the common ROCK
Pi 4 devicetree to move the OPP from the common devicetree to individual
board devicetrees. Sync the Rockchip RK3399 ROCK Pi 4-related DTs from
Linux to gain from these changes.
Kernel tag: next-20230719
Kernel commits: cfa12c32b96f ("arm64: dts: rockchip: correct wifi interrupt flag in Rock \
Pi 4B") cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4") 2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+") fd2762a62646 ("arm64: dts: rockchip: Move OPP table from ROCK Pi 4 dtsi")
Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Alex Bee [Tue, 18 Jul 2023 14:57:14 +0000 (16:57 +0200)]
rockchip: evb_rk3229: Update/fix README
This updates the evb_rk3229's README on howto create / use the FIT image
created by binman.
Also fix some wrong paths and update filenames which have changed in recent
upstream optee-os versions.
Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Alex Bee [Tue, 18 Jul 2023 14:57:13 +0000 (16:57 +0200)]
rockchip: RK322x: Select SPL_OPTEE_IMAGE
For RK322x series ARM SoCs the OP-TEE is non-optional, as besides the TEE
it also provides the PSCI implementation, which is expected to be available
by upstream linux.
Select CONFIG_SPL_OPTEE_IMAGE if an FIT image is built.
Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Alex Bee [Tue, 18 Jul 2023 14:57:11 +0000 (16:57 +0200)]
rockchip: Support OP-TEE for ARM in FIT images created by binman
CONFIG_SPL_OPTEE_IMAGE option is used during DRAM size detection for
Rockchip ARM platform to indicate that an OP-TEE binary was already loaded
and a Trusted Execution Environment (TEE) is available in order to
block/reserve a memory-region for it.
This adds a bunch of new `#if's` to u-boot-rockchip.dtsi to include the
OP-TEE binary in the FIT image for ARM SOCs if CONFIG_SPL_OPTEE_IMAGE is
selected.
That makes it a little harder to read, but I opted for that, because all
the duplicates in an extra ARM-OP-TEE-specfic .dtsi would be the greater
evil, IMHO. Besides it's more likley being "forgotten" to sync when changes
in u-boot-rockchip.dtsi are made.
The no longer required rockchip-optee.dtsi and it's inclusions are dropped.
The hardcoded load address is common across all OP-TEE implemenations for
Rockchip (vendor and upstream).
The OP-TEE-binary is non-optional if CONFIG_SPL_OPTEE_IMAGE is selected and
there will be an error if the file does not exist and/or `TEE=` build
option is missing.
Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Johan Jonker [Thu, 22 Jun 2023 13:59:24 +0000 (15:59 +0200)]
mtd: nand: raw: rockchip_nfc: copy hwecc PA data to oob_poi buffer
Rockchip boot blocks are written per 4 x 512 byte sectors per page.
Each page must have a page address (PA) pointer in OOB to the next page.
Pages are written in a pattern depending on the NAND chip ID.
This logic used to build a page pattern table is not fully disclosed and
is not easy to fit in the MTD framework.
The formula in rk_nfc_write_page_hwecc() function is not correct.
Make hwecc and raw behavior identical.
Generate boot block page address and pattern for hwecc in user space
and copy PA data to/from the already reserved last 4 bytes before EEC
in the chip->oob_poi data layout.
Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 21 Jun 2023 16:02:53 +0000 (18:02 +0200)]
rockchip: puma: pass platform parameter to TF-A
Puma supports upstream TF-A and is configured to output serial on UART0
instead of the default UART2. Since U-Boot is properly configured to
output on UART0, let's pass the DT to TF-A so there is no need for a
custom TF-A to make the latter output to UART0 too.
Quentin Schulz [Wed, 21 Jun 2023 16:02:52 +0000 (18:02 +0200)]
rockchip: rk3399: pass platform parameter to TF-A by default for new RK3399 boards
Long are gone the times TF-A couldn't handle the FDT passed by U-Boot.
Specifically, since commit e7b586987c0a ("rockchip: don't crash if we
get an FDT we can't parse") in TF-A, failure to parse the FDT will use
the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two
years ago.
New boards should likely have this option disabled or explicitly enable
it in their respective defconfig.
Because existing boards might depend on a TF-A version that predates
v2.4, let's just enable this option in all RK3399 defconfigs.
Maintainers of each board can decide for themselves if they would prefer
to disable this option and allow U-Boot to pass the DT to TF-A.
projects / u-boot.git / log