John Schmoller [Thu, 10 Mar 2011 22:09:26 +0000 (16:09 -0600)]
mpc8[5/6]xx: Ensure POST word does not get reset
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors. When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word. To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Timeout counter value is set as DTOCV bits in SYSCTL register
For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should
cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Wed, 19 Jan 2011 23:37:33 +0000 (15:37 -0800)]
corenet_ds: pick the middle value for all tested timing parameters
For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.
York Sun [Wed, 2 Mar 2011 22:24:11 +0000 (14:24 -0800)]
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Po-Yu Chuang [Tue, 15 Feb 2011 22:54:35 +0000 (22:54 +0000)]
arm: get_sp() should always be compiled
get_sp() was incorrectly excluded if none of
CONFIG_SETUP_MEMORY_TAGS
CONFIG_CMDLINE_TAG
CONFIG_INITRD_TAG
CONFIG_SERIAL_TAG
CONFIG_REVISION_TAG
were defined.
Lei Wen [Wed, 9 Feb 2011 12:47:47 +0000 (18:17 +0530)]
Pantheon: Add Board Support for Marvell dkb board
DKB is a Development Board for PANTHEON TD/TTC(pxa920/pxa910) with
* Processor upto 806Mhz
* LPDDR1/2
* x8/x16 SLC/MLC NAND
* Footprints for eMMC & MMC x8 card
With Peripherals:
* Parallel LCD I/F
* Audio codecs (88PM8607)
* MIPI CSI-2 camera
* Marvell 88W8787 802.11n/BT module
* Marvell 2G/3G RF
* Dual analog mics & speakers, headset jack, LED, ambient
* USB2.0 HS host, OTG (mini AB)
* GPIO, GPIO expander with DIP switches for easier selection
* UART serial over USB, CIR
This patch adds basic board support with DRAM and UART functionality
Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Lei Wen [Wed, 9 Feb 2011 12:36:58 +0000 (18:06 +0530)]
ARM: Add Support for Marvell Pantheon Familiy SoCs
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
Lei Wen [Wed, 9 Feb 2011 12:36:58 +0000 (18:06 +0530)]
mv: seperate kirkwood and armada from common setting
Since there are lots of difference between kirkwood and armada series,
it is better to seperate them but still keep the most common file
shared by all marvell platform in the mv-common configure file.
This patch move the kirkwood only driver definitoin in mv-common to
the <soc_name>/config.h.
This patch is tested with compilation for armada100 and guruplug.
Wolfgang Denk [Fri, 11 Feb 2011 12:25:48 +0000 (12:25 +0000)]
ARM: fix write*() I/O accessors
Commit 3c0659b "ARM: Avoid compiler optimization for readb, writeb
and friends." introduced I/O accessors with memory barriers.
Unfortunately the new write*() accessors introduced a bug:
The problem is that the argument "v" gets evaluated twice. This
breaks code like used here (from "drivers/net/dnet.c"):
for (i = 0; i < wrsz; i++)
writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
Use auxiliary variables to avoid such problems.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Alexander Holler <holler@ahsoftware.de> Cc: Dirk Behme <dirk.behme@googlemail.com>
Vitaly Kuzmichev [Fri, 11 Feb 2011 15:18:31 +0000 (18:18 +0300)]
USB-CDC: handle interrupt after dropped pullup
Disconnecting USB gadget with pending interrupt may cause its wrong
handling in the next time when interface will be started again
(especially actual for RNDIS). This interrupt may force the gadget
to queue unexpected response before setup stage.
Despite the fact that such interrupt handled after dropped pullup
also may add pending response, this will not bring to any issues due to
usb_ep_disable (which clears the queue) called on gadget unregistering.
Simon Glass [Wed, 16 Feb 2011 19:14:33 +0000 (11:14 -0800)]
Add USB host ethernet adapter support
This adds support for using USB Ethernet dongles in host mode. This is just
the framework - drivers will come later. A new config option called
CONFIG_USB_HOST_ETHER can be defined in board config files to switch this
on.
The was originally written by NVIDIA and was cleaned up for release by the
Chromium authors.
Wolfgang Denk [Fri, 11 Feb 2011 19:20:51 +0000 (20:20 +0100)]
unzip: return uncompressed size in `filesize', and print it.
The unzip command did not provide a way for the caller to get any
information about the uncompressed size. To make it better usable in
scripts, we now store the uncompressed size in the `filesize'
variable, like we do when for example loading a file over the network
or when reading it from a file system. Following that analogy, it is
only consequent to also print the size.
Wolfgang Denk [Tue, 8 Feb 2011 15:56:05 +0000 (16:56 +0100)]
itest: fix result of string compares
The implementation of the string compare function of the "itest"
command was weird, as only the length of the shortest argument was
included in the compare, with the result that something like
"itest.s abd == abddef" would return TRUE. Fix this.
Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
Graeme Russ [Sat, 12 Feb 2011 04:11:33 +0000 (15:11 +1100)]
x86: Call early_board_init when warm booting
early_board_init has been skipped to avoid SDRAM corruption in the case
that a fully relocatable image has been loaded into SDRAM and is being
executed from SDRAM. x86 is being aligned with other architectures (ARM
and PPC in particlar) and will be using Cache-As-RAM to run a C
environment from Flash (or SRAM if you have some). early_board_init may
be needed to assist in the setup of Cache-As-RAM and the early C
environment
Graeme Russ [Sat, 12 Feb 2011 04:11:22 +0000 (15:11 +1100)]
eNET: Create distinct board configurations
Position independant functionality is due for removal from the x86
architecture, so create two distinct configurations - One for Flash and
one for SRAM
York Sun [Thu, 10 Feb 2011 18:13:10 +0000 (10:13 -0800)]
powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3
When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Wed, 9 Feb 2011 19:40:51 +0000 (13:40 -0600)]
fsl: update CRC after setting EEPROM identifier
The "mac id" command is used to initialize the EEPROM data to a specific
format, but it was not updating the CRC. This didn't cause any real
problems, because writing the data to the EEPROM will always update the
CRC anyway, but it did result in a bogus CRC warning.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Dirk Eibach [Fri, 21 Jan 2011 08:31:21 +0000 (09:31 +0100)]
ppc4xx: Add DLVision-10G board support
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.
Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Joakim Tjernlund [Thu, 27 Jan 2011 15:30:54 +0000 (16:30 +0100)]
mpc83xx: Use correct register to calculate clocks.
Use SPMR instead of HRCWL when calculating clocks as HCRWL
may be changed and the CPU will not pick up all changes
until there is a POR. u-boot will think SPMF has changed and get
the clocks wrong.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
projects / u-boot.git / log