Tom Rini [Fri, 9 Apr 2021 17:10:59 +0000 (13:10 -0400)]
Merge tag 'u-boot-stm32-20210409' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
Marek Vasut [Wed, 31 Mar 2021 12:15:09 +0000 (14:15 +0200)]
arm: stm32mp1: Set soc_type, soc_pkg, soc_rev env variables
Split up get_soc_name(), clean the decoding up a bit, and set up
environment variables which contain the SoC type, package, revision.
This is useful on SoMs, where multiple SoC options are populated.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
A now removed comment promises to "limit SYSRAM usage to first 128 KB".
This would imply that only SYSRAM from 0x2ffc0000 - 0x2ffe0000 would be
used. This is not what happens at all.
First, SPL_MAX_SIZE is referenced from SPL_TEXT_BASE, which on all
existing configs is set to 0x2ffc2500, not SYSRAM_BASE (0x2ffc0000).
Some of it is in the first 128 KiB and some of it is in the second
128 KiB chunk of SYSRAM.
Second, SPL_MAX_SIZE, does not restrict the BSS size. While a valiant
attempt is made via SPL_BSS_MAX_SIZE, the value of 0x00100000 is much
larger than SYSRAM, and doesn't account for the non-BSS sections.
Because we're putting the .text and .bss in the same boat, the correct
way to limit them together is via SPL_MAX_FOOTPRINT. With the current
SPL_TEXT_BASE, we couldn't limit even a very basic SPL to the first
128 KiB, and there is no technical reason to do so. Because of this,
simply allow the SPL to use all SYSRAM.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
CONFIG_SPL_BSS_START_ADDR is only used on a few mach- linker scripts.
stm32mp1 uses the generic script under arch/arm/cpu/u-boot-spl.lds,
which does not make use of this definition.
The SPL BSS starts in SRAM, right after .text, .rodata, .data, and
.u_boot_list. A very short version of the STM32MP1 memory map is:
* SYSRAM: 2ffc0000 - 30000000 <- all of SPL is here
* DRAM: c0000000+
0xC0200000 is a DRAM address, and has nothing to do with SPL. It is
just very misleading to have it next to CONFIG_SPL_BSS_MAX_SIZE, or to
have it at all.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Since commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for
loading images"), FIT images must be malloc()'d before being loaded.
The old size of 1 MiB is suitable for FIT images with u-boot and an
FDT, but something containing a linux kernel is almost sure to fail.
It's safe to extend malloc all the way to 0xc2000000, but no further.
Linux likes to be loaded at 0xc2000000, so we use that as our cutoff
point. This gives us 29 MiB of malloc() space, which suited for more
complex FIT images including several DTBs, kernel, and OP-TEE images.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
stm32mp1: remove the board_check_usb_power function when ADC is not activated
Simplify the code of the function board_check_usb_power
based in CONFIG_ADC and adc_measurement; the function is removed by the
linker when the CONFIG_ADC is not activated.
stm32mp: update uart number in trace of serial device not found
Align the uart number in the trace of setup_boot_mode() with the name of
the uart/usart device (start at 1) and not with the instance value
(start at 0), i.e. the serial device sequence number and the index in
serial_addr[].
Fixes: f49eb16c17e2c ("stm32mp: stm32prog: replace alias by serial
device sequence number")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Jagan Teki [Tue, 16 Mar 2021 16:22:07 +0000 (21:52 +0530)]
board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.
MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.
Jagan Teki [Tue, 16 Mar 2021 16:22:00 +0000 (21:52 +0530)]
ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features
i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating complete platform solutions.
dillon min [Fri, 9 Apr 2021 07:28:44 +0000 (15:28 +0800)]
ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
This patchset has following changes:
- introduce stm32h750.dtsi to support stm32h750 value line
- add pin groups for usart3/uart4/spi1/sdmmc2
- add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile)
- add stm32h750i-art-pi.dts to support art-pi board
- add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot)
dillon min [Fri, 9 Apr 2021 07:28:41 +0000 (15:28 +0800)]
ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750
This patch is intend to add support stm32h750 value line,
just add stm32h7-pinctrl.dtsi for extending, with following changes:
- rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
- move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi
- update stm32h743i-{disco, eval}.dts to include stm32h7-pinctrl.dtsi
Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
dillon min [Fri, 9 Apr 2021 07:28:40 +0000 (15:28 +0800)]
ARM: dts: stm32: split sdram pin & timing parameter into specific board dts
As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.
Signed-off-by: dillon min <dillon.minfei@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Max Krummenacher [Thu, 11 Mar 2021 17:18:07 +0000 (18:18 +0100)]
imx: bootaux fix elf loading
This reverts the arch/arm/mach-imx/imx_bootaux.c changes of commit 805b3cac1e0c. The loader function name was changed so that it does
not clash with the generically available function in lib/elf.c.
imx-bootaux loads an elf file linked for an auxilary core. Thus the
loader function requires address translation from the auxilary core's
address space to where those are mapped into U-Boot's address space.
So the elf loader is specific and must not be replaced with a generic
loader which doesn't provide the address translation functionality.
Fixes commit 805b3cac1e0c ("lib: elf: Move the generic elf
loading/validating functions to lib")
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Haibo Chen [Mon, 22 Mar 2021 10:55:38 +0000 (18:55 +0800)]
mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessary
Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need
around 18ms, common code only delay 10ms, so need to delay extra 8ms.
Otherwise voltage switch will timeout when wait for data0 line.
This IO voltage switch time depends on board design, depend on the
PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF
capacitance.
Marek Vasut [Thu, 25 Mar 2021 00:20:48 +0000 (01:20 +0100)]
doc: imx: psb: Document usage of SRC_GPR10 PERSIST_SECONDARY_BOOT for A/B switching
Document SRC_GPR10 PERSIST_SECONDARY_BOOT functionality. This is useful for
reliable bootloader A/B updates, as it permits switching between two copies
of bootloader at different offsets of the same storage. The switch happens
in case one copy is corrupted OR can be enforced by user. This functionality
is present at least since i.MX53, however is poorly documented in all known
SoC datasheets, hence this document aims to clarify the usage, currently on
i.MX7D and i.MX8MM.
Signed-off-by: Marek Vasut <marex@denx.de> # Original MX7D work, this document Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> # All the MX8M work Cc: Christoph Niedermaier <cniedermaier@dh-electronics.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Harald Seiler <hws@denx.de> Cc: Igor Opaniuk <igor.opaniuk@foundries.io> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Ludwig Zenz <lzenz@dh-electronics.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Niel Fourie [Mon, 22 Mar 2021 13:05:11 +0000 (14:05 +0100)]
ARM: pcm058: Match mainline Linux NAND ECC layout/behaviour
Enabled "fsl,legacy-bch-geometry" in U-Boot device tree overlay
to match the legacy BCH geometry layout, which mainline Linux
applies when "fsl,use-minimum-ecc" is not specified in the device
tree.
Reinstated SYS_NAND_ONFI_DETECTION, which when disabled, masked
the mismatch on SOMs with Winbond NAND flash chips.
Haibo Chen [Wed, 3 Mar 2021 09:05:46 +0000 (17:05 +0800)]
mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.
board: st: stm32f746-disco: fix console is not enabled while init dram
While initializing dram in spl_dram_init(), mdelay() is called that in
order calls get_ticks() that verifies if timer exists, if doesn't, it
throws a panic(), but since preloader_console_init() has still not been
called those panic()s will fail. This doesn't help debugging, so let's
setup console before calling spl_dram_init() by moving it after
spl_dram_init().
board: freescale: imxrt1050-evk: fix console is not enabled while init dram
While initializing dram in spl_dram_init(), mdelay() is called that in
order calls get_ticks() that verifies if timer exists, if doesn't, it
throws a panic(), but since preloader_console_init() has still not been
called those panic()s will fail. This doesn't help debugging, so let's
setup console before calling spl_dram_init() by moving it after
spl_dram_init().
board: freescale: imxrt1020-evk: fix console is not enabled while init dram
While initializing dram in spl_dram_init(), mdelay() is called that in
order calls get_ticks() that verifies if timer exists, if doesn't, it
throws a panic(), but since preloader_console_init() has still not been
called those panic()s will fail. This doesn't help debugging, so let's
setup console before calling spl_dram_init() by moving it after
spl_dram_init().
Since Toradex provides the full set of overlays for Linux kernel
for display interfaces for both Apalis iMX6Q and Colibri iMX6DL
modules, the video= settings are obsolete. Remove them.
commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images")'
changed the way buffer allocation worked for SPL to a more flexible
method.
For venice this caused breakage that is resolved by increasing the size
of CONFIG_SYS_SPL_MALLOC_SIZE as the current FIT slighly exceeds 512KiB.
Additionally remove the unnecessary comment on CONFIG_SPL_BSS_MAX_SIZE
and CONFIG_SYS_SPL_MALLOC_SIZE as the size is obvious from the define.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tim Harvey [Mon, 1 Mar 2021 22:33:35 +0000 (14:33 -0800)]
imx: ventana: enable dm support for MMC and SATA
Enable driver model support for MMC and SATA.
Note that DM_MMC requires aliases for your mmc devices so
they are added to the dts. Linux does not support enumerating mmc
devices by alias so these are not present in the Linux dts.
Note that we still need board_mmc_init() and board_mmc_getcd() for
not DM SPL to support MMC.
Tim Harvey [Mon, 1 Mar 2021 22:33:34 +0000 (14:33 -0800)]
imx: ventana: enable dm support for USB
Enable dm support for USB (which also requires dm support for fixed
regulators used for vbus enable) and remove usb iomux which is no
longer needed.
We can remove the handling of otgpwr_en gpio as this is defined in
dt as usbotg vbus-supply but we need to keep the handling of
USB_HUB_RST# for boards that have a USB HUB as that isn't defined in
the dt's currently.
Tim Harvey [Mon, 1 Mar 2021 22:33:31 +0000 (14:33 -0800)]
arm: dts: imx6qdl-gw*: add dr_mode prop to dt to avoid error
The fsl-usb dt bindings in Linux default dr_mode to 'host' for
backward compatibility however U-Boot prints an error if
this property does not exist. Declare it in the Gateworks
Ventana device-trees to avoid the error.
Tim Harvey [Mon, 1 Mar 2021 22:33:28 +0000 (14:33 -0800)]
spl: fit: nand: allow for non-page-aligned elements
Add a weak nand_get_mtd function for nand drivers to provide mtd info
and use this to set pagesize such that reading of non page-aligned
elements can succeed.
The spl_load_simple_fit already handles block block access so all we
need to do is provide the nand writesize as the block length.
Further cleanup of the drivers which use nand_spl_loaders.c such as
am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done
using info from mtd_info instead of statically defined details.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tim Harvey [Mon, 1 Mar 2021 22:33:27 +0000 (14:33 -0800)]
spl: fit: nand: skip bad block handling if NAND chip not fully defined
commit 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks")
added support for adjusting the image offset to account for bad blocks.
However this requires nand_spl_adjust_offset() which requires fully defined
specifics of the NAND chip being used may not be avialable.
Allow skipping this support for drivers or configs which don't specify
the NAND chip details statically with defines.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Ye Li [Thu, 25 Mar 2021 09:30:36 +0000 (17:30 +0800)]
crypto: fsl: refactor for 32 bit version CAAM support on ARM64
Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit
for i.MX8M" breaks the 64 bits CAAM.
Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64),
to adapt and not break 64 bits CAAM support, add a new config
CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t".
This config is default enabled when CONFIG_PHYS_64BIT is set except
for iMX8M.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Clement Faure [Thu, 25 Mar 2021 09:30:33 +0000 (17:30 +0800)]
imx8m: Add DEK blob encapsulation for imx8m
Add DEK blob encapsulation support for IMX8M through "dek_blob" command.
On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob
for encrypted boot.
The DEK blob is encapsulated by OP-TEE through a trusted application call.
U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE
dynamic shared memory.
To enable the DEK blob encapsulation, add to the defconfig:
CONFIG_SECURE_BOOT=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_DEKBLOB=y
Signed-off-by: Clement Faure <clement.faure@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3
It is highly recommended to set the PRIBLOB bitfield to 0x3 once your
encrypted boot image has booted up, this prevents the generation of new
blobs that can be used to decrypt an encrypted boot image. The PRIBLOB is
a sticky type bit and cannot be changed until the next power on reset.
Add the set_priblob_bitfield U-Boot command to prevent the generation of
new blobs.
Signed-off-by: Clement Le Marquis <clement.lemarquis@nxp.com> Acked-by: Ye Li <Ye.Li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
- Add Armada 38x RTC driver (Marek)
- turris_omnia: Misc updates (enable RTC and other cmds) (Marek)
- ds414: Misc updates (enable XHCI_PCI USB support etc) (Phil)
- Convert MVEBU MMC driver to DM (Harm)
- kirkwood: Misc updates and cleanups to some boards (Harm)
arm: socfpga: Enable FIT signature with crc32 for SOC64 devices
Add signature with crc32 value for all images in binman node for FIT
image in device tree. And, enable FIT signature checking for Stratix10
and Agilex ATF and VAB sdmmc boot.
arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
Rearrange sequence of macros in handoff_soc64.h without any functionality
change. In preparation for Stratix10 and Agilex handoff function
restructuring.
projects / u-boot.git / log