arm64: versal: Add octal spi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a
smaller footprint from on chip memory(OCM). This configuration has
required CONFIG's enabled to support octal spi flash and uses DCC terminal
for console output. Add required dts for octal spi flash mini u-boot
configuration.
spi: cadence-qspi: Fix compilation error in mini u-boot flash reset
When cadence_qspi_versal_flash_reset() function is called in mini
u-boot where there is no firmware support, it is missing defines for
macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with
already define macro's which have same values as these.
arm64: versal: Add qspi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a
smaller footprint from on chip memory(OCM). This configuration has
required CONFIG's enabled to support qspi flash and uses DCC terminal
for console output. Add required dts files for qspi mini configuration.
Add soc_xilinx_versal_net driver to identify the family & revision of
versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to
enable/disable this driver. To enable this driver by default, add this
config to xilinx_versal_net_virt_defconfig file. This driver will be
probed using platdata U_BOOT_DEVICE structure which is specified in
mach-versal-net/cpu.c.
Michal Simek [Wed, 16 Nov 2022 10:59:19 +0000 (11:59 +0100)]
arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106
zcu106 also connects ethernet phy reset via tca6416 chip as is done on
other evaluation boards. That's why describe this connection to make sure
that ethernet phy is reset before it's use.
Michal Simek [Sun, 6 Nov 2022 19:48:06 +0000 (11:48 -0800)]
xilinx: versal-net: Fix SYS_LOAD_ADDR to point to OCM
Versal NET mini U-Boot configuration is used for memory testing that's why
load address can't be really placed in memory which doesn't need to work
that's why move it to start of OCM which is the same memory which U-Boot is
running from.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Michal Simek [Tue, 1 Nov 2022 00:08:44 +0000 (17:08 -0700)]
net: phy: Fix ethernet-phy-id <dot> in the code
Use dot instead of comma. The fix doesn't affect anything but it is good to
be aligned with used pattern. The first is used only for string size
calculation and the second change is in the comment.
Fixes: db681d4929ca ("net: phy: Add new read ethernet phy id function") Signed-off-by: Michal Simek <michal.simek@amd.com>
Ovidiu Panait [Wed, 12 Oct 2022 05:36:56 +0000 (08:36 +0300)]
timer: xilinx-timer: use timer_conv_64() to fix timer wrap around
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver") Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
On systems with older PMUFW using these pinctrl properties can cause system
hang because there is missing feature autodetection.
When it is implemented support for these two properties should go back.
Michal Simek [Wed, 12 Oct 2022 09:35:30 +0000 (11:35 +0200)]
arm64: zynqmp: Disable watchdog by default for virt platform
Disable watchdog based on request in past that not all Linux rootfs have
proper utilities ready to service it. Enable it if your rootfs have proper
watchdog handling.
T Karthik Reddy [Wed, 12 Oct 2022 09:03:45 +0000 (11:03 +0200)]
microblaze: Make extended addressing support default
Axi qspi controller supports 32-bit & 24-bit addressing modes
for micron, macronix & spansion flash parts. But for winbond
flashes it only supports 24-bit addressing mode.
Enable CONFIG_SPI_FLASH_BAR to use extended addressing mode
to make 32-bit addressing mode work on all flashes.
Samuel Holland [Mon, 31 Oct 2022 04:26:19 +0000 (23:26 -0500)]
spl: Fix SPL_ATF and SPL_OPENSBI dependencies
The code for these two options depends on having the FIT loadables
recorded in the FDT. Thus, these options require the full version of
the SPL_LOAD_FIT code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
DFU implementation does not bound the length field in USB
DFU download setup packets, and it does not verify that
the transfer direction. Fixing the length and transfer
direction.
CVE-2022-2347
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Marek Vasut <marex@denx.de>
Pali Rohár [Sun, 20 Nov 2022 16:56:28 +0000 (17:56 +0100)]
Nokia RX-51: Do not overwrite standard $loadaddr variable
Instead of overwriting $loadaddr variable, use custom temporary
$fileloadaddr variable. So scripts can access default/original address
stored in $loadaddr at build time.
Pali Rohár [Sun, 20 Nov 2022 16:56:26 +0000 (17:56 +0100)]
arm32: Fix relocation of env_addr if POSITION_INDEPENDENT=y
Apply commit 534f0fbd6520 ("arm64: Fix relocation of env_addr if
POSITION_INDEPENDENT=y") also for 32-bit ARM.
This change fixes crashing of U-Boot on ARMv7 (Omap3 / Cortex-A8) Nokia N900
phone (real HW). Note that qemu emulator of this board with same u-boot.bin
binary has not triggered this crash.
Crash happened after U-Boot printed following debug lines to serial console:
initcall: 0001ea8c (relocated to 8fe0aa8c)
Loading Environment from <NULL>... Using default environment
Destroy Hash Table: 8fe25a98 table = 00000000
Create Hash Table: N=387
Due to usage of PREBOOT in Kconfig, macro CONFIG_PREBOOT is always defined
when CONFIG_USE_PREBOOT is enabled. In case CONFIG_PREBOOT is not
explicitly enabled it is set to empty C string and therefore
'#ifdef CONFIG_PREBOOT' guard does not work. Fix this issue by introducing
a new Kconfig symbol PREBOOT_DEFINED which cause to define new C macro
CONFIG_PREBOOT_DEFINED only when CONFIG_PREBOOT is really defined.
Change usage of '#ifdef CONFIG_PREBOOT' by '#ifdef CONFIG_USE_PREBOOT' for
code which checks if preboot code would be called and by
'#ifdef CONFIG_PREBOOT_DEFINED' for defining preboot code.
- Fix and improve microchip's clock driver to allow sync'ing DTS with linux
- Improve the help message in "SBI_V02" Kconfig
- Improve DTS property "isa-string" parsing rule
Ilias Apalodimas [Fri, 11 Nov 2022 18:04:31 +0000 (20:04 +0200)]
efi_loader: replace a u16_strdup with alloc + memcpy
Heinrich reports that on RISC-V unaligned access is emulated by OpenSBI
which is very slow. Performance wise it's better if we skip the calls
to u16_strdup() -- which in turn calls u16_strsize() and just allocate/copy the
memory directly. The access to dp.length may still be unaligned, but that's
way less than what u16_strsize() would do
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Use malloc() instead of calloc(). Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Ilias Apalodimas [Thu, 10 Nov 2022 13:31:30 +0000 (15:31 +0200)]
efi_loader: add comments on efi_file_from_path() regarding alignment
UEFI specification requires pointers that are passed to protocol member
functions to be aligned. There's a u16_strdup in that function which
doesn't make sense otherwise Add a comment so no one removes it
accidentally
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Ilias Apalodimas [Thu, 10 Nov 2022 08:21:24 +0000 (10:21 +0200)]
efi_loader: initialize return values in efi_uninstall_multiple_protocol_interfaces_int()
If the va_list we got handed over contains no protocols we must return
EFI_SUCCESS. However in that case the current code just returns
an unintialized value.
Fix that by setting the return value in the variable definition
Quentin Schulz [Mon, 7 Nov 2022 13:49:31 +0000 (14:49 +0100)]
doc: fix build with sphinx 5.0 and later.
Sphinx 5.0 and later fails to build when language is set to None:
Warning, treated as error:
Invalid configuration value found: 'language = None'. Update your configuration to a valid langauge code. Falling back to 'en' (English)
Let's set the language to English since it is the language used for the
documentation.
Correct GD_FLG_CYCLIC_RUNNING documentation to match Sphinx style.
Fixes: d7de5ef62935 ("cyclic: use a flag in gd->flags for recursion protection") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
riscv: Fix detecting FPU support in standard extension
We should check the string until it hits underscore, in case it
searches multi-letter extensions. For example, "rv64imac_xandes"
will be treated as D extension support since there is a "d" in
"andes", resulting illegal instruction caused by initializing FCSR.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
Conor Dooley [Tue, 25 Oct 2022 07:58:49 +0000 (08:58 +0100)]
riscv: dts: fix the mpfs's reference clock frequency
The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.
Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Conor Dooley [Tue, 25 Oct 2022 07:58:48 +0000 (08:58 +0100)]
clk: microchip: mpfs: fix criticality of peripheral clocks
Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.
Conor Dooley [Tue, 25 Oct 2022 07:58:47 +0000 (08:58 +0100)]
clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.
As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.
Conor Dooley [Tue, 25 Oct 2022 07:58:45 +0000 (08:58 +0100)]
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.
Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.
Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.
The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.
Conor Dooley [Tue, 25 Oct 2022 07:58:44 +0000 (08:58 +0100)]
dt-bindings: clk: add missing clk ids for microchip mpfs
When this binding header was initally upstreamed, the PLL clocking the
microprocessor subsystem (MSS) and the RTC reference clocks were
omitted. Add them now, matching the IDs used in Linux.
Conor Dooley [Wed, 26 Oct 2022 07:49:19 +0000 (08:49 +0100)]
i2c: microchip: fix erroneous late ack send
A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.
Conor Dooley [Wed, 26 Oct 2022 07:49:18 +0000 (08:49 +0100)]
i2c: microchip: fix ack sending logic
"Master receive mode" was not correctly sending ACKs/NACKs in the
interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED &
M_RX_DATA_NACKED in line with the Linux driver.
Tom Rini [Sat, 29 Oct 2022 00:27:10 +0000 (20:27 -0400)]
Convert CONFIG_SYS_NONCACHED_MEMORY to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_NONCACHED_MEMORY
To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to
gate if we are going to have noncached_... functions available and then
continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said
cache. We make this new option depend on both the architectures which
implement support and the drivers which make use of it.
Cc: Tom Warren <twarren@nvidia.com> Cc: Mingming lee <mingming.lee@mediatek.com> Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:07 +0000 (20:27 -0400)]
Convert CONFIG_SYS_MONITOR_LEN to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MONITOR_LEN
To do this, we set a default of 0 for everyone because there are a
number of cases where we define CONFIG_SYS_MONITOR_LEN but the only
impact is that we set TOTAL_MALLOC_LEN to be CONFIG_SYS_MALLOC_LEN +
CONFIG_ENV_SIZE, so we must continue to allow all boards to set this
value. Update the SPL code to use 200 KB as the default raw U-Boot size
directly, if we don't have a real CONFIG_SYS_MONITOR_LEN value.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:02 +0000 (20:27 -0400)]
Convert CONFIG_SYS_LOADS_BAUD_CHANGE et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_LOADS_ECHO
As part of this, we move CMD_SAVES to be after CMD_LOADS as they are
logically related (load or save an s-record format file) and this makes
grouping of CONFIG_SYS_LOADS_BAUD_CHANGE easier.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:59 +0000 (20:26 -0400)]
fs: jffs2: Move SYS_JFFS2_SORT_FRAGMENTS to Kconfig
Move the symbol SYS_JFFS2_SORT_FRAGMENTS to Kconfig and use the only
remaining part of doc/README.JFFS2 that is still relevant and useful to
the help for this option.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:58 +0000 (20:26 -0400)]
Remove unused symbols CONFIG_SYS_JFFS2_FIRST_BANK et al
This removes the following symbols:
CONFIG_RTC_MCFRRTC
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LIME_SIZE
CONFIG_SYS_MAMR
CONFIG_SYS_MCFRRTC_BASE
CONFIG_SYS_MONITOR_SEC
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Fabio Estevam [Fri, 4 Nov 2022 11:12:54 +0000 (08:12 -0300)]
wandboard: Pass mmc aliases
Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi.
After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a regression in which the SD card cannot be found anymore:
Since commit the aliases node has been removed
U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300)
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
Core: 62 devices, 17 uclasses, devicetree: separate
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the SD card (esdhc3) was
mapped to mmc0.
Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 13:43:41 +0000 (08:43 -0500)]
configs: imx8mn_beacon: Re-align memory to standard imx8mn settings
The imx8mn_beacon board does not use the same memory map as the reference
design from NXP or other imx8mn boards. As such, memory is more limited
in SPL.
Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases
the amount of available meory for the SPL stack. Doing this allows
the board to no longer define CONFIG_MALLOC_F_ADDR.
Since SYS_LOAD_ADDR also does not align with other boards, move it too.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
projects / u-boot.git / log