Pavel Machek [Tue, 7 Jun 2016 10:37:23 +0000 (12:37 +0200)]
ARM: socfpga: add support for IS1 board
This adds support for IS1 board. Pretty usual socfpga board,
256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two
additional ethernet ports connected to the FPGA.
Andre Przywara [Tue, 31 May 2016 17:45:06 +0000 (10:45 -0700)]
arm/arm64: implement a boot header capability
Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.
Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
.space 1000
.word 0x12345678
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Steve Rae <srae@broadcom.com>
Commit Notes:
Please note that the current code:
start.S (arm64) and
vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).
For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.
[1] https://github.com/apritzel/pine64/tree/master/tools
END Reviewed-by: Tom Rini <trini@konsulko.com>
Chris Packham [Tue, 31 May 2016 08:30:59 +0000 (20:30 +1200)]
lib: make strmhz available in SPL
When setting up a DDR controller it is useful to be able to display
frequencies in a readable form. Make the strmhz() function available in
SPL builds provided there is full vsprintf available.
Reviewed-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com>
Alexander Graf [Fri, 27 May 2016 10:25:03 +0000 (12:25 +0200)]
efi_loader: Don't allocate from memory holes
When a payload calls our memory allocator with the exact address hint, we
happily allocate memory from completely unpopulated regions. Payloads however
expect this to only succeed if they would be allocating from free conventional
memory.
This patch makes the logic behind those checks a bit more obvious and ensures
that we always allocate from known good free conventional memory regions if we
want to allocate ram.
Reported-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 2 Jun 2016 09:38:27 +0000 (11:38 +0200)]
efi_loader: Move to normal debug infrastructure
We introduced special "DEBUG_EFI" defines when the efi loader
support was new. After giving it a bit of thought, turns out
we really didn't have to - the normal #define DEBUG infrastructure
works well enough for efi loader as well.
So this patch switches to the common debug() and #define DEBUG
way of printing debug information.
Alexander Graf [Fri, 20 May 2016 21:28:23 +0000 (23:28 +0200)]
efi_loader: Add exit support
Some times you may want to exit an EFI payload again, for example
to default boot into a PXE installation and decide that you would
rather want to boot from the local disk instead.
This patch adds exit functionality to the EFI implementation, allowing
EFI payloads to exit.
Alexander Graf [Fri, 20 May 2016 21:28:22 +0000 (23:28 +0200)]
arm: Introduce setjmp/longjmp
To quit an EFI application we will need logic to jump to the caller
of a function without returning from the function we called into,
so we need setjmp/longjmp functionality.
This patch introduces a trivial implementation of these that I
verified works on armv7, thumb2 and aarch64.
Ed Swarthout [Wed, 1 Jun 2016 13:11:24 +0000 (08:11 -0500)]
dm: scsi: if_typename should be scsi
Fixes:
=> ext2ls scsi 0:1
** Bad device scsi 0:1 **
for boards which use the scsi legacy driver (such as ls1043ardb).
Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Tested-by: George McCollister <george.mccollister@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 22 Apr 2016 12:28:54 +0000 (14:28 +0200)]
ARM64: zynqmp: Add support for standard distro boot commands
Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.
Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 1 Jun 2016 20:41:54 +0000 (22:41 +0200)]
ARM64: zynqmp: Remove CONFIG_BOOTP_SERVERIP
When the CONFIG_BOOTP_SERVERIP option is set, we ignore all
dhcp values for the tftp server and use our own serverip and
file name instead.
This is usually not what we want and I doubt it's set for a
good reason on ZynqMP. It definitely hurts if we want to support
uEFI PXE boot on it. So just remove the option for now.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When no DTB can be matched successfully to the board that's being used
a list of available FIT-embedded DTBs will be output to the console for
diagnostic purposes. But rather than the contents of the "description"
FDT property a non-existent property was accessed and as a result "NULL"
was output instead of the actual name(s) of the DTB(s). Fix this issue
by using the correct property which is also the exact same property
that's used earlier during the actual board matching process.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Certain GPIO devices have the capability to switch their GPIOs into
open-drain mode, that is, instead of actively driving the output
(Push-pull output), the pin is connected to the collector (for a NPN
transistor) or the drain (for a MOSFET) of a transistor, respectively.
The pin then either forms an open circuit or a connection to ground,
depending on the state of the transistor.
This patch adds functions to the GPIO uclass to switch GPIOs to
open-drain mode on devices that support it.
Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).
The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.
The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.
Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
Max Krummenacher [Mon, 30 May 2016 14:28:28 +0000 (16:28 +0200)]
nand: fix nand torture to use changed mtd api
The mtd subsystem deprecated and renamed the direct use of the mtd_info
struct's functionpointers. Instead the corresponding mtd_xxx function
should be used.
Scott Wood [Mon, 30 May 2016 18:57:58 +0000 (13:57 -0500)]
mtd: nand: Sync with Linux v4.6
Updates the NAND code to match Linux v4.6. The previous sync was from
Linux v4.1 in commit d3963721d93fafa.
Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.
Signed-off-by: Scott Wood <oss@buserror.net> Tested-by: Heiko Schocher <hs@denx.de>
Scott Wood [Mon, 30 May 2016 18:57:57 +0000 (13:57 -0500)]
mtd: nand: Add page argument to write_page() etc.
This change is part of the Linux 4.6 sync. It is being done before the
main sync patch in order to make it easier to address the issue across
all NAND drivers (many/most of which do not closely track their Linux
counterparts) separately from other merge issues.
Scott Wood [Mon, 30 May 2016 18:57:56 +0000 (13:57 -0500)]
mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data
These functions are part of the Linux 4.6 sync. They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.
Scott Wood [Mon, 30 May 2016 18:57:55 +0000 (13:57 -0500)]
nand: Embed mtd_info in struct nand_chip
nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Scott Wood [Mon, 30 May 2016 18:57:53 +0000 (13:57 -0500)]
mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only
user of the docg4 driver and the palmtreo680 image flashing tool. This
patch removes them.
Signed-off-by: Scott Wood <oss@buserror.net> Cc: Mike Dunn <mikedunn@newsguy.com> Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Mon, 30 May 2016 18:57:52 +0000 (13:57 -0500)]
mtd: nand: Remove jz4740 driver
This driver is not used by anyone, remove it.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Scott Wood <oss@buserror.net> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Scott Wood <oss@buserror.net>
Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Fri, 3 Jun 2016 22:35:03 +0000 (07:35 +0900)]
usb: move CONFIG_USB_XHCI to Kconfig with renaming
Move CONFIG_USB_XHCI to defconfig files for all boards, renaming it
into CONFIG_USB_XHCI_HCD.
As commented in the help of "config USB_XHCI" entry, this has been
a TODO for a long time; now CONFIG_USB_XHCI_HCD and CONFIG_USB_XHCI
have been unified in favor of the former.
Note:
Some boards define CONFIG_USB_XHCI in their headers without
CONFIG_USB, which does not meet the "depends on" in Kconfig.
I added CONFIG_USB=y for those boards when converting.
Otherwise, they would fail to build.
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Wed, 25 May 2016 08:15:00 +0000 (16:15 +0800)]
driver/ddr/fsl: Check condition for erratum A-009803
Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
pcie/layerscape: fix bug in bus number computation when setting msi-map
When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.
The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose->first_busno, so that has to be
subtracted from the PCI device id.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Acked-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Thu, 19 May 2016 04:11:19 +0000 (21:11 -0700)]
drivers/ddr/fsl: Fix timing_cfg_2 register
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.
Yangbo Lu [Thu, 12 May 2016 11:12:58 +0000 (19:12 +0800)]
mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function
In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Wed, 4 May 2016 02:20:21 +0000 (10:20 +0800)]
drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Stephen Warren [Fri, 3 Jun 2016 19:05:11 +0000 (13:05 -0600)]
arm: lib: fix push/pop-section directives
With the existing code, function symbols are defined in .text, and the
body is defined in .text.xxx. This causes (at least some version of) the
linker not to emit the function body into the final binary, since it's
part of a different section to the symbols being referenced. This of
course causes a wide variety of failures.
This change moves the push/pop-section directives before the function
symbols, and after any relate ENDPROC macro invocations, so that symbols
and bodies are all in the "pushed" sections, and thus the function bodies
are emitted into the binary.
This solves (at least) the boot problems currently seen on Tegra systems
that use SPL (i.e. all ARMv7 Tegras).
Fixes: 13b0a91a6d48 ("arm: lib: Split asm symbols into different .text subsections") Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Lokesh Vutla [Thu, 26 May 2016 13:35:44 +0000 (19:05 +0530)]
ARM: k2g: Configure reset mux to device reset
BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.
Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.
Right now to give a default watchdog behaviour "Device reset" is
being selected.
Keerthy [Tue, 24 May 2016 06:15:06 +0000 (11:45 +0530)]
arm: am57xx: Fix omap_vcores assignment for am572x-idk
Currently omap_vcores is wrongly assigned a default value of
beagle_x15_volts. Hence populating a new structure for am572x-idk
and assigning it to omap_vcores in the vcores_init function.
Fixes: c020d355c45ed40fe12a ("board: ti: am57xx: Add support for am572x idk in SPL") Reported-by: Suman Anna <s-anna@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Keerthy [Tue, 24 May 2016 06:15:05 +0000 (11:45 +0530)]
arm: omap: Introduce vcores_init function
The pmic registers for variants of am57xx boards are different
hence we need to assign them carefully based on the board type.
Add a function to assign omap_vcores after the board detection.
Anna, Suman [Mon, 23 May 2016 18:32:17 +0000 (13:32 -0500)]
ARM: DRA7: Add macros for voltage values for all OPPs
Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.
The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Anna, Suman [Mon, 23 May 2016 18:32:16 +0000 (13:32 -0500)]
ARM: DRA7: Consolidate voltage macros across different SoCs
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Anna, Suman [Mon, 23 May 2016 18:32:15 +0000 (13:32 -0500)]
ARM: DRA7: Define common macros for efuse register offsets
Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Anna, Suman [Mon, 23 May 2016 18:32:14 +0000 (13:32 -0500)]
ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values
The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.
The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Roger Quadros [Mon, 23 May 2016 14:37:48 +0000 (17:37 +0300)]
ARM: AM57xx: AM43xx: Fix USB host
CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.
Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.
Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks") Signed-off-by: Roger Quadros <rogerq@ti.com>
projects / u-boot.git / log