]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
9 months agousb: gadget: UMS: support multiple sector sizes
Caleb Connolly [Wed, 20 Mar 2024 14:30:50 +0000 (14:30 +0000)]
usb: gadget: UMS: support multiple sector sizes

UFS storage often uses a 4096-byte sector size, add support for dynamic
sector sizes based loosely on the Linux implementation.

Support for dynamic sector sizes changes the types used in some
divisions, resulting in the compiler attempting to use
libgcc helpers (__aeabi_ldivmod).
Replace these divisions with calls to lldiv() to handle this correctly.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-4-41be480172e1@linaro.org
[mkorpershoek: squashed the lldiv() fix from caleb]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
9 months agousb: gadget: CDC ACM: call usb_gadget_initialize
Caleb Connolly [Wed, 20 Mar 2024 14:30:49 +0000 (14:30 +0000)]
usb: gadget: CDC ACM: call usb_gadget_initialize

To actually use the gadget the peripheral driver must be probed and we
must call g_dnl_clear_detach(). Otherwise acm_stdio_start() will always
fail to find a UDC on DT platforms.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-3-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
9 months agousb: dwc3-generic: implement Qualcomm wrapper
Caleb Connolly [Wed, 20 Mar 2024 14:30:47 +0000 (14:30 +0000)]
usb: dwc3-generic: implement Qualcomm wrapper

The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented
the missing initialisation for host and gadget mode.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-1-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
9 months agoMerge branch '2024-03-19-assorted-updates' into next
Tom Rini [Wed, 20 Mar 2024 12:39:05 +0000 (08:39 -0400)]
Merge branch '2024-03-19-assorted-updates' into next

- TI J7200 updates, GIC-600 support, 2 more tests, fix parsing
  ccsidr_el1 register in some cases, prepare for allowing remoteproc to
  use fs_loader and make the binary_size_check rule not require 'bc'.

9 months agotest/py: reset: Add a test for reset command
Love Kumar [Tue, 12 Mar 2024 08:48:33 +0000 (14:18 +0530)]
test/py: reset: Add a test for reset command

Add a test for reset commands which performs resetting of CPU, It does
COLD reset by default and WARM reset with -w option.

Signed-off-by: Love Kumar <love.kumar@amd.com>
9 months agotest/py: saveenv: Add a test for saveenv command
Love Kumar [Tue, 12 Mar 2024 08:46:10 +0000 (14:16 +0530)]
test/py: saveenv: Add a test for saveenv command

Add test case for saveenv command in non-JTAG bootmode which saves the
u-boot environment variables in persistent storage.

Signed-off-by: Love Kumar <love.kumar@amd.com>
9 months agoMakefile: use shell to calculate map_size
Leon M. Busch-George [Sun, 10 Mar 2024 21:53:52 +0000 (22:53 +0100)]
Makefile: use shell to calculate map_size

The error message "bc: command not found" is easily missed since the
build continues.
bc is not a part of coreutils or base-devel. POSIX sh can also do the
calculation.

Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
9 months agoarm: Check FEAT_CCIDX when parsing ccsidr_el1 register
Lukasz Wiecaszek [Sun, 10 Mar 2024 10:29:58 +0000 (11:29 +0100)]
arm: Check FEAT_CCIDX when parsing ccsidr_el1 register

Current Cache Size ID Register (ccsidr_el1) has two "flavors"
depending on whether FEAT_CCIDX is implemented or not.
When FEAT_CCIDX is implemented Associativity parameter
is coded on bits [23:3] and NumSets parameter on bits [55:32].
When FEAT_CCIDX is not implemented then Associativity parameter
is coded on bits [12:3] and NumSets parameter on bits [27:13].
Current U-Boot code does not check whether FEAT_CCIDX is implemented
and always parses ccsidr_el1 as if FEAT_CCIDX was not implemented.
This is of course wrong on systems where FEAT_CCIDX is implemented.
This patch fixes that problems and tests whether FEAT_CCIDX
is implemented or not and accordingly parses the ccsidr_el1 register.

Signed-off-by: Lukasz Wiecaszek <lukasz.wiecaszek@gmail.com>
9 months agoarm64: gic: Add power up sequence for GIC-600
Venkatesh Yadav Abbarapu [Wed, 6 Mar 2024 11:24:41 +0000 (16:54 +0530)]
arm64: gic: Add power up sequence for GIC-600

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Power on the redistributor and  wait until
the power on state is reflected by checking the bit
GICR_PWRR.RDPD == 0. While running U-Boot in EL3
without enabling this register, GICR_WAKER.ChildrenAsleep
bit is not getting cleared and loops infinitely.
This register(GICR_PWRR) must be programmed to mark the frame
as powered on, before accessing other registers in the frame.
Rest of initialization sequence remains the same.

ARM GIC-600 IP complies with ARM GICv3 architecture.
Enable this config if GIC-600 IP present.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
9 months agoarm: dts: k3-j7200-r5-common: Add missing overrides for ringacc and udmap
Aniket Limaye [Wed, 6 Mar 2024 06:37:49 +0000 (12:07 +0530)]
arm: dts: k3-j7200-r5-common: Add missing overrides for ringacc and udmap

Corrects the ti,sci property to point to dm_tifs node for proper
functioning of mcu_ringacc and mcu_udmap.

Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1")
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
9 months agoarm: dts: k3-j7200-r5-common: fix the mcu_timer0 clock frequency
Aniket Limaye [Wed, 6 Mar 2024 06:37:48 +0000 (12:07 +0530)]
arm: dts: k3-j7200-r5-common: fix the mcu_timer0 clock frequency

Correcting the clock-frequency property of the mcu_timer0 node

Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1")
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
9 months agoarm: dts: k3-j7200: Fix support for OSPI flash
Aniket Limaye [Wed, 6 Mar 2024 06:37:47 +0000 (12:07 +0530)]
arm: dts: k3-j7200: Fix support for OSPI flash

- Add the missing bootph-all property in the flash subnode for ospi
- Add the missing overrides for the ospi node in the r5 devicetree

Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
9 months agoconfigs: j7200_evm_*_defconfig: Enable OSPI configs
Aniket Limaye [Wed, 6 Mar 2024 06:37:46 +0000 (12:07 +0530)]
configs: j7200_evm_*_defconfig: Enable OSPI configs

Add the necessary configs required for OSPI functionality.
Also update the ospi flash partition offsets as per the devicetree.

Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
9 months agoarm: mach-k3: Fix config check for FS_LOADER
MD Danish Anwar [Thu, 14 Mar 2024 14:33:10 +0000 (20:03 +0530)]
arm: mach-k3: Fix config check for FS_LOADER

load_firmware() API calls fs-loader APIs and checks for CONFIG_FS_LOADER
before calling those APIs. The if check only checks for CONFIG_FS_LOADER
but not for CONFIG_SPL_FS_LOADER.

When CONFIG_FS_LOADER is enabled, load_firmware() API calls fs-loader APIs
but this is done at SPL stage and at this time FS_LOADER is not built yet
as a result we see below build error.

  AR      spl/boot/built-in.o
  LD      spl/u-boot-spl
arm-none-linux-gnueabihf-ld.bfd: arch/arm/mach-k3/common.o: in function
`load_firmware':
/home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:184: undefined
reference to `get_fs_loader'
arm-none-linux-gnueabihf-ld.bfd:
/home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:185: undefined
reference to `request_firmware_into_buf'
make[2]: *** [/home/danish/workspace/u-boot/scripts/Makefile.spl:527:
spl/u-boot-spl] Error 1
make[1]: *** [/home/danish/workspace/u-boot/Makefile:2055:
spl/u-boot-spl] Error 2
make[1]: Leaving directory '/home/danish/uboot_images/am64x/r5'
make: *** [Makefile:177: sub-make] Error 2

Fix this by modifying the if check to CONFIG_IS_ENABLED(FS_LOADER) instead
of IS_ENABLED(CONFIG_FS_LOADER) as the former will check for the
appropriate config option (CONFIG_SPL_FS_LOADER / CONFIG_FS_LOADER) based
on the build stage.

Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Acked-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
9 months agoMerge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians...
Tom Rini [Tue, 19 Mar 2024 13:10:30 +0000 (09:10 -0400)]
Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

- A new driver in the misc to register setting from device tree. This
  also provides user a clean interface and all register settings are
  centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
  new files are created for board, dts, configs and makefile to create
  the base for Agilex5.

Build-tested on SoC64 boards, boot tested on some of them.

9 months agoarch: arm: Agilex5 enablement
Jit Loon Lim [Tue, 12 Mar 2024 14:01:03 +0000 (22:01 +0800)]
arch: arm: Agilex5 enablement

This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
9 months agodrivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
Wan Yee Lau [Mon, 5 Feb 2024 03:47:16 +0000 (11:47 +0800)]
drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA

Add socfpga_dtreg driver enablement for Intel SoCFPGA.

Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
9 months agoMerge tag 'u-boot-imx-next-20240317' of https://gitlab.denx.de/u-boot/custodians...
Tom Rini [Mon, 18 Mar 2024 01:22:50 +0000 (21:22 -0400)]
Merge tag 'u-boot-imx-next-20240317' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19975

- Select polling-rate from cpu-thermal devicetree node on imx_tmu.
- Re-organize the U-Boot environment and add RAUC logic for
  phycore_imx8mp.
- Enable watchdog on colibri-imx7.
- Move imx8mm-venice to use OF_UPSTREAM.

9 months agoimx8m*_venice: move venice to OF_UPSTREAM
Tim Harvey [Tue, 12 Mar 2024 19:05:43 +0000 (12:05 -0700)]
imx8m*_venice: move venice to OF_UPSTREAM

Move to imx8m{m,n,p}-venice to OF_UPSTREAM:
 - replace the non-upstream generic imx8m{m,n,p}-venice dt with one of the
   dt's from the OF_LIST
 - handle the fact that dtbs now have a 'freescale/' prefix
 - imply OF_UPSTREAM
 - remove rudundant files from arch/arm/dts leaving only the
   *-u-boot.dtsi files

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
9 months agoboard: phytec: phycore_imx8mp: Add RAUC boot logic to environment
Leonard Anderweit [Tue, 12 Mar 2024 14:30:33 +0000 (15:30 +0100)]
board: phytec: phycore_imx8mp: Add RAUC boot logic to environment

Add RAUC boot logic to the environment. This is the first board to
utilize this environment.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
9 months agoinclude: env: Add phytec RAUC boot logic
Leonard Anderweit [Tue, 12 Mar 2024 14:30:32 +0000 (15:30 +0100)]
include: env: Add phytec RAUC boot logic

Add logic for booting systems with the RAUC update mechanism. This can
be reused by other phytec boards.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
9 months agoconfigs: phycore-imx8mp_defconfig: Use redundant environment
Leonard Anderweit [Tue, 12 Mar 2024 14:30:31 +0000 (15:30 +0100)]
configs: phycore-imx8mp_defconfig: Use redundant environment

Add support for the redundant environment.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
9 months agophycore_imx8mp: Move default bootcmd to board env
Leonard Anderweit [Tue, 12 Mar 2024 14:30:30 +0000 (15:30 +0100)]
phycore_imx8mp: Move default bootcmd to board env

Move the default bootcmd from the defconfig to the board environment.
No change in functionality.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
9 months agophycore_imx8mp: Move environment from include/config to board
Leonard Anderweit [Tue, 12 Mar 2024 14:30:29 +0000 (15:30 +0100)]
phycore_imx8mp: Move environment from include/config to board

Move the environment into the board directory and convert it from a C
header to a text file. Sort the variables alphabetically.
No functional changes.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
9 months agodrivers: imx_tmu: Select polling-rate from cpu-thermal devicetree node
Benjamin Hahn [Mon, 4 Mar 2024 11:48:54 +0000 (12:48 +0100)]
drivers: imx_tmu: Select polling-rate from cpu-thermal devicetree node

The polling rate is already specified in some devicetrees, like
imx8mp.dtsi for example, but was not selected so far. For the
trippoints, the cpu-thermal node is used. Also get the polling rate from
this node. Use the default of 5000ms if the polling rate should not be
specified in the devicetree.

NOTE: The polling rate from the devicetree will be used after this
patch. In imx8*.dtsi devicetrees the polling delay is set to 2000ms for
example.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
9 months agoconfigs: colibri-imx7: enable watchdog
Parth Pancholi [Thu, 7 Mar 2024 15:23:02 +0000 (16:23 +0100)]
configs: colibri-imx7: enable watchdog

Enable watchdog functionality for Toradex's Colibri iMX7 (NAND/EMMC)
modules.

Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
9 months agoMerge tag 'u-boot-rockchip-20240315' of https://source.denx.de/u-boot/custodians...
Tom Rini [Fri, 15 Mar 2024 13:15:31 +0000 (09:15 -0400)]
Merge tag 'u-boot-rockchip-20240315' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next

Please pull the updates for rockchip platform:
- Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC,
             Toybrick TB-RK3588X;
             rk3588s Cool Pi 4B;
             rk3566 Pine64 PineTab2;
- Add saradc v2 support;
- Add PMIC RK806 support;
- rk3588 disable force_jtag by default;
- Migrate to use IO-domain driver for all boards;
- Use common bss and stack addresses for rk33xx and rk35xx boards;
- Other updates for driver, config and dts;

9 months agoCI: Move to latest container image
Tom Rini [Fri, 15 Mar 2024 02:36:43 +0000 (22:36 -0400)]
CI: Move to latest container image

This moves us to our latest container image, which is now based on the
current "Jammy" tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
9 months agoCI: Cherry-pick reset support for m68k for QEMU
Tom Rini [Mon, 11 Mar 2024 14:02:43 +0000 (10:02 -0400)]
CI: Cherry-pick reset support for m68k for QEMU

In order to support the reset pytest on QEMU on m68k platforms we need
to grab this change from upstream.

Signed-off-by: Tom Rini <trini@konsulko.com>
9 months agoCI: Update to using clang-17
Tom Rini [Sun, 10 Mar 2024 19:59:28 +0000 (15:59 -0400)]
CI: Update to using clang-17

Currently, llvm-17 is the stable release. Update our container and CI to
fetch and use that.

Signed-off-by: Tom Rini <trini@konsulko.com>
9 months agoDockerfile: install xilinx-bootgen package
Heinrich Schuchardt [Wed, 28 Feb 2024 07:23:09 +0000 (08:23 +0100)]
Dockerfile: install xilinx-bootgen package

Bootgen is used in a binman test. The test is skipped without the binary.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
9 months agoDockerfile: build fiptool
Heinrich Schuchardt [Wed, 28 Feb 2024 07:43:11 +0000 (08:43 +0100)]
Dockerfile: build fiptool

Fiptool is used in a binman test. The test is skipped without the binary.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
9 months agorockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support
Quentin Schulz [Thu, 14 Mar 2024 09:36:29 +0000 (10:36 +0100)]
rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support

ADC support is implied by the Rockchip arch Kconfig but that means it
should be possible to disable ADC support and still be able to build.

However the weak implementation of rockchip_dnl_key_pressed() currently
blindly use functions from the ADC subsystem which do not exist when ADC
is not enabled, failing the build.

Therefore, let's encapsulate this logic with a check on the ADC symbol
being selected.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agobutton: add missing ADC dependency for BUTTON_ADC
Quentin Schulz [Thu, 14 Mar 2024 09:36:28 +0000 (10:36 +0100)]
button: add missing ADC dependency for BUTTON_ADC

The BUTTON_ADC symbol guards the compilation of button-adc driver whose
name very well makes it explicit that it requires ADC support to be
enabled.

Fix build issue of button-adc driver when ADC support isn't enabled by
making sure it cannot be built without ADC support.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agoadc: add missing depends on ADC for controller drivers
Quentin Schulz [Thu, 14 Mar 2024 09:36:27 +0000 (10:36 +0100)]
adc: add missing depends on ADC for controller drivers

The ADC controller drivers are obviously all depending on ADC symbol
being selected.

While they don't seem to fail to build without, they won't be useful
without that symbol selected, so let's make sure the options aren't
shown in menuconfig when ADC isn't selected.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: jaguar-rk3588: enable SARADC and derivatives
Quentin Schulz [Thu, 14 Mar 2024 09:36:26 +0000 (10:36 +0100)]
rockchip: jaguar-rk3588: enable SARADC and derivatives

The SARADC is used on Jaguar for multiple things:
- channel 0 is used (at runtime) as a BIOS button,
- channel 2 is exposed on the Mezzanine connector for customer specific
  logic,
- channel 5 and 6 are used for identification,

Since the SARADC requires a vref-supply provided by the RK806 PMIC, its
support and the support for its regulators are also enabled.

The button, adc, pmic and regulator commands are also enabled for CLI
use in U-Boot for debugging and scripting purposes.

The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable
Rockchip SPI controller driver.

Finally, the SARADC channel 1 on Jaguar is hardwired so will never
change in the lifetime of a unit, for that reason, disable the Rockchip
Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agopower: pmic: rk8xx: fix duplicate prompt
Quentin Schulz [Thu, 14 Mar 2024 09:36:25 +0000 (10:36 +0100)]
power: pmic: rk8xx: fix duplicate prompt

SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it
difficult to know at first glance in menuconfig what's for what, let's
fix this by adding "in SPL" at the end of the prompt for the SPL symbol.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: adc: rockchip-saradc: add support for RK3588
Quentin Schulz [Thu, 14 Mar 2024 09:36:24 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: add support for RK3588

This adds support for the SARADCv2 found on RK3588.

There is no stop callback as it is currently configured in single
conversion mode, where the ADC is powered down after a single conversion
has been made.

Due to what seems to be a silicon bug, a controller reset needs to be
issued before starting a channel conversion otherwise Rockchip says that
channel 1 will error whatever that means. This is aligned with upstream
and downstream Linux kernel as well as downstream U-Boot.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: adc: rockchip-saradc: factor out stop callback
Quentin Schulz [Thu, 14 Mar 2024 09:36:23 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: factor out stop callback

SARADC v2 doesn't have a stop mechanism once in single mode. In series
conversion, the logic is different anyway. Therefore, let's abstract
this function so that it can be provided from the udevice.data pointer.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: adc: rockchip-saradc: factor out start_channel callback
Quentin Schulz [Thu, 14 Mar 2024 09:36:22 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: factor out start_channel callback

SARADC v1 and v2 have a different way of starting a channel, therefore
let's abstract this function so that it can be provided from the
udevice.data pointer.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: adc: rockchip-saradc: factor out channel_data callback
Quentin Schulz [Thu, 14 Mar 2024 09:36:21 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: factor out channel_data callback

SARADC v1 and v2 have a different way of reading data, therefore let's
abstract this function so that it can be provided from the udevice.data
pointer.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: adc: rockchip-saradc: use union for preparing for v2
Quentin Schulz [Thu, 14 Mar 2024 09:36:20 +0000 (10:36 +0100)]
rockchip: adc: rockchip-saradc: use union for preparing for v2

The registers are entirely different between SARADC v1 and SARADC v2, so
let's prepare to add another struct for accessing v2 registers by adding
a union.

Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agopmic: reword help text
Quentin Schulz [Thu, 14 Mar 2024 09:36:19 +0000 (10:36 +0100)]
pmic: reword help text

Reword the help text for the pmic read and pmic write commands to better
match what's expected from the user.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agopower: rk8xx: add support for RK806
Quentin Schulz [Thu, 14 Mar 2024 09:36:18 +0000 (10:36 +0100)]
power: rk8xx: add support for RK806

This adds support for RK806, only the SPI variant has been tested.

The communication "protocol" over SPI is the following:
 - write three bytes:
   - 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write
   - 1 byte: LSB register address
   - 1 byte: MSB register address
 - write/read length of payload

The CRC is always disabled for now.

The RK806 technically supports I2C as well, and this should be able to
support it without any change, but it wasn't tested.

The DT node name prefix for the buck converters has changed in the
Device Tree and is now dcdc-reg. The logic for buck converters is
however manageable within the current logic inside the rk8xx regulator
driver. The same cannot be said for the NLDO and PLDO.

Because pmic_bind_children() parses the DT nodes and extracts the LDO
index from the DT node name, NLDO and PLDO will have overlapping
indices. Therefore, we need a separate logic from the already-existing
ldo callbacks. Let's reuse as much as possible though.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agoregulator: rk8xx: add indirection level for some ldo callbacks
Quentin Schulz [Thu, 14 Mar 2024 09:36:17 +0000 (10:36 +0100)]
regulator: rk8xx: add indirection level for some ldo callbacks

By passing a rk8xx_reg_info directly to the internal get_value, it'd be
possible to call this same function with a logic for getting the
rk8xx_reg_info different from the current get_ldo_reg, e.g. for NLDO and
PLDO support for RK806.

No logic change is expected.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agoregulator: rk8xx: fix SWITCH enable on RK809
William Wu [Thu, 14 Mar 2024 09:36:16 +0000 (10:36 +0100)]
regulator: rk8xx: fix SWITCH enable on RK809

On RK809 in PMIC_POWER_ENX registers, in order to set or clear a bit N,
the bit at offset N + 4 needs to be set otherwise nothing is done.

This fixes the inability to modify the SWITCH state on RK809.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: William Wu <william.wu@rock-chips.com>
[reworded commit log]
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agoregulator: rk8xx: remove unused functions
Quentin Schulz [Thu, 14 Mar 2024 09:36:15 +0000 (10:36 +0100)]
regulator: rk8xx: remove unused functions

Those two functions had their last user removed in commit f9c68a566c4d
("rockchip: phycore_rk3288: remove phycore_init() function") part of
v2023.01 release, so let's do some cleanup here.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: spi: rk_spi: do not write bytes when in read-only mode
Quentin Schulz [Thu, 14 Mar 2024 09:36:14 +0000 (10:36 +0100)]
rockchip: spi: rk_spi: do not write bytes when in read-only mode

The read-only mode is currently supported but only for 16b-aligned
buffers. For unaligned buffers, the last byte will be read in RW mode
right now, which isn't what is desired. Instead, let's put the
controller back into RO mode for that last byte and skip any write in
the xfer loop.

This is required for 3-wire SPI mode where PICO/POCI lanes are shorted
on HW level. This incidentally the recommended design for RK806 PMIC for
RK3588 products.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: load env from boot MMC device
Ben Wolsieffer [Fri, 8 Mar 2024 03:00:51 +0000 (22:00 -0500)]
rockchip: load env from boot MMC device

Currently, if the environment is stored on an MMC device, the device
number is hardcoded by CONFIG_SYS_MMC_ENV_DEV. This is problematic
because many boards can choose between booting from an SD card or a
removable eMMC. For example, the Rock64 defconfig sets
CONFIG_SYS_MMC_ENV_DEV=1, which corresponds to the SD card. If an eMMC
is used as the boot device and no SD card is installed, it is impossible
to save the environment.

To avoid this problem, we can choose the environment MMC device based on
the boot device. The theobroma-systems boards already contain code to do
this, so this commit simply moves it to the common Rockchip board file,
with some refactoring. I also removed another implementation of
mmc_get_env_dev() from tinker_rk3288 that performed MMC boot device
detection by reading a bootrom register.

This has been tested on a Rock64v2.

Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agoboard: rockchip: Add early ADC button detect for RGxx3
Chris Morgan [Mon, 5 Feb 2024 18:58:55 +0000 (12:58 -0600)]
board: rockchip: Add early ADC button detect for RGxx3

Add ADC button detect for early SPL stage for RGxx3 device. This is
important because on at least the RG353P and RG353V a clk pin is not
exposed that would allow us to take the eMMC out of the boot path.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoconfigs: Remove unnecessary options from RGxx3 config
Chris Morgan [Mon, 5 Feb 2024 18:58:54 +0000 (12:58 -0600)]
configs: Remove unnecessary options from RGxx3 config

Based on feedback from the mailing list while adding support for a new
device (the Powkiddy X55), correct the config options for the RGxx3
as well to remove unnecessary drivers and increase the SPL stack size.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoboard: rockchip: Add support for Powkiddy RGB10MAX3
Chris Morgan [Mon, 5 Feb 2024 18:58:53 +0000 (12:58 -0600)]
board: rockchip: Add support for Powkiddy RGB10MAX3

Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device
is extremely similar to all the other devices and can use the same
bootloader with the same detection logic.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoarm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3
Chris Morgan [Mon, 5 Feb 2024 18:58:52 +0000 (12:58 -0600)]
arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3

Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
Move the necessary defines to the RGxx3 main dts file.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: board: Move gpt_capsule_update_setup() call
Jonas Karlman [Tue, 12 Mar 2024 23:36:22 +0000 (23:36 +0000)]
rockchip: board: Move gpt_capsule_update_setup() call

Move the call to gpt_capsule_update_setup() from the weak function
rk_board_late_init() into the main board_late_init() function.

Also change to use IS_ENABLED() instead for defined().

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: google: gru: Migrate to use IO-domain driver
Jonas Karlman [Tue, 12 Mar 2024 23:36:21 +0000 (23:36 +0000)]
rockchip: google: gru: Migrate to use IO-domain driver

Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: theobroma-systems: puma: Migrate to use IO-domain driver
Jonas Karlman [Tue, 12 Mar 2024 23:36:20 +0000 (23:36 +0000)]
rockchip: theobroma-systems: puma: Migrate to use IO-domain driver

Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: vamrs: rock960: Migrate to use IO-domain driver
Jonas Karlman [Tue, 12 Mar 2024 23:36:19 +0000 (23:36 +0000)]
rockchip: vamrs: rock960: Migrate to use IO-domain driver

Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: pine64: pinephone-pro: Migrate to use IO-domain driver
Jonas Karlman [Tue, 12 Mar 2024 23:36:18 +0000 (23:36 +0000)]
rockchip: pine64: pinephone-pro: Migrate to use IO-domain driver

Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: pine64: pinebook-pro: Migrate to use IO-domain driver
Jonas Karlman [Tue, 12 Mar 2024 23:36:17 +0000 (23:36 +0000)]
rockchip: pine64: pinebook-pro: Migrate to use IO-domain driver

Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: pine64: rockpro64: Migrate to use IO-domain driver
Jonas Karlman [Tue, 12 Mar 2024 23:36:16 +0000 (23:36 +0000)]
rockchip: pine64: rockpro64: Migrate to use IO-domain driver

Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: io-domain: Add support for RK3399
Jonas Karlman [Tue, 12 Mar 2024 23:36:15 +0000 (23:36 +0000)]
rockchip: io-domain: Add support for RK3399

Port the RK3399 part of the Rockchip IO-domain driver from linux.

This differs from linux version in that pmu io iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supply that have been configured.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoboard: rockchip: Add a common ROCK Pi 4 target
Jonas Karlman [Tue, 12 Mar 2024 23:36:14 +0000 (23:36 +0000)]
board: rockchip: Add a common ROCK Pi 4 target

Move ROCK Pi 4 specific board code from the shared evb_rk3399 target
into its own board target and update related defconfigs to use the new
TARGET_ROCKPI4_RK3399 option.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
9 months agoboard: rockchip: rk3399: Remove unused board_early_init_f functions
Jonas Karlman [Tue, 12 Mar 2024 23:36:13 +0000 (23:36 +0000)]
board: rockchip: rk3399: Remove unused board_early_init_f functions

These functions is excluded from SPL build and BOARD_EARLY_INIT_F is not
enabled for any of the affected boards, so this legacy code is not used.

Rockchip common board code already enable all regulators flagged as
always-on or boot-on in device tree, and fixed/gpio regulators now have
basic reference counting support so the original intent of this code is
no longer valid.

Remove the unneeded and unused code that used to enable usb regulators.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoboard: rockchip: rk3399: Add myself as reviewer to MAINTAINERS
Jonas Karlman [Tue, 12 Mar 2024 23:36:12 +0000 (23:36 +0000)]
board: rockchip: rk3399: Add myself as reviewer to MAINTAINERS

Add myself as a reviewer for RK3399 boards that I have and can help with
review and testing of defconfig and device tree changes.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoboard: rockchip: rk3399: Add device tree files to MAINTAINERS
Jonas Karlman [Tue, 12 Mar 2024 23:36:11 +0000 (23:36 +0000)]
board: rockchip: rk3399: Add device tree files to MAINTAINERS

Update MAINTAINERS files for RK3399 boards to include related device
tree files. Also correct a few filenames.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Migrate to use DM_USB_GADGET on RK3328
Jonas Karlman [Sun, 10 Mar 2024 18:51:00 +0000 (18:51 +0000)]
rockchip: Migrate to use DM_USB_GADGET on RK3328

USB gadget is not working fully as expected on RK3328, it uses a
board_usb_init() function to initialize the DWC2 OTG port.

The board_usb_init() function does not intgrate with the generic phy
framework and as a result the USB phy is not properly configured before
or after USB gadget use.

Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
causing some issues.

Trying to use rockusb or ums command after usb stop result in a freeze
due to usb stop is putting the phy in a suspended state.

  => usb start
  => usb stop
  => ums 0 mmc 0
  --> freeze due to usb phy is suspended <--

Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
depending on the most likely usage of the otg port and by migrating to
use DM_USB_GADGET instead of a board_usb_init() function.

The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
Type-C connector, mark these boards dr_mode as peripheral, the most
likely usage is for recovery and image download.

The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
driver from these boards to ensure that the USB_DWC2 driver is used.

The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
and DWC2_OTG is removed from this board.

Enable RockUSB and UMS on all boards with a otg port in peripheral mode.

Also with the migration to DM_USB_GADGET completed the U-Boot specific
change to reorder usb nodes in the soc device tree can be reverted.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: board: Use a common USB Product ID for UMS
Jonas Karlman [Sun, 10 Mar 2024 18:50:59 +0000 (18:50 +0000)]
rockchip: board: Use a common USB Product ID for UMS

Change to use the common Product ID 0x0010 when the ums command is used.

This matches downstream vendor U-Boot and is a Product ID that tools
such as rkdeveloptool and RKDevTool will identify as MSC mode.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: board: Prepare for use of DM_USB_GADGET with DWC2_OTG
Jonas Karlman [Sun, 10 Mar 2024 18:50:58 +0000 (18:50 +0000)]
rockchip: board: Prepare for use of DM_USB_GADGET with DWC2_OTG

The board_usb_init() and board_usb_cleanup() functions is always
included when USB_GADGET and USB_GADGET_DWC2_OTG is enabled.

Prepare for a change to use DM_USB_GADGET with DWC2_OTG by adding an
extra ifdef condition. The extra separate ifdef for USB_GADGET prepare
for next patch that adds a g_dnl_bind_fixup() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Update the default USB Product ID value
Jonas Karlman [Sun, 10 Mar 2024 18:50:57 +0000 (18:50 +0000)]
rockchip: Update the default USB Product ID value

RK3036 is using the USB product id normally used by RK3066B, and RK3328
is using the product id normally used by RK3368.

Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option
for remaining supported Rockchip SoCs to match the product id used in
Maskrom mode.

Also remove a reference to an undefined ROCKCHIP_RK3229 Kconfig symbol.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
9 months agorockchip: Use common bss and stack addresses on RK3588
Jonas Karlman [Sat, 2 Mar 2024 19:16:16 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK3588

Currently the following memory layout is typically used on RK3588:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[ 3.5M,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,   6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[   5M,   6M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[  10M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,  12M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[11.5M,  12M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[  64M, +16K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)

SPL can safely load U-Boot proper + FDT to [10M, 11.5M) with this layout.

However, on ROCK 5A the SPL stacks is overlapping:
[   -X,  16M) - SPL pre-reloc stack (SPL_STACK)
[15.5M,  16M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,  16M) - SPL reloc stack (SPL_STACK_R_ADDR)
[  15M,  16M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)

Because bind and probe udevice instanses is allocated on the pre-reloc
malloc heap, there is going to be an overlap when reloc malloc heap
reaches close to 512 KiB of usage.

Migrate to use common bss, stack and malloc heap size and addresses to
mitigate these limitations and allow for a larger U-Boot proper size.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Update for new boards defconfig)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Use common bss and stack addresses on RK356x
Jonas Karlman [Sat, 2 Mar 2024 19:16:15 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK356x

Currently the following memory layout is typically used on RK356x:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[-128K,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,   6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[   5M,   6M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[  10M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,  12M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[-128K,  12M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[  64M, +16K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)

SPL can safely load U-Boot proper + FDT to [10M, 12M-128K) with this
layout.

Migrate to use common bss, stack and malloc heap size and addresses to
remove this size limitation.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Update for pinetab2-rk3566_defconfig)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Use common bss and stack addresses on RK3399
Jonas Karlman [Sat, 2 Mar 2024 19:16:14 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK3399

With the stack and text base used by U-Boot SPL and proper on RK3399
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.

Currently the following memory layout is typically used on RK3399:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   2M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,   3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[ -16K,   3M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[ -16K,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   4M,  +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)
[   -X,  64M) - SPL reloc stack (SPL_STACK_R_ADDR)
[  63M,  64M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)

SPL can safely load U-Boot proper + FDT to [2M, 4M-16K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.

Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Use common bss and stack addresses on RK3328
Jonas Karlman [Sat, 2 Mar 2024 19:16:13 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK3328

With the stack and text base used by U-Boot SPL and proper on RK3328
there is a high likelihood of overlapping when U-Boot proper + FDT nears
or exceeded 1 MiB in size.

Currently the following memory layout is typically used on RK3328:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   2M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,   3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[  -8K,   3M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[  -8K,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   -X,   6M) - SPL reloc stack (SPL_STACK_R_ADDR)
[   5M,   6M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)
[  32M,  +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)

SPL can safely load U-Boot proper + FDT to [2M, 4M-8K) with this layout.
However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is
restricting the safe size of U-Boot proper + FDT to be less than 1 MiB.

Migrate to use common bss, stack and malloc heap size and addresses to
fix this restriction and allow for a larger U-Boot proper image size.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Use common bss and stack addresses on RK3308
Jonas Karlman [Sat, 2 Mar 2024 19:16:12 +0000 (19:16 +0000)]
rockchip: Use common bss and stack addresses on RK3308

Currently the following memory layout is typically used on RK3308:
[    0, 256K) - SPL binary
[ 256K,   2M) - TF-A / reserved
[   -X,   4M) - SPL pre-reloc stack (SPL_STACK)
[  -8K,   4M)   - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN)
[   4M,  +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE)
[   6M,   +X) - U-Boot proper binary (TEXT_BASE)
[   -X,   8M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR)
[  -8K,   8M)   - pre-reloc malloc heap (SYS_MALLOC_F_LEN)
[   -X,  12M) - SPL reloc stack (SPL_STACK_R_ADDR)
[  11M,  12M)   - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN)

SPL can safely load U-Boot proper + FDT to [6M, 8M-8K) with this layout.

Migrate to use common bss, stack and malloc heap size and addresses to
remove this size limitation and extend the malloc heap size being used.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: Add common default bss and stack addresses
Jonas Karlman [Sat, 2 Mar 2024 19:16:11 +0000 (19:16 +0000)]
rockchip: Add common default bss and stack addresses

On Rockchip the typical aarch64 boot steps are as follows:
- BROM load TPL to SRAM
- TPL init full DRAM
  - use stack in SRAM at TPL_STACK addr
  - use malloc heap on stack, size is TPL_SYS_MALLOC_F_LEN
- TPL jump back to BROM
- BROM load SPL to beginning of DRAM
- SPL init storage devices
  - use bss in DRAM at SPL_BSS_START_ADDR, size is SPL_BSS_MAX_SIZE
  - use stack in DRAM at SPL_STACK addr (or CUSTOM_SYS_INIT_SP_ADDR)
  - use malloc heap on stack, size is SPL_SYS_MALLOC_F_LEN
- SPL load FIT images from storage to DRAM
  - use stack in DRAM at SPL_STACK_R_ADDR
  - use new malloc heap on stack, size is SPL_STACK_R_MALLOC_SIMPLE_LEN
- SPL jump to TF-A at 0x40000
- (optional) TF-A load OPTEE
- TF-A jump to U-Boot proper at TEXT_BASE
- U-Boot proper init pre-reloc devices
  - use stack in DRAM at CUSTOM_SYS_INIT_SP_ADDR
  - use malloc heap on stack, size is SYS_MALLOC_F_LEN
- U-Boot proper relocate to end of usable DRAM
- U-Boot proper init devices and complete boot

SPL have access to full DRAM, however, current configuration for text
base, stack addr and malloc heap size used at the different boot steps
are at risk of overlapping, e.g. when U-Boot proper + FDT grows close
to 1 MiB on RK3328/RK3399 or when pre-reloc and reloc stack and malloc
heap overlap on ROCK 5A.

Fix this by defining safe defaults for bss, stack and malloc size and
addresses. A range at around [60 MiB, 64 MiB) was chosen to be used for
bss and stack until U-Boot proper have been relocated to end of usable
DRAM. The range was primarily chosen to be able to accommodate SoCs with
a small amount of embedded DRAM, e.g. RK3308G has 64 MiB DRAM.

Overiew of the new common memory layout:
[    0,   2M) - SPL / TF-A / reserved
[   2M,   +X) - U-Boot proper pre-reloc
[   -X,  64M) - bss, stack and malloc heap

During SPL pre-reloc phase:
[    0, 256K) - SPL binary is loaded by BROM to beginning of DRAM
[   -X,  63M) - SPL pre-reloc stack
[ -32K,  63M)   - SPL pre-reloc malloc heap
[63.5M, +32K) - SPL bss

After SPL reloc phase:
[    0, 256K) - SPL binary
[ 256K,   +X) - TF-A image is loaded by SPL
[   2M,   +X) - U-Boot proper + FDT image is loaded by SPL
[   -X,  62M) - SPL reloc stack
[  60M,  62M)   - SPL reloc malloc heap
[ -32K,  63M) - SPL init malloc heap, memory allocated during SPL
                pre-reloc phase is still in use at reloc phase
[63.5M, +32K) - SPL bss

During U-Boot proper pre-reloc phase:
[    0,   2M) - TF-A / reserved
[   2M,   +X) - U-Boot proper + FDT
[   -X,  63M) - U-Boot proper pre-reloc stack (shared addr with SPL)
[ -64K,  63M)   - U-Boot proper pre-reloc malloc heap

After U-Boot proper has relocated to top of memory we should be able to
use 2M+ for loading kernel, initrd, scripts etc.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoboard: rockchip: Add Pine64 PineTab2
Jonas Karlman [Sun, 4 Feb 2024 17:30:35 +0000 (17:30 +0000)]
board: rockchip: Add Pine64 PineTab2

The Pine64 PineTab2 is a tablet computer based on the Rockchip RK3566
SoC. The table features 4/8 GB LPDDR4 RAM and 64/128 GB eMMC storage.

Features tested on a Pine64 PineTab2 8GB v2.0:
- SD-card boot
- eMMC boot
- SPI Flash boot
- USB host

Device tree is imported from linux maintainer branch v6.9-armsoc/dts64,
commit 1b7e19448f8f ("arm64: dts: rockchip: Add devicetree for Pine64
PineTab2").

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: board: Add minimal generic RK3588S/RK3588 board
Jonas Karlman [Wed, 31 Jan 2024 22:08:51 +0000 (22:08 +0000)]
rockchip: board: Add minimal generic RK3588S/RK3588 board

Add a minimal generic RK3588S/RK3588 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3588S/RK3588 boards that follow reference board design.

Also fix the alphabetical order of RK3588 boards listed in Makefile and
documentation.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
9 months agoboard: rockchip: add Rockchip Toybrick TB-RK3588X board
Elon Zhang [Mon, 11 Mar 2024 03:57:33 +0000 (11:57 +0800)]
board: rockchip: add Rockchip Toybrick TB-RK3588X board

TB-RK3588X board is a Rockchip Toybrick RK3588 based development board.

Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB Memory LPDDR4x
Mali G610MC4 GPU
2× MIPI-CSI0 Connector
1x 2Lanes PCIe3.0 Connector
1x SATA3.0 Connector
32GB eMMC Module
2x USB 2.0, 2x USB 3.0
1x HDMI Output, 1x HDMI Input
2x Ethernet Port

Functions work normally:
[1] USB2.0 Host
[2] Ethernet0 with PHY RTL8211F

More information can be obtained from the following websites:
[1] https://t.rock-chips.com/en/wiki/EN/tb-rk3588x_en/index.html
[2] http://t.rock-chips.com/

Kernel commits:
8ffe365f8dc7 ("arm64: dts: rockchip: Add devicetree support for TB-RK3588X board")
7140387ff49d ("dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X")

Reviewed-by: Weizhao Ouyang <weizhao.ouyang@arm.com>
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agophy: rockchip-inno-usb2: Limit changes made to regs
Jonas Karlman [Sun, 25 Feb 2024 22:10:20 +0000 (22:10 +0000)]
phy: rockchip-inno-usb2: Limit changes made to regs

The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.

Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.

When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
9 months agophy: rockchip-inno-usb2: Write to correct GRF
Jonas Karlman [Sun, 25 Feb 2024 22:10:19 +0000 (22:10 +0000)]
phy: rockchip-inno-usb2: Write to correct GRF

On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
that is supported by this driver have the USB2PHY regs in a different
GRF.

When support for RK356x, RK3588 and RK3328 was added this driver was
never updated to use correct GRF and have instead incorrectly written
to wrong GRF for these SoCs.

The default reset values for the USB2PHY have made USB mostly working
even when wrong GRF was used, however, following have been observed:

  scanning bus usb@fd840000 for devices...
  ERROR:  USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
  not provide a handshake (OUT) (5)
  ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
  not provide a handshake (OUT) (5)
  unable to get device descriptor (error=-1)

Fix this by using a regmap from rockchip,usbgrf prop and fall back to
getting a regmap for parent udevice instead of always getting the
common GRF.

Also protect against accidental clear of bit 0 in a reg with offset 0,
only bind driver to enabled otg/host-ports and remove unused headers.

Fixes: 3da15f0b49a2 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568")
Fixes: cdf9010f6e17 ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY")
Fixes: 9aa93d84038b ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: spl: Enable caches to speed up checksum validation
Jonas Karlman [Sat, 17 Feb 2024 12:34:04 +0000 (12:34 +0000)]
rockchip: spl: Enable caches to speed up checksum validation

FIT checksum validation is very slow in SPL due to D-cache not being
enabled.

Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation,
from seconds to milliseconds.

This change enables caches in SPL on all Rockchip ARM64 boards, the
Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to
disable caches for a specific board or SoC if needed.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoboard: rockchip: Add support for rk3588 based Cool Pi CM5 EVB
Andy Yan [Sat, 17 Feb 2024 11:25:00 +0000 (19:25 +0800)]
board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

9 months agoboard: rockchip: Add support for rk3588s based Cool Pi 4B
Andy Yan [Sat, 17 Feb 2024 11:24:59 +0000 (19:24 +0800)]
board: rockchip: Add support for rk3588s based Cool Pi 4B

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

9 months agorockchip: nanopi-r4s: Drop ROCKCHIP_OTP
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:08 +0000 (21:51 +0800)]
rockchip: nanopi-r4s: Drop ROCKCHIP_OTP

The NanoPi R4S has an RK3399 SoC, which has efuse supported by
ROCKCHIP_EFUSE, not ROCKCHIP_OTP.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
9 months agorockchip: rk3399: regenerate defconfigs
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:07 +0000 (21:51 +0800)]
rockchip: rk3399: regenerate defconfigs

Regenerate RK3399 defconfigs after adding imply statements.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
9 months agorockchip: rk3328: regenerate defconfigs
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:06 +0000 (21:51 +0800)]
rockchip: rk3328: regenerate defconfigs

Regenerate RK3328 defconfigs after adding imply statements.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
9 months agorockchip: rk3399: Read cpuid and generate MAC address from efuse
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:05 +0000 (21:51 +0800)]
rockchip: rk3399: Read cpuid and generate MAC address from efuse

The rockchip-efuse driver supports the efuse found on RK3399. This
hardware block is part of the SoC and contains the CPUID, which can
be used to generate stable serial numbers and MAC addresses.

Enable the driver and reading cpuid by default for RK3399.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
9 months agorockchip: rk3328: Read cpuid and generate MAC address from efuse
Chen-Yu Tsai [Mon, 12 Feb 2024 13:51:04 +0000 (21:51 +0800)]
rockchip: rk3328: Read cpuid and generate MAC address from efuse

The rockchip-efuse driver supports the efuse found on RK3328. This
hardware block is part of the SoC and contains the CPUID, which can
be used to generate stable serial numbers and MAC addresses.

Enable the driver and reading cpuid by default for RK3328.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
9 months agorockchip: rk3328-orangepi-r1-plus: Enable boot from SPI NOR flash
Jonas Karlman [Sat, 17 Feb 2024 00:22:41 +0000 (00:22 +0000)]
rockchip: rk3328-orangepi-r1-plus: Enable boot from SPI NOR flash

Add Kconfig options to enable support for booting from SPI NOR flash on
Orange Pi R1 Plus boards.

The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of
SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx
boards.

  => sf probe
  SF: Detected zb25vq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1376768 bytes read in 66 ms (19.9 MiB/s)

  => sf update ${fileaddr} 0 ${filesize}
  device 0 offset 0x0, size 0x150200
  1126912 bytes written, 249856 bytes skipped in 14.22s, speed 100542 B/s

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328-rock64: Enable boot from SPI NOR flash
Jonas Karlman [Sat, 17 Feb 2024 00:22:40 +0000 (00:22 +0000)]
rockchip: rk3328-rock64: Enable boot from SPI NOR flash

Add Kconfig options to enable support for booting from SPI NOR flash on
Pine64 Rock64.

The generated bootable u-boot-rockchip-spi.bin can be written to 0x0 of
SPI NOR flash. The FIT image is loaded from 0x60000, same as on RK35xx
boards.

  => sf probe
  SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1359872 bytes read in 65 ms (20 MiB/s)

  => sf update ${fileaddr} 0 ${filesize}
  device 0 offset 0x0, size 0x14c000
  1118208 bytes written, 241664 bytes skipped in 8.516s, speed 163516 B/s

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328: Add support to build bootable SPI image
Jonas Karlman [Sat, 17 Feb 2024 00:22:39 +0000 (00:22 +0000)]
rockchip: rk3328: Add support to build bootable SPI image

Similar to RK35xx the BootRom in RK3328 can read all data and look for
idbloader at 0x8000, same as it does for SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agoRevert "rockchip: Allow booting from SPI"
Jonas Karlman [Sat, 17 Feb 2024 00:22:38 +0000 (00:22 +0000)]
Revert "rockchip: Allow booting from SPI"

This reverts commit 3523c07867b403d5b3b68812aebac8a5afa5be4c.

Booting from SPI was already allowed before this commit was first
introduced. A few lines further down the exact same code already existed
and still does.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328: Sync device tree from linux v6.8-rc1
Jonas Karlman [Sat, 17 Feb 2024 00:22:37 +0000 (00:22 +0000)]
rockchip: rk3328: Sync device tree from linux v6.8-rc1

Sync rk3328 device tree from linux v6.8-rc1.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorng: rockchip: Use same compatible as linux
Jonas Karlman [Sat, 17 Feb 2024 00:22:36 +0000 (00:22 +0000)]
rng: rockchip: Use same compatible as linux

Replace the rockchip,cryptov1-rng compatible with compatibles used in
the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC
device tree from linux.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agogpio: rockchip: Use gpio alias id as gpio bank id
Jonas Karlman [Sat, 17 Feb 2024 00:22:35 +0000 (00:22 +0000)]
gpio: rockchip: Use gpio alias id as gpio bank id

The U-Boot driver try to base the gpio bank id on the gpio-ranges prop
and fall back to base the bank id on the node name. However, the linux
driver try to base the bank id on the gpio alias id and fall back on
node order.

This can cause issues when SoC DT is synced from linux and gpioX@ nodes
has been renamed to gpio@ and gpio-ranges or a SoC specific alias has
not been assigned.

Try to use the gpio alias id as first fallback when a gpio-ranges prop
is missing to ease sync of updated SoC DT. Keep the current fallback on
node name as a third fallback to not affect any existing unsynced DT.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328: Fix loading FIT from SD-card when booting from eMMC
Jonas Karlman [Sat, 17 Feb 2024 00:22:34 +0000 (00:22 +0000)]
rockchip: rk3328: Fix loading FIT from SD-card when booting from eMMC

When RK3328 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there is a fallback to
read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card will fail:

  U-Boot SPL 2024.04-rc1 (Feb 05 2024 - 22:18:22 +0000)
  Trying to boot from MMC1
  mmc_load_image_raw_sector: mmc block read error
  Trying to boot from MMC2
  Card did not respond to voltage select! : -110
  spl: mmc init failed with error: -95
  Trying to boot from MMC1
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328-orangepi-r1-plus: Update defconfig
Jonas Karlman [Sat, 17 Feb 2024 00:22:33 +0000 (00:22 +0000)]
rockchip: rk3328-orangepi-r1-plus: Update defconfig

Update defconfig for rk3328-orangepi-r1-plus boards with new defaults.

Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.

Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.

Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.

Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.

Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.

Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
&gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.

Add PHY_ROCKCHIP_INNO_USB2=y option to support the onboard USB PHY.

Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.

Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.

Also add missing device tree files to MAINTAINERS file.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328-nanopi-r2: Update defconfig
Jonas Karlman [Sat, 17 Feb 2024 00:22:32 +0000 (00:22 +0000)]
rockchip: rk3328-nanopi-r2: Update defconfig

Update defconfig for rk3328-nanopi-r2* boards with new defaults.

Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.

Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.

Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.

Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.

Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.

Add DM_ETH_PHY=y, PHY_GIGE=y, PHY_MOTORCOMM=y, PHY_REALTEK=y and remove
&gmac2io to support reset of onboard ethernet PHYs. Also add DM_MDIO=y
to ensure device tree props is used by motorcomm PHY driver.

Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.

Add DM_REGULATOR_GPIO=y and SPL_DM_REGULATOR_GPIO=y to support the
regulator-gpio compatible.

Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.

Also add missing device tree files to MAINTAINERS file.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328-rock-pi-e: Update defconfig
Jonas Karlman [Sat, 17 Feb 2024 00:22:31 +0000 (00:22 +0000)]
rockchip: rk3328-rock-pi-e: Update defconfig

Update defconfig for rk3328-rock-pi-e with new defaults.

Remove the xPL_DRIVERS_MISC=y option, no misc driver is used in xPL.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.

Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.

Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands.

Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.

Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.

Add DM_MDIO=y to ensure device tree props can be used by PHY driver.

Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.

Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.

Also add myself as a reviewer for this board.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
9 months agorockchip: rk3328-roc-cc: Update defconfig
Jonas Karlman [Sat, 17 Feb 2024 00:22:30 +0000 (00:22 +0000)]
rockchip: rk3328-roc-cc: Update defconfig

Update defconfig for rk3328-roc-cc with new defaults.

Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.

Add CONFIG_SPL_FIT_SIGNATURE=y to let SPL verify an auto generated hash
of FIT images. This help indicate if there is an issue loading any of
the images to DRAM or SRAM. Also add LEGACY_IMAGE_FORMAT=y to keep
support for scripts.

Remove SPL_I2C=y and SPL_PMIC_RK8XX=y, the related i2c and pmic nodes is
not included in the SPL fdt.

Add CMD_GPIO=y and CMD_REGULATOR=y to add the helpful gpio and regulator
commands. Also add CMD_POWEROFF=y to be able to use the poweroff command.

Add ROCKCHIP_EFUSE=y and remove NET_RANDOM_ETHADDR=y, ethaddr and
eth1addr is set based on cpuid read from eFUSE.

Add SPL_DM_SEQ_ALIAS=y option to use alias sequence number in SPL.

Add DM_ETH_PHY=y, PHY_MOTORCOMM=y and PHY_REALTEK=y to support common
ethernet PHYs.

Remove REGULATOR_PWM=y, the pwm-regulator compatible is not used.

Add RNG_ROCKCHIP=y and DM_RNG=y options to support the onboard random
generator.

Also add missing device tree file to MAINTAINERS and add myself as a
reviewer for this board.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>