Andre Przywara [Tue, 7 Feb 2023 15:21:04 +0000 (15:21 +0000)]
arm: semihosting: replace inline assembly with assembly file
So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about one instruction, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
pointer land in the right registers.
This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembly file.
This is much more readable and robust.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Devarsh Thakkar [Mon, 6 Feb 2023 11:34:51 +0000 (17:04 +0530)]
am62a7: dts: Enable full 4GB LPDDR4
AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
but only 2GB was enabled early.
Enable full 4GB memory by updating the latter 2GB memory region
which gets mapped to 0x0880000000 i.e. DDR16SS0_SDRAM as referred in
Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].
Kunihiko Hayashi [Tue, 28 Feb 2023 02:37:09 +0000 (11:37 +0900)]
ARM: dts: uniphier: Sync DT with Linux v6.2
Synchronize devicetree sources with Linux v6.2.
- Use GIC interrupt definitions
- Add reg properties in USB-glue and SoC-glue node
- Fix node names to follow the generic names list in DT specification
- Add L2 cache and AHCI nodes
- Update nand and pcie nodes
- And some trivial fixes
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Marek Vasut <marex@denx.de>
Christophe Leroy [Sun, 26 Feb 2023 09:44:09 +0000 (10:44 +0100)]
powerpc, mpc83xx: Remove CONFIG_ELBC_BRx_ORx
Commit fe7d654d04 ("mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to
Kconfig") converted CONFIG_SYS_{BRx/ORx}_PRELIM to Kconfig by
implementing a fine-grained selection of every bit in Kconfig.
But commit c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to
Kconfig") reworked it so that you now just have to provide the raw
value of each register in Kconfig. However, all fine-grained
Kconfig items remained allthough they are not used anymore.
Remove them all.
Fixes: c7fad78ec0 ("Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Manorit Chawdhry [Fri, 24 Feb 2023 05:07:49 +0000 (10:37 +0530)]
configs: j7200: Merge HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Acked-by: Andrew Davis <afd@ti.com>
Manorit Chawdhry [Fri, 24 Feb 2023 05:07:48 +0000 (10:37 +0530)]
configs: j721s2: merge HS and non-HS defconfigs
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Acked-by: Andrew Davis <afd@ti.com>
Marc Zyngier [Tue, 14 Feb 2023 13:38:14 +0000 (21:38 +0800)]
arm64: Reduce PT size estimation complexity
count_required_pts()'s complexity is high if mappings are not using the
largest possible block size (due to some other requirement such as tracking
dirty pages, for example).
Let's switch to a method that follows the pattern established with
the add_map() helper, and make it almost instantaneous instead of
taking a large amount of time if 2MB mappings are in use instead of
1GB.
Marc Zyngier [Tue, 14 Feb 2023 13:38:13 +0000 (21:38 +0800)]
arm64: Reduce add_map() complexity
In the add_map() function, for each level it populates, it iterates from
the root of the PT tree, making it ineficient if a mapping needs to occur
past level 1.
Instead, replace it with a recursive (and much simpler) algorithm
that keeps the complexity as low as possible. With this, mapping
512GB at level 2 goes from several seconds down to not measurable
on an A55 machine.
We keep the block mappings at level 1 for now though.
Sergei Antonov [Mon, 13 Feb 2023 17:34:36 +0000 (20:34 +0300)]
timer: fttmr010: return a previously deleted driver now ported to DM
The fttmr010 timer driver was deleted by
commit 29fc6f24926e ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c
Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.
This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.
Memory used to hold the page tables is allocated from the top of RAM
with no prior initialization and could therefore hold invalid data. As
invalidate_dcache_all() will be called before the MMU has been
initialized and as that function relies indirectly on the page tables
when using CMO_BY_VA_ONLY, these must be in a valid state from their
allocation.
Marc Zyngier [Wed, 8 Feb 2023 20:54:27 +0000 (04:54 +0800)]
arm: cpu: Add optional CMOs by VA
Exposing set/way cache maintenance to a virtual machine is unsafe, not
least because the instructions are not permission-checked but also
because they are not broadcast between CPUs. Consequently, KVM traps and
emulates such maintenance in the host kernel using by-VA operations and
looping over the stage-2 page-tables. However, when running under
protected KVM, these instructions are not able to be emulated and will
instead result in an exception being delivered to the guest.
Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select
this option and perform by-VA cache maintenance instead of using the
set/way instructions.
Tom Rini [Fri, 3 Mar 2023 17:48:23 +0000 (12:48 -0500)]
Merge branch '2023-03-02-kconfig-and-CONFIG-cleanups' into next
- Partial merge of a series of mine to select some framework options
that shouldn't be prompted for (and remove some unused code related to
that), and a partial merge of a series from Simon to remove some dead
code and address various CONFIG_IS_ENABLED/IS_ENABLED issues in code.
Simon Glass [Wed, 22 Feb 2023 16:34:12 +0000 (09:34 -0700)]
test: Tidy up sandbox handling in test-main
This is pretty messy at present since it relies on a SPL_SANDBOX option
that does not exist. Use the normal options instead, so that it will work
with split config.
Simon Glass [Wed, 22 Feb 2023 16:34:06 +0000 (09:34 -0700)]
sandbox: Tidy up I2C options
At present we enable the sandbox I2C driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 22 Feb 2023 16:34:04 +0000 (09:34 -0700)]
sandbox: Tidy up RTC options
At present we enable the sandbox RTC driver for all builds. Add a separate
Kconfig option to control this, so that it can be disabled in TPL, where
it is not needed.
Chunfeng Yun [Fri, 17 Feb 2023 09:04:10 +0000 (17:04 +0800)]
usb: xhci-mtk: modify the SOF/ITP interval for mt8195
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we shall set the
accurate interval according to 48Mhz for those controllers.
Note:
The first controller no need set it, but if set it, shall change
tphy's pll at the same time.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Marek Vasut <marex@denx.de>
Chunfeng Yun [Fri, 17 Feb 2023 09:04:09 +0000 (17:04 +0800)]
phy: phy-mtk-tphy: add support mt8195
The T-PHY controller is designed to use use PLL integer mode, but
in fact use fractional mode for some ones on mt8195 by mistake,
this causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve signal
quality.
Marek Vasut [Thu, 23 Feb 2023 16:32:43 +0000 (17:32 +0100)]
usb: dwc3-meson-g12a: Select PHY instead of imply PHY
Imply means you can turn off the option and expect things to work
- "it's a good idea to have X enabled" is when to use imply
- "you must have X for Y to work" is when to use select
Use "select" here.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Tom Rini [Thu, 16 Feb 2023 03:36:55 +0000 (22:36 -0500)]
s5p: Remove empty arch_misc_init
We don't need to provide an empty arch_misc_init function here, we can
just not enable the hook.
Cc: Stefan Bosch <stefan_b@posteo.net> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Tom Rini [Thu, 16 Feb 2023 03:36:53 +0000 (22:36 -0500)]
mvebe: Drop ARCH_MISC_INIT from alleycat 5
In this platform, arch_misc_init doesn't perform any real function. The
call to get_soc_type_rev has no lasting side effects.
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Tom Rini [Thu, 16 Feb 2023 03:36:52 +0000 (22:36 -0500)]
imx9: Remove ARCH_MISC_INIT
We don't need an empty function, we can just not enable the hook we
don't use.
Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Thu, 16 Feb 2023 03:36:51 +0000 (22:36 -0500)]
common: Make ARCH_EARLY_INIT_R be selected only
As platforms which require this hook need this hook enabled, in order to
function, or do not need this hook, it doesn't make sense to prompt the
user. As all platforms that need this hook now select the symbol, remove
the prompt text.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 16 Feb 2023 03:36:50 +0000 (22:36 -0500)]
arm: rk3368: Select ARCH_EARLY_INIT_R when used
On the lion and evb-px5 platforms, we need this function, so select it.
Cc: Andy Yan <andy.yan@rock-chips.com> Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com> Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tom Rini [Thu, 16 Feb 2023 03:36:49 +0000 (22:36 -0500)]
arm: zynq: Move to select'ing ARCH_EARLY_INIT_R if we have FPGA
The function arch_early_init_r only does anything on these platforms if
we have FPGA (or SPL and SPL_FPGA) enabled, so move the logic to select
based on that.
Cc: Michal Simek <michal.simek@amd.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 16 Feb 2023 03:36:47 +0000 (22:36 -0500)]
common/Kconfig: Reword text for BOARD_TYPES
While it is true that for some Samsung platforms, we call
get_board_type() the main usage of this CONFIG switch is to enable
board_types in global data, which is then used by various platforms.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Pali Rohár [Fri, 3 Feb 2023 20:41:45 +0000 (21:41 +0100)]
arm: mvebu: Define env_sf_get_env_addr() also for Proper U-Boot
Proper U-Boot moves SPI0 CS0 Flash mapping from 0xD4000000 to 0xF4000000
and change its size from 64 MB to 8 MB. Definitions are already in
MBUS_SPI_BASE/MBUS_SPI_SIZE macros. So define these macros also for SPL
build, use them in env_sf_get_env_addr() function and move this function
from spl.c to cpu.c to be available in Proper U-Boot too.
Pali Rohár [Sat, 21 Jan 2023 23:09:04 +0000 (00:09 +0100)]
arm: mvebu: clearfog: Add defconfig for SATA booting
This new clearfog_sata_defconfig file is copy of existing
clearfog_defconfig file and changed to instruct build system to
generate final kwbimage for SATA booting.
This change is more readable via git option --find-copies-harder.
Pali Rohár [Sat, 21 Jan 2023 20:42:08 +0000 (21:42 +0100)]
arm: mvebu: db-88f6820-amc: Add defconfig for NAND booting
This new db-88f6820-amc_nand_defconfig file is copy of existing
db-88f6820-amc_defconfig file and changed to instruct build system to
generate final kwbimage for NAND booting. It was done by adding options:
Pali Rohár [Tue, 10 Jan 2023 22:13:01 +0000 (23:13 +0100)]
arm: mvebu: Fix description of MVEBU_SPL_BOOT_DEVICE_(SPI|MMC) options
MVEBU_SPL_BOOT_DEVICE_SPI is for NOR flash. Either serial or parallel. Not
for general serial/SPI devices. The correct name should be BOOT_DEVICE_NOR
but name SPI is already used in mkimage config format which we do not want
to change for compatibility reasons.
MVEBU_SPL_BOOT_DEVICE_MMC is for MMC and SD compatible devices. Not for
SDIO devices. In most cases used for eMMC or SD card.
Pali Rohár [Tue, 10 Jan 2023 22:09:15 +0000 (23:09 +0100)]
arm: mvebu: Add support for generating PEX kwbimage
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_PEX which instruct
make to generate kwbimage with PEX header. This image is used for booting
from PCI Express device which is in the Root Complex mode.
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then start
executing U-Boot proper.
Pali Rohár [Tue, 10 Jan 2023 21:55:21 +0000 (22:55 +0100)]
arm: mvebu: Add support for generating NAND kwbimage
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct
make to generate kwbimage with NAND header. This image is used for booting
from NAND flash (either SPI or parallel).
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and
executes U-Boot proper.
To generate correct kwbimage NAND header, it is required to set following
Kconfig options:
Pali Rohár [Sat, 21 Jan 2023 19:11:28 +0000 (20:11 +0100)]
tools: kwbimage: Add support for creating an image with no data
This change add support for mkimage's -s option to kwbimage format. It will
create an kwbimage with empty data part of image (data part would contain
only required 32-bit checksum). mkimage's -s option is indicated by skipcpy
flag and it is basically in conflict with mkimage's -d (datafile) option.
"Empty" kwbimage with no data can still contain headers. For example it can
contain binary executable header which is copied by BootROM into L2SRAM.
This is useful for example for small images which can do not require DDR
RAM and can be run in L2SRAM (which do not require any initialization).
Pali Rohár [Sat, 21 Jan 2023 19:09:26 +0000 (20:09 +0100)]
tools: mkimage: Do not try to open datafile when it is skipped
When mkimage was instructed to skip datafile via option -s then do not try
to validate or open datafile as it does not have to exist or to be
specified via -d option.
This change allows to use -s option for skipping datafile when -d option
for datafile was not specified.
Pali Rohár [Sun, 8 Jan 2023 22:28:39 +0000 (23:28 +0100)]
tools: mkimage: Print human readable error when -d is not specified
When asking mkimage to create a new image file and option -d is not
specified then mkimage show human unfriendly error message:
mkimage: Can't open (null): Bad address
Without debugger it is hard to debug what is the issue. Function open() is
being called with file name set to NULL. So add a check for this and if it
happens then show human readable message that option -d was not specified.
Pali Rohár [Wed, 18 Jan 2023 20:42:40 +0000 (21:42 +0100)]
tools: kwbimage: Add support for XIP SPI/NOR images
Marvell BootROM can execute SPI images directly from NOR (either SPI/serial
or parallel) without copying them to DDR RAM. This is know at XIP - execute
in place. To achieve that, destination address in kwbimage must be set to
0xFFFFFFFF and execute address to the offset in bytes from the beginning of
NOR memory.
Kirkwood and Dove which use kwbimage v0 format and have SPI address space
mapped to physical memory at 0xE8000000-0xEFFFFFFF by BootROM.
Armada SoCs use kwbimage v1 format and have SPI address space mapped to
physical memory at 0xD4000000-0xD7FFFFFF and Device bus address space (used
for parallel NOR) at 0xD8000000-0xDFFFFFFF.
Add support for generating XIP kwbimages by mkimage -x flag and mark xflag
as valid option in kwbimage.c.
Pali Rohár [Sat, 21 Jan 2023 19:05:43 +0000 (20:05 +0100)]
tools: mkimage: Do not fill legacy_img_hdr for non-legacy XIP images
Skip filling legacy_img_hdr structure for XIP images which do not use
legacy_img_hdr structure header. Adding unwanted header to other image
formats, like kwbimage cause generation of broken image.
Secure boot header signature is calculated from the image header with
zeroed header checksum. Calculation is done in add_secure_header_v1()
function. So after calling this function no header member except
main_hdr->checksum can be modified. Commit 2b0980c24027 ("tools: kwbimage:
Fill the real header size into the main header") broke this requirement as
final header size started to be filled into main_hdr->headersz_* members
after the add_secure_header_v1() call.
Fix this issue by following steps:
- Split header size and image data offset into two variables (headersz and
*dataoff).
- Change image_headersz_v0() and add_binary_header_v1() functions to return
real (unaligned) header size instead of image data offset.
- On every place use correct variable (headersz or *dataoff)
After these steps variable headersz is correctly filled into the
main_hdr->headersz_* members and so overwriting them in the end of the
image_create_v1() function is not needed anymore. Remove those overwriting
which effectively reverts changes in problematic commit without affecting
value in main_hdr->headersz_* members and makes secure boot header
signature valid again.
Fixes: 2b0980c24027 ("tools: kwbimage: Fill the real header size into the main header") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sun, 29 Jan 2023 13:33:36 +0000 (14:33 +0100)]
tools: kwbimage: Fix generating secure boot data image signature
Secure boot data image signature is calculated from the data image without
trailing 4-bit checksum. Commit 37cb9c15d70d ("tools: kwbimage: Simplify
aligning and calculating checksum") unintentionally broke this calculation
when it increased payloadsz variable by 4 bytes which was propagated also
into the add_secure_header_v1() function. Fix this issue by decreasing size
of buffer by 4 bytes from which is calculated secure boot data image
signature.
Pali Rohár [Sun, 29 Jan 2023 12:17:21 +0000 (13:17 +0100)]
tools: kwbimage: Rename imagesz to dataoff
Variable imagesz in functions image_create_v0(), image_create_v1() and
kwbimage_set_header() stores offset to data from the beginning of the main
header. So it is not image size.
Pali Rohár [Sun, 29 Jan 2023 12:08:10 +0000 (13:08 +0100)]
tools: kwbimage: Simplify add_secure_header_v1()
To make add_secure_header_v1() function more readable, call it directly
with arguments: header pointer with header size and data image pointer with
data image size. No functional change.
Pali Rohár [Sun, 8 Jan 2023 15:22:34 +0000 (16:22 +0100)]
tools: kwbimage: Add support for dumping NAND_BLKSZ for v0 images
In Dove functional specification, which use kwbimage v0, is also defined
nand block size field. So dump NAND_BLKSZ also for v0 images.
In Kirkwood functional specification, which also use kwbimage v0, this
field is not defined. So when it is zero and Kirkwood is detected, do not
dump it.
Fixes: f76ae2571fe0 ("tools: kwbimage: Add support for dumping extended and binary v0 headers") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sat, 14 Jan 2023 12:42:14 +0000 (13:42 +0100)]
tools: kwbimage: Fix dumping NAND_BLKSZ
kwbimage nandblocksize field is in 64 kB unit, but NAND_BLKSZ command
expects it in bytes. So do required unit conversion.
Also zero value in nandblocksize field has special meaning. When this field
is set to zero, the default block size is used. This default size is
defined by the NAND flash page size (16 KB for a 512B page or small page
NAND and 64 KB for a large page NAND flash).
Pali Rohár [Sat, 14 Jan 2023 13:46:09 +0000 (14:46 +0100)]
tools: kwbimage: Fix dumping NAND_BADBLK_LOCATION
Value 0x0 for NAND_BADBLK_LOCATION/nandbadblklocation means that BBI is on
the first or second page and value 0x1 means that BBI is on the last page.
This indicates also NAND Flash Technology, value 0x0 is SLC NAND and value
0x1 is MLC NAND.
Therefore we need to dump NAND_BADBLK_LOCATION also when it is zero.
Note that in v0 images, nandbadblklocation field overlaps with ddrinitdelay
field in one union. ddrinitdelay is used in Kirkwood and nandbadblklocation
is used in Dove. For Dove images is_v0_ext should be set, so use it to
distinguish if nandbadblklocation is available or not. In v1 images there
is always nandbadblklocation field.
For 32-bit Armada boards which use SPL we can determinate boot device from
existing MVEBU_SPL_BOOT_DEVICE_* option. For all other boards (e.g. 64-bit
Armada) default option still needs to be set manually.
Pali Rohár [Sun, 8 Jan 2023 13:01:03 +0000 (14:01 +0100)]
cmd: mvebu/bubt: Set correct default image name for 32-bit Armada SoCs
32-bit Armada SoCs uses u-boot binary packed in kwbimage format. Name of
the image is in CONFIG_BUILD_TARGET option. So use it as a default option
in Kconfig.
projects / u-boot.git / log