Lukasz Majewski [Wed, 13 Feb 2019 21:46:48 +0000 (22:46 +0100)]
ARM: DTS: Update pcm052 based dts files (bk4r1/pcm052)
This commit provides update and renames the bk4r1.dts to vf610-bk4r1.dts
file with more on SoC HW description.
The pcm052.dts has been renamed to vf610-pcm052.dts as well.
Moreover, a new vf610-pcm052.drsi file has been introduced
to reuse the common code between devices based on Phytec's
pcm052 modules.
Ported from Linux kernel - v4.20 (tag)
Lukasz Majewski [Wed, 13 Feb 2019 21:46:41 +0000 (22:46 +0100)]
vybrid: clock: Provide enable_i2c_clk() function for Vybrid
Provide function to enable I2C clocks for vf610 - in the generic code.
This function overrides the default weak function implementation (which
only returns 1).
Tom Rini [Fri, 12 Apr 2019 16:34:44 +0000 (12:34 -0400)]
Merge git://git.denx.de/u-boot-marvell
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
board support (Chris)
Tom Rini [Fri, 12 Apr 2019 16:22:43 +0000 (12:22 -0400)]
Merge branch '2019-04-11-ti-master-imports'
- Improve Keystone 3 SoC support (DMA, TI SCI)
- Improve Keystone 2 SoC support (PHY fixes on various platforms)
- Improve am335x families (new platforms, more boot mode options in SPL
via DM).
- General DaVinci, OMAP5 fixes.
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
We are facing issues in the driver since SPI NOR framework has moved
on SPI MEM framework, and SPI NAND framework is not running properly
with the current driver.
To be able to solve issues met on SPI NOR Flashes and to be able to
support SPI NAND Flashes, the driver has been reworked. We are now using
exec_op ops instead of using xfer ops.
Thanks to this rework, the driver has been successfully tested with:
- mx66l51235l SPI NOR Flash on stm32f746 SOC
- n25q128a SPI NOR Flash on stm32f769 SOC
- mx66l51235l SPI NOR Flash on stm32mp1 SOC
- mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC
Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Patrick Delaunay [Fri, 12 Apr 2019 12:38:28 +0000 (14:38 +0200)]
ARM: dts: Add STMFX gpio expander support for stm32mp157c-ev1
Adds alias to set the pincontrol seq id.
For STMFX gpio expander, force sequence number after
the last bank (GPIOZ) to avoid conflict between STM32MP and STMFX
gpio bank sequence number.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 11 Mar 2019 10:13:16 +0000 (11:13 +0100)]
config: stm32mp15: Enable STMFX support
Activate PINCTRL_STMFX and needed part for generic pincontrol
PINCTRL_FULL, PINCONF. Increase pre-reloc memory for MALLOC
(needed for each DM pinconfig node).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Tue, 12 Feb 2019 15:50:40 +0000 (16:50 +0100)]
Board: stm32mp1: Add supply current boot information
For DK1/DK2 boards, check if power supply provides enough current
to allow the board to boot correctly.
ADC@0 channel 18 and 19 are connected to USB type-C CC1 and CC2
signals. The table below shows the behavior for different range of
CC1 or CC2:
range | power supply | red led | console message
(Volts) | (Amps) | blinks |
--------------|--------------|---------|-----------------------------------
[2.10 - 1.23[ | 3 | NO | NO
[1.23 - 0.66[ | 1.5 | 3 times | WARNING 1.5A power supply detected
[0.66 - 0] | 0.5 | 2 times | WARNING 500mA power supply detected
If detected current is < 3A, red led is kept ON after blinking.
Patrice Chotard [Tue, 12 Feb 2019 15:50:38 +0000 (16:50 +0100)]
ARM: dts: stm32: Synchronize DT with kernel one
This patch synchronizes U-boot DT with kernel one
This is based on https://patchwork.kernel.org/cover/10797115/
This patch adds initial support of STM32MP157 discovery boards:
- Add support of stm32mp157a discovery1 board (part number: STM32MP157A-DK1).
This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios)
and 512MB of DDR3. Several connections are available on this boards:
4*USB2.0, 1*USB2.0 typeC, SDcard, RJ45, HDMI, Arduino connector, ...
- Add support of stm32mp157c discovery2 board (part number: STM32MP157C-DK2).
This board is a "super-set" of stm32mp157a-dk1. A display panel (otm8009a)
and Murata wifi/BT combo is added.
Add functions to read/update the non volatile memory of STPMIC1
(8 bytes-register at 0xF8 address) and allow access
with fuse command (bank=1, word > 0xF8).
Patrick Delaunay [Fri, 12 Apr 2019 09:55:46 +0000 (11:55 +0200)]
stm32mp1: add command poweroff
Activate the command poweroff by default for STM32MP1:
- with PCSI from TF-A for trusted boot
- with PMIC sysreset request for basic boot (SYSRESET_POWER)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Alignment with STPMIC1 datasheet
s/MAIN_CONTROL_REG/MAIN_CR/g
s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
s/MASK_RESET_LDOS/LDOS_MRST_CR/g
s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
s/USB_CTRL_REG/BST_SW_CR/g
s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
SW impact for Rev 1.2 of STPMIC1 in U-Boot:
Buck converters output voltage change for Buck1
=> Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V
(see STPMIC1 datasheet / chapter 5.3 Buck converters)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:24 +0000 (17:01 +0100)]
stm32mp1: add syscfg initialization
Initialize the system configuration for basic boot
- update interconnect setting
- disable pull-down for boot pin
- enable High Speed Low Voltage Pad mode for SPI, SDMMC, ETH, QSPI
- activate I/O compensation
Done by SSBL = TF-A for trusted boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:21 +0000 (17:01 +0100)]
stm32mp1: update memory layout
Update the memory layout to be aligned with other platform and avoid
overlap with 32MB Linux kernel (multiv7 image).
+ Kernel => 32MiB offset = 0xC2000000
and increase the bootm size to 32MiB
+ FDT => 64MiB offset = 0xc4000000
+ SCRIPT => 65Mib offset = 0xc4100000
+ PXESCRIPT => 66Mib offset = 0xc4200000
+ SPLASHIMAGE => 67Mib offset = 0xc4300000
+ RAMDISK => 68Mib offset = 0xc4400000
(not limited size)
In sources/boot/u-boot/doc/README.distro
+ kernel_addr_r: A size of 16MB for the kernel is likely adequate.
+ pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate.
+ fdt_addr_r: A size of 1MB for the FDT/DTB seems reasonable.
+ ramdisk_addr_r: It is recommended that this location be highest in RAM
out of fdt_addr_, kernel_addr_r, and ramdisk_addr_r,
so that the RAM disk can vary in size and use any
available RAM.
+ pxefile_addr_r: A size of 1MB for extlinux.conf is more than adequate.
+ scriptaddr: A size of 1MB for extlinux.conf is more than adequate.
For suggestions on memory locations for ARM systems, you must follow
the guidelines specified in Documentation/arm/Booting
in the Linux kernel tree.
And in sources/linux-stm32mp/Documentation/arm/Booting
The zImage may also be placed in system RAM and called there. The
kernel should be placed in the first 128MiB of RAM. It is recommended
that it is loaded above 32MiB in order to avoid the need to relocate
prior to decompression, which will make the boot process slightly
faster.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:15 +0000 (17:01 +0100)]
stm32mp1: cosmetic cleanup Kconfig
Cosmetic cleanup in mach-stm32mp Kconfig
- remove duplicated SPL_DRIVERS_MISC_SUPPORT
- update help for TARGET_STM32MP1
- set value for NR_DRAM_BANKS
- remove one comment as DEBUG_UART is deactivated by default
- include board Kconfig at the end of the file
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 27 Feb 2019 16:01:12 +0000 (17:01 +0100)]
stm32mp1: update boot mode management
- export the function get_bootmode() and reused it in spl code
- manage uart instance by alias (prepare v4.19 binding)
- solve issue on nand instance
- restore console for uart boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 12 Feb 2019 10:44:41 +0000 (11:44 +0100)]
stm32mp1: display board information
Implement checkboard() function to display
- the boot chain used: basic or trusted
- the board compatible in device tree
- the board identifier and revision, saved in OTP59 for ST boards
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Faiz Abbas [Fri, 5 Apr 2019 08:48:46 +0000 (14:18 +0530)]
mmc: omap_hsmmc: Set 3.3V for IO voltage
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Tom Rini [Tue, 19 Mar 2019 11:14:37 +0000 (07:14 -0400)]
ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option. Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.
Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
Faiz Abbas [Mon, 18 Mar 2019 08:24:34 +0000 (13:54 +0530)]
net: ti: cpsw-common: Isolate getting syscon address from assigning macid
ti_cm_get_macid() is used to get a syscon node from the dt, read the
efuse address and then assign the macid read from the address. Divide
these two steps into separate functions one of which can be called from
ofdata_to_platdata() while the other can be called from _probe(). This
ensures that platdata can be assigned statically in a board file when
OF_CONTROL is not enabled. Also add a macid_sel_compat in private data
to get information about the macid byte placement.
Faiz Abbas [Mon, 18 Mar 2019 08:24:33 +0000 (13:54 +0530)]
net: ti: cpsw: Convert cpsw_platform_data to a pointer in cpsw_priv
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it
dynamically and assign it as a part of eth_pdata. This helps in
isolating platform data handling and implementing platdata for SPL
in a board file.
Faiz Abbas [Mon, 18 Mar 2019 08:24:32 +0000 (13:54 +0530)]
net: ti: cpsw: Move cpsw_phy_sel() to _probe()
cpsw_phy_sel() is a configuration step that should not be in
ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data
structure so that it is accessible in _probe. Then move the call of
cpsw_phy_sel() to _probe.
armv7R: K3: am654: Trigger panic on DDR init failures
When initializing DDR from R5 SPL trigger U-Boot's panic facility
rather than simply returning from the board init function as there
is little point continuing code execution. Further, as panic implies
a board reset, so using it might potentially allow to recover from
this error in certain cases such as when the init failure was caused
by a temporary glitch of some sorts.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Fri, 8 Mar 2019 06:17:35 +0000 (11:47 +0530)]
board: ti: am65x: Enable fixing up msmc sram node
Create a ft_board_setup() api that gets called as part of
DT fixup before jumping to kernel. In this ft_board_setup()
call fdt_fixup_msmc_ram that update msmc sram node.
Lokesh Vutla [Fri, 8 Mar 2019 06:17:34 +0000 (11:47 +0530)]
arm: k3: Add support for updating msmc dt node
Certain parts of msmc sram can be used by DMSC or can be
marked as L3 cache. Since the available size can vary, changing
DT every time the size varies might be painful. So, query this
information using TISCI cmd and fixup the DT for kernel.
Fixing up DT does the following:
- Create a sram node if not available
- update the reg property with available size
- update ranges property
- loop through available sub nodes and delete it if:
- mentioned size is out if available range
- subnode represents l3 cache or dmsc usage.
Lokesh Vutla [Fri, 8 Mar 2019 06:17:32 +0000 (11:47 +0530)]
firmware: Add support for querying msmc memory
DMSC can use certain amount of msmc memory available in the
system. Also certain part of msmc memory can be marked as L3
cache using board config. But users might not know what size
is being used and the remaining available msmc memory. In order
to fix this TISCI protocol provides a messages that can query
the available msmc memory in the system. Add support for this
message.
board: ti: dra71: Add pinmux settings for NAND on DRA71x EVM
By default VOUT3 occupies the pins required for NAND. Therefore, create
a seperate entry that can be use to reconfigure these pins to work for
NAND.
On the EVM SWITCH 8 pins 0 and 1 will be used to determine if NAND is
enabled or not. For NAND to be selected pin 0 should be on and pin 1
should be off. Any other combination will assume NAND shouldn't be
enabled.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Adam Ford [Tue, 26 Feb 2019 03:53:47 +0000 (21:53 -0600)]
ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATA
With the memory mapping giving us some more avialable RAM, this
updates the da850-evm-u-boot.dtsi to include the serial port, SPI
and Flash nodes along with some dependent nodes in the SPL dtb.
This also removes the platform data initialization code for the
serial port and SPI Flash.
Adam Ford [Tue, 26 Feb 2019 03:53:46 +0000 (21:53 -0600)]
davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit
larger. This patch relocates BSS to SDRAM instead of SRAM which
is similar to how ARMv7 boards (like OMAP2+) do it.
This means two new variables are required:
CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE
CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte
before the location where U-Boot will load.
Martyn Welch [Mon, 25 Feb 2019 15:32:59 +0000 (15:32 +0000)]
env: Don't check CONFIG_ENV_OFFSET_REDUND for SPL build
When booting using an SPL on am335x, if we want to support booting with
the boot ROM loader via USB (which uses RNDIS, making bootp and tftp
calls) we need to enable gadget eth in the SPL to load the main U-Boot
image. To enable CONFIG_SPL_ETH_SUPPORT, we must enable
CONFIG_SPL_ENV_SUPPORT as the environment is used by the eth support, but
we don't actually need to have environment variables saved in the SPL
environment. We do however have environment variables saved in the main
U-Boot image and enable CONFIG_ENV_OFFSET_REDUND (we are storing in raw
NAND). In such instances, even with the build config enabling both
CONFIG_CMD_SAVEENV and CONFIG_CMD_NAND, these options aren't set when
building the SPL, but CONFIG_ENV_OFFSET_REDUND still is.
Don't check this configuration option for SPL builds to enable the above
configuration.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:07 +0000 (12:02 -0500)]
ARM: dts: k2g-ice: add dt node for netcp
This patch adds dt node for DP83867 phy used on K2G ICE board and
also enable netcp device nodes for the board.
EVM hardware spec recommends to add 0.25 nsec delay in the tx
direction and 2.25 nsec delay in the rx direction for internal
delay in the clock path to be on the safer side.
The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode
1. Unfortunately, the phy data manual disallows this. Add
ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to
enable workaround suggested for this incorrect strap setting. This
ensures proper operation of this PHY.
The dts bindings are kept in sync with that from 4.14.y linux
kernel. This required the pinmux device related bindings to be
commented out to allow for compilation.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:05 +0000 (12:02 -0500)]
ARM: dts: k2g-evm: remove unused phy-mode property from phy node
This patch removes the unused phy-mode property from the phy dt node. On
K2G, currently link-interface determines if phy is used or not and is
already set to use rgmii. So this is not needed. Besides phy-mode should
be added to slave interface configuration of the cpsw driver, not in the
phy node.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:04 +0000 (12:02 -0500)]
ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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