Tom Rini [Mon, 15 Mar 2021 12:43:19 +0000 (08:43 -0400)]
Merge tag 'u-boot-stm32-20210312' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
Adam Ford [Sat, 6 Mar 2021 02:48:50 +0000 (20:48 -0600)]
ARM: da850-evm: Fix boot issues from missing SPL_PAD_TO
In a previous attempt to unify config options and remove items
from the whitelist file, SPL items were moved into a section
enabled with CONFIG_SPL_BUILD. Unfortunately, SPL_PAD_TO
is referenced at the head Makefile and uses this define
to create padding of the output file. When it was moved
to CONFIG_SPL_BUILD, it caused boot errors with devices
that are not booting from NOR. Fix the boot issues by moving
SPL_PAD_TO out so it's always.
Fixes: 7bb33e4684aa ("ARM: da850-evm: Unify config options with Kconfig") Signed-off-by: Adam Ford <aford173@gmail.com>
- Some more updates/sync's to A38x DDR3 code (Marek & Pali)
- marvell/ddr/AXP: Some type fixes found in the LTO work (Marek)
- Espressobin: Enable more options (Pali)
- pci-aardvark: Implement workaround for the readback value of
VEND_ID (Paili)
Patrice Chotard [Wed, 24 Feb 2021 12:53:27 +0000 (13:53 +0100)]
arm: stm32mp: Fix compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled
Fix following compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS
are enabled :
arch/arm/mach-stm32mp/cpu.c: In function ‘early_enable_caches’:
arch/arm/mach-stm32mp/cpu.c:223:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_size’
223 | gd->arch.tlb_size = PGTABLE_SIZE;
| ^
arch/arm/mach-stm32mp/cpu.c:224:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’
224 | gd->arch.tlb_addr = (unsigned long)&early_tlb;
| ^
Patrice Chotard [Wed, 24 Feb 2021 12:38:20 +0000 (13:38 +0100)]
board: st: Remove board_early_init_f and board_late_init callbacks for stm32 boards
Remove board_early_init_f() and board_late_init() callbacks for stm32
boards as the corresponding flags (CONFIG_BOARD_LATE_INIT and
CONFIG_BOARD_EARLY_INIT_R) are now disabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Wed, 24 Feb 2021 12:38:19 +0000 (13:38 +0100)]
configs: stm32: Remove BOARD_EARLY_INIT_F and BOARD_LATE_INIT for stm32 boards
These flags was defined and callbacks linked to these flags are empty
and only returning 0.
Remove BOARD_EARLY_INIT_F and BOARD_LATE_INIT flags for these stm32 boards.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Enable support for NVMe disks which can be connected to mPCIe slot via M.2
reduction. Enable btrfs and squashfs filesystems which are used by more
Linux distributions. And enable fsuuid and setexpr commands which can be
useful in scripting.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Sat, 6 Mar 2021 23:00:34 +0000 (00:00 +0100)]
ddr: marvell: axp: fix array types have different bounds warning
The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have
different bounds declared in header files where these variables are also
defined from the ones declared in source files.
This causes the compiler to complain (when building with LTO):
ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match
original declaration
[-Wlto-type-mismatch]
ddr3_patterns_64bit.h:911:5: note: array types have different bounds
ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously
declared here
ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match
original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:167:4: note: array types have different bounds
ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared
here
ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match
original declaration [-Wlto-type-mismatch]
ddr3_axp_vars.h:196:4: note: array types have different bounds
ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared
here
CI managed to trigger this as an error when compiling with LTO for AXP.
Fix this by using values from the header files, which seem to be the
correct ones.
Marek Behún [Thu, 4 Mar 2021 10:23:14 +0000 (11:23 +0100)]
ddr: marvell: axp: align signature of mv_xor_mem_init() with a38x
In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common
XOR definitions, regardless whether we compile for axp or a38x.
But the declaration of this function has a different signature in axp's
xor.h from the one used in a38x' implementation - one parameter is u64
instead of u32. This can result in wrong argument's being passed to that
function on a38x with no one the wiser.
I discovered this when building U-Boot for Turris Omnia with LTO. The
compiler complains about the different signatures being thrown into the
same linking process:
axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match
original declaration [-Wlto-type-mismatch]
67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size,
| ^
a38x/xor.c:165:5: note: type mismatch in parameter 3
165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long
| ^
a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match
type ‘u32’
Fix this by changing the type of the block_size argument in the axp's
implementation and header file to the one used in a38x (and upstream
mv-ddr-marvell).
Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Tue, 2 Mar 2021 10:17:41 +0000 (11:17 +0100)]
ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the
commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot").
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x and ddr3:
3. Manually omit SPDX-License-Identifier changes from this patch as
upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x ddr3 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch is removal of dead code and some fixes with
include files.
Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
At this moment, only page 0 of SPD is being read but to support
smbios, we need to read page 1 also which has more info. In order
to do that, we need to allocate more space.
board: stm32mp1: use CONFIG_SYS_MMC_ENV_DEV when available
Check whether user has explicitly defined the mmc device to use
in mmc_get_env_dev() with CONFIG_SYS_MMC_ENV_DEV.
On STMicroelectronics boards the used mmc device for environment is
the instance of boot device provided by the ROM code; the mmc instance
is configured by alias in device tree. The used partition is defined in
device tree with u-boot,mmc-env-partition = "ssbl".
This patch allows to override this selection for the support of customer
boards without alias; for example when SDMMC1 is not used and ENV in
mmc0=SDMMC2, user can force the value: CONFIG_SYS_MMC_ENV_DEV = 0.
On STMicroelectronics boards, the current behavior is kept with
CONFIG_SYS_MMC_ENV_DEV = -1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Yannick Fertre [Thu, 4 Mar 2021 12:14:36 +0000 (13:14 +0100)]
video: dw_mipi_dsi: update log of dphy_enable
The DSI phy can be turned on from the DSI digital interface in
the dphy_enable() function or from a dedicated DSI phy "wrapper"
in phy_ops->init() function. If the STM32MP1 case, the wrapper
is used then the dphy_enable() "warning" traces are not relevant.
This patch moves these "warning" traces to "debug" traces so
they are still available for DSI phy based on the digital
interface in debug logging mode, but not there in normal mode
for both cases.
Note: The related Linux kernel driver uses a "debug"
message too.
video: stm32: remove all child of DSI bridge when its probe failed
Remove the child device of the STM32 DSI bridge when the driver probe
failed to stop futher probe request on panels used with STMicroelectronics
board (orisetech_otm8009a.c or raydium-rm68200.c driver).
This patch avoid the trace "cannot get reset GPIO" when
STM32MP157 device tree is used on stm32MP151 SOC without DSI support.
In this hw_version value is 0, as DSI bridge is absent and the panel
ofdata_to_platdata is called for each try of panel probe,
the gpio reset pin is requested but after dsi father probe failed).
For the next request, the PANEL ofdata_to_platdata failed as the gpio
is already used.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
configs: stm32mp15: move bootdelay configuration in defconfig
The STM32MP15 boards have no reason to configure bootdelay in stm32mp1.h
as it is already done with CONFIG_BOOTDELAY (default = 2) and in
include/env_default.h.
This patch allows configuration for customers which reuse stm32mp1.h
and reduce the size of the default environment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 25 Feb 2021 12:37:03 +0000 (13:37 +0100)]
stm32mp: stm32prog: replace alias by serial device sequence number
The command "stm32prog serial <dev>" can directly use the device sequence
number of serial uclass as this sequence number is egual to alias when it
exist; this assumption simplify the code and avoid access to gd->fdt_blob
and the device tree parsing.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 25 Feb 2021 12:37:01 +0000 (13:37 +0100)]
stm32mp: stm32prog: Add CONFIG_CMD_STM32PROG_SERIAL and _USB
Add CONFIG_CMD_STM32PROG_SERIAL and CONFIG_CMD_STM32PROG_USB to
independently select the support of UART or USB communication for
STM32CubeProgrammer.
For serial boot over UART, user can deactivate CONFIG_CMD_STM32PROG_SERIAL
to use U-Boot console of binary loaded by UART (for board bring-up for
example).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Thu, 25 Feb 2021 10:49:28 +0000 (11:49 +0100)]
board: st: remove the nand MTD configuration for NOR boot in stm32mp1 board
Since commit d5d726d3cc47 ("configs: stm32mp1: only support SD card after
NOR in bootcmd_stm32mp"), the stm32mp1 boards only support SD card after
NOR boot device, so the MTD partitions for nand0 or spi-nand0 are useless
(no need of "UBI" partition in nand0 or spi-nand0).
This patch removes these nand MTD update for nor boot and simplify nand0
and spi-nand0 support (remove the mtd_boot variable).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrick Delaunay [Wed, 24 Feb 2021 10:19:46 +0000 (11:19 +0100)]
configs: stm32mp1_trusted_defconfig rely on SCMI support
Enable SCMI clock and reset domain support for stm32mp1 platform
and ARM SMC mailbox driver used as communication channel for
SCMI messages between non-secure world and secure SCMI server.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Etienne Carriere [Wed, 24 Feb 2021 10:19:42 +0000 (11:19 +0100)]
clk: stm32mp1: gets root clocks from fdt
This change makes stm32mp1 clock driver to get the root clocks
reference from the device node in the FDT rather than fetching
straight these clocks by their name. Driver now stores the
clock reference and use it to know if a root clock is present,
get its rate or gets its related udevice reference.
Define in the RCC clock provider node which root clocks the driver
depends on. These are root oscillators, which may be present or
not, upon FDT content.
This update binding is introduced in Linux kernel device tree by patch
"ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15"
This patch is a preliminary step for SCMI support of stm32mp15
boards with trusted boot chain, based on TF-A or OP-TEE.
Patrice Chotard [Wed, 20 Jan 2021 13:42:04 +0000 (14:42 +0100)]
mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write()
In case of big area read/write on spi nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and
spinand_mtd_write() to ensure that watchdog is reset.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Wed, 20 Jan 2021 13:42:03 +0000 (14:42 +0100)]
mtd: nand: Add WATCHDOG_RESET() in nanddev_mtd_erase()
In case of big area erased on nand, watchdog timeout may occurs.
To fix that, add WATCHDOG_RESET() in nanddev_mtd_erase() to ensure that
watchdog is reset.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Wed, 20 Jan 2021 13:42:02 +0000 (14:42 +0100)]
spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo()
In case of reading large area and memory-map mode is misconfigured
(memory-map size declared lower than the real size of the memory chip)
watchdog can be triggered.
Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it.
Issue reproduced with stm32mp157c-ev1 board and memory map size set to
1, with following command:
sf read 0xC0000000 0 0x4000000
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Chunfeng Yun [Wed, 3 Mar 2021 08:07:05 +0000 (16:07 +0800)]
usb: mtu3: flush cache for next GPD
When flush cache of the current GPD and resume QMU, the controller
will try to access the next GPD after processing the current one,
if not flush the next GPD, the controller may get wrong GPD status.
Simon Glass [Tue, 23 Feb 2021 10:35:42 +0000 (05:35 -0500)]
x86: Select advanced Intel code only if allowed
At present most of the Intel-specific code is built on all devices, even
those which don't have software support for the features provided there.
This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does
not have the required features.
Add a new INTEL_SOC option to control this access. This must be selected
by SoCs that can support the required features.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 23 Feb 2021 10:35:41 +0000 (05:35 -0500)]
x86: Move INTEL_ACPIGEN to arch/x86
This option is better placed in the x86 code since it is not generic
enough to be in the core code. Move it.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
x86: sizeof-array-div error in lpc_common_early_init
Building qemu-x86_64_defconfig with GCC 11.0 fails with:
arch/x86/cpu/intel_common/lpc.c:
In function ‘lpc_common_early_init’:
arch/x86/cpu/intel_common/lpc.c:56:40:
error: expression does not compute the number of elements in this array;
element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’}
[-Werror=sizeof-array-div]
56 | sizeof(values) / sizeof(u32));
| ^
arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the
second ‘sizeof’ to silence this warning
arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here
50 | } values[4], *ptr;
| ^~~~~~
Add parentheses to silence warning.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Neil Armstrong [Wed, 10 Feb 2021 14:22:13 +0000 (15:22 +0100)]
configs: meson64: add fdtoverlay_addr_r
In order to support loading FTD Overlays when booting with the pxe
command (or extlinux.conf), supported with [1], add the missing
fdtoverlay_addr_r used to load the overlay before applying it to
the FDT loaded at fdt_addr_r.
Neil Armstrong [Tue, 23 Feb 2021 15:07:51 +0000 (16:07 +0100)]
button: adc: fix treshold typo
Fix the treshold typo in code by threshold.
Fixes: c0165c85c3 ("button: add a simple Analog to Digital Converter device based button driver") Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Makefile: socfpga: Add target to generate hex output for combined spl and dtb
Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel
SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It
combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.
configs: socfpga: soc64: Move CONFIG_BOOTCOMMAND to defconfig
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Up to now the EFI capsule Python tests were always skipped. The reason is
that mkimage fails with:
uboot_bin_env.its:13.21-23.5: Warning (unit_address_vs_reg):
/images/u-boot-bin@100000: node has a unit name, but no reg property
uboot_bin_env.its:24.21-34.5: Warning (unit_address_vs_reg):
/images/u-boot-env@150000: node has a unit name, but no reg property
If a unit in a device-tree has an address, a reg property must be provided.
But adding a reg property is not the solution here.
Since 2017 unit addresses are disallowed for FIT,
cf. common/image-fit.c:1624.
So remove the unit addresses in uboot_bin_env.its.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
- Convert qemu-ppce500 to driver model and enable additional driver
support
- bug fixes/updates in net-dsa driver, vid driver, move configs to kconfig
- Update Maintainers of some powerpc, layerscape platforms
Bin Meng [Thu, 25 Feb 2021 09:22:55 +0000 (17:22 +0800)]
ppc: qemu: Delete the temporary FDT virtual-physical mapping after U-Boot is relocated
After U-Boot is relocated to RAM already, the previous temporary FDT
virtual-physical mapping that was used in the pre-relocation phase
is no longer needed. Let's delete the mapping.
get_fdt_virt() might be used before and after relocation, update it
to return different virtual address of FDT.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:54 +0000 (17:22 +0800)]
ppc: qemu: Enable RTC support via I2C
The QEMU ppce500 target integrates a Freescale I2C controller and
has a Pericom pt7c4338 RTC connected to it. Enable corresponding
DM drivers so that 'date' command is actually useful.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:53 +0000 (17:22 +0800)]
ppc: qemu: Enable support for power off via GPIO
The QEMU ppce500 target provides the power off functionality via
the GPIO pin#0, and we can support this using the sysreset gpio
poweroff driver. Let's enable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:52 +0000 (17:22 +0800)]
dm: sysreset: Add a Kconfig option for the 'reset' command
sysreset uclass driver provides an implementation of 'reset'
command using the sysreset_ APIs unconditionally. It also
supports the 'poweroff' command using the sysreset_ APIs,
but under a Kconfig option CONFIG_SYSRESET_CMD_POWEROFF.
Let's do the same for the 'reset' command, by introducing a
new Kconfig option CONFIG_SYSRESET_CMD_RESET, and set it to
on by default, to allow a board that don't have a sysreset
reset driver yet, but have a sysreset poweroff driver to
compile without any issue.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:51 +0000 (17:22 +0800)]
ppc: qemu: Enable GPIO support
QEMU ppce500 target integrates a GPIO controller that is compatible
with the QorIQ GPIO controller. Enable the DM GPIO driver for it
and the 'gpio' command.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:50 +0000 (17:22 +0800)]
gpio: mpc8xxx: Support controller register physical address beyond 32-bit
dev_read_addr_size_index() returns fdt_addr_t which might be a
64-bit physical address. This might be true for some 85xx SoCs
whose CCSBAR is mapped beyond 4 GiB.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:46 +0000 (17:22 +0800)]
ppc: qemu: Enable VirtIO NET support
By default the QEMU ppce500 machine connects a VirtIO NET to the
PCI controller, although it can be replaced to an e1000 NIC via
additional command line options.
Now that we have switched over to DM PCI, VirtIO support becomes
possible. This commit enables the support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:43 +0000 (17:22 +0800)]
ppc: qemu: Switch over to use DM ETH and PCI
At present the board supports non-DM version PCI and E1000 drivers.
Switch over to use DM ETH and PCI by:
- Rewrite the PCI address map functions using DM APIs
- Enable CONFIG_MISC_INIT_R to do the PCI initialization and
address map
- Drop unnecessary ad-hoc config macros
- Remove board_eth_init() in the board codes
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:42 +0000 (17:22 +0800)]
pci: mpc85xx: Support 64-bit bus and cpu address
At present the driver only supports 32-bit bus and cpu address.
The controller's outbound registers/fields for extended address
are not programmed. Let's program them to support 64-bit bus and
cpu address.
Bin Meng [Thu, 25 Feb 2021 09:22:41 +0000 (17:22 +0800)]
pci: mpc85xx: Support controller register physical address beyond 32-bit
devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit
physical address. Use map_physmem() to return the virtual address
that can be used by a 32-bit machine.
Bin Meng [Thu, 25 Feb 2021 09:22:40 +0000 (17:22 +0800)]
pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAW
For the QEMU ppce500 machine, LAW registers are not implemented
hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not
available. We should wrap all LAW registers programming in the
mpc85xx PCI driver with CONFIG_FSL_LAW.
Bin Meng [Thu, 25 Feb 2021 09:22:38 +0000 (17:22 +0800)]
common: Move initr_addr_map() to a bit earlier
At present initr_addr_map() is put at a late stage in the
init_sequence_r[] calls. This won't work because lot of
device driver initialization (e.g.: serial port) happens
before it but is lack of the address translation support.
This moves the call to a bit earlier, right after the DM
initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:37 +0000 (17:22 +0800)]
ppc: io.h: Use addrmap_ translation APIs only in post-relocation phase
In phys_to_virt() and virt_to_phys(), if CONFIG_ADDR_MAP is defined,
they use addrmap_ translation APIs to do the address translation.
However these APIs only work in post-relocation phase.
Update the code logic to fall back to use the default one when in
pre-relocation phase.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:33 +0000 (17:22 +0800)]
lib: addr_map: Move address_map[] type to the header file
At present address_map[] is static and its type is unknown to external
modules. In preparation to create a command to list its contents, this
patch moves its type definition and declaration to the header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:30 +0000 (17:22 +0800)]
ppc: qemu: Enable OF_CONTROL
The QEMU ppce500 machine generates a device tree blob and passes
it to U-Boot during boot. Let's enable OF_CONTROL with OF_BOARD
and provide board_fdt_blob_setup() in the board codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Bin Meng [Thu, 25 Feb 2021 09:22:26 +0000 (17:22 +0800)]
ppc: qemu: Fix CONFIG_SYS_PCI_MAP_END
CONFIG_SYS_PCI_MAP_END currently points to 0xe8000000, which means
the upper end of the virtual address mapped to PCI bus address ends
at 0xe8000000. But this is wrong as the CCSBAR was already mapped
at 0xe0000000 with a 1 MiB size.
Bin Meng [Thu, 25 Feb 2021 09:22:25 +0000 (17:22 +0800)]
ppc: qemu: Support non-identity PCI bus address
When QEMU originally supported the ppce500 machine back in Jan 2014,
it was created with a 1:1 mapping of PCI bus address. Things seemed
to change rapidly that in Nov 2014 with the following QEMU commits:
commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper end of address space")
and
commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs")
the PCI memory and IO physical address were moved to beyond 4 GiB,
but PCI bus address remained below 4 GiB, hence a non-identity
mapping was created. Unfortunately corresponding U-Boot updates
were missed along with the QEMU changes and the U-Boot QEMU ppce500
PCI support has been broken since then.
This commit makes the PCI (non-DM version) work again.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
projects / u-boot.git / log