For example on a raspberry pi the u-boot environment can be
saved in a file on the first VFAT partition.
This example illustrates how to use it with fw_printenv/fw_setenv.
KM/IVM: split the IVM reading and parsing in 2 parts
This allows to first read the IVM content (earlier in the boot sequence)
and define the ethaddr env variable thanks to the ivm_read_eepromi().
Later, the IVM content can be parsed and used to define some hush
variables, when the hush subsystem is available thanks to
ivm_analyze_eeprom().
To avoid the HW read to happen twice, the buffer passed to
ivm_read_eeprom() has to be reused by ivm_analyze_eeprom (and thus
allocated before calling ivm_read_eeprom()).
Heiko Schocher [Fri, 6 Feb 2015 08:31:36 +0000 (09:31 +0100)]
spl, spl_nor: fix compiler warning
executing "tools/buildman/buildman mpc5xx" drops this warning:
common/spl/spl_nor.c: In function 'spl_nor_load_image':
common/spl/spl_nor.c:26:10: warning: assignment discards 'const' qualifier from pointer target type [enabled by default]
David Feng [Mon, 2 Feb 2015 08:53:13 +0000 (16:53 +0800)]
PCI: add 64-bit prefetchable memory support
PCI specification allow prefetchable memory to be 32-bit or 64-bit.
PCI express specification states that all memmory bars for prefetchable
memory must be implemented as 64-bit. They all require that 64 bit
prefetchble memory are suported especially when u-boot is ported to
more and more 64bit processors.
Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
sunxi: Support the FEL boot mode in the regular u-boot build
So that the CONFIG_SPL_FEL option is not needed anymore. And the regular
SPL binary, generated by the default u-boot build, is now also bootable
over USB in the FEL mode. The SPL still can boot from the SD card too.
A bunch of system registers need to be saved/restored in order to ensure
that the IRQ handler still works in the BROM FEL code after getting
control back from the SPL. This is done in the sunxi code instead of
abusing ifdefs in 'start.S'.
The decision whether to load the main u-boot binary from the SD card or
return to the FEL code in the BROM is done at runtime.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[hdegoede@redhat.com: Since we now restore various regs before returning to
the FEL BROM code we can drop the sunxi specific #ifdefs in start.S] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Simon Glass [Sat, 7 Feb 2015 17:47:30 +0000 (10:47 -0700)]
sunxi: Normalise FEL support
Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of
creating its own. There are some #ifdefs required in start.S. Future work
will hopefully remove these.
This series is available at u-boot-dm, branch sunxi-working.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Simon Glass [Sat, 7 Feb 2015 17:47:29 +0000 (10:47 -0700)]
arm: spl: Provide for a board-specific loader
Some boards have a special way of loading U-Boot that does not fit with
the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot
is loaded over USB. Add a CONFIG option and boot mode for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Simon Glass [Sat, 7 Feb 2015 17:47:28 +0000 (10:47 -0700)]
arm: Allow lr to be saved by board code
The link register value can be required on some boards (e.g. FEL mode on
sunxi) so use a branch instruction to jump to save_boot_params() instead
of a branch link.
This requires a branch back to save_boot_params_ret so adjust the users
to deal with this. For exynos just drop the function since it doesn't
do anything.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
tools: mksunxiboot: Fix problems on big endian systems
Now my PS3 can be also used to build u-boot for sunxi devices.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Wed, 4 Feb 2015 11:14:56 +0000 (12:14 +0100)]
sunxi: dram: Un-inline dram helper functions
Move the dram helper functions to a separate C file, rather then having them
as inline helpers in dram.h. This saves 144 bytes in the .text segment for
sun6i builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Only use CONFIG_SUNXI_MAX_FB_SIZE to reserve memory at the top when relocating
u-boot, and calculate the actual amount of memory necessary when setting up
the video-mode and use only that, freeing up some additional memory for use
by the kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 2 Feb 2015 16:13:29 +0000 (17:13 +0100)]
sunxi: video: Do not use CONFIG_SYS_MEM_TOP_HIDE for the framebuffer
Do not use CONFIG_SYS_MEM_TOP_HIDE for the framebuffer, instead override
board_get_usable_ram_top to make sure that u-boot is not relocated into the
area where we want to use the framebuffer, and patch the devicetree from
sunxi_simplefb_setup() to tell the kernel to not touch the framebuffer.
This makes u-boot properly see the framebuffer as dram, and initalize the
level 2 cache for it, fixing the very slow cfb scrolling problem.
As an added bonus this stops us from reserving the framebuffer when simplefb
is not used because an older kernel is booted, or hdp is used and no hdmi
cable was plugged in, freeing up the memory for kernel use in these cases.
Reported-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Commit a93648d197df48fa46dd55f925ff70468bd81c71 introduced linker generated
lists for imagetool which is the base for some host tools (mkimage, dumpimage,
et al.). Unfortunately some host tool chains do not support the used type of
linker scripts. Therefore this commit broke these host-tools for them, namely
FreeBSD and Darwin (OS/X).
This commit tries to fix this. In order to have a clean distinction between host
and embedded code space we need to introduce our own linker generated list
instead of re-using the available linker_lists.h provided functionality. So we
copy the implementation used in linux kernel script/mod/file2alias.c which has
the very same problem (cause it is a host tool). This code also comes with an
abstraction for Mach-O binary format used in Darwin systems.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Guilherme Maciel Ferreira <guilherme.maciel.ferreira@gmail.com>
Vitaly Andrianov [Wed, 11 Feb 2015 19:05:41 +0000 (14:05 -0500)]
net: keystone_net: move serdes setup to initialization function
On Keystone2 devices serdes must be initialized before accessing MDIO bus.
This commit moves the keystone2_net_serdes_setup() from keystone2_eth_open
to keystone2_emac_initialize to meet that requirement.
This also eliminates unnecessary serdes initializatin every time when the
keystone2_eth_open is being called.
Vitaly Andrianov [Wed, 11 Feb 2015 19:07:58 +0000 (14:07 -0500)]
keystone2: ddr3: eliminate using global ddr3_size variable
KS2 ddr3 initialization uses ddr3_size global variable before u-boot
relocation. Even if the variable is not being used after relocation,
writing to it corrupts relocation table.
This patch removes the global ddr3_size variable and uses local one
instead.
Steve Kipisz [Wed, 11 Feb 2015 23:54:28 +0000 (18:54 -0500)]
clock_am43xx:Set the MAC clock to /5 for OPP100
When EMAC is in the boot order, the boot ROM sets OPP50 and the
MAC clock is set to /2. SPL needs to change it to /5 for Ethernet
to generate the correct txclk. This patch sets it correctly.
Lokesh Vutla [Mon, 16 Feb 2015 04:45:56 +0000 (10:15 +0530)]
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.
Angela Stegmaier [Mon, 16 Feb 2015 04:45:55 +0000 (10:15 +0530)]
ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.
Egli, Samuel [Fri, 13 Feb 2015 14:47:10 +0000 (15:47 +0100)]
mtd, omap: fix case NAND_OMAP_GPMC_PREFETCH not defined
The patch c316f577b4b72d1a1aeb559e9b3fad20808f1ffd breaks
siemens boards because prefetch mode is not enabled.
I assume it breaks other boards as well that don't use
prefetch.
This patch sets read_buf to nand_read_buf if
NAND_OMAP_GPMC_PREFETCH is not defined.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com> CC: Daniel Mack <zonque@gmail.com> CC: Guido Martínez <guido@vanguardiasur.com.ar> CC: Tom Rini <trini@ti.com> CC: Heiko Schocher <hs@denx.de>
Michael Walle [Fri, 13 Feb 2015 17:45:57 +0000 (18:45 +0100)]
lsxl: add a README file
The README describes the recovery method which can be used if the NAS box
is not reachable anymore. Addionally, it describes the different boot
scripts.
Simon Glass [Wed, 11 Feb 2015 01:52:35 +0000 (18:52 -0700)]
sandbox: Adjust the order of the NO_SDL check
An option is provided to avoid using SDL in U-Boot sandbox (and drop
support for the LCD). However the check in the Makefile is too late
and warnings are printed even if NO_SDL=y is given.
Adjust the order to avoid this warning.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Joe Hershberger [Fri, 6 Feb 2015 21:37:31 +0000 (15:37 -0600)]
sandbox: Return '-c command' exit value as sandbox exit code
When a command is passed into sandbox using the '-c' argument the
command is run directly. This is most helpful when running tests (such
as test-dm.sh). Previously the exit code was an unused enum. Change it
to be the actual return code from the command so that the script calling
sandbox can know if the command succeeded (tests passed). Also remove
the now completely unused "exit_state" in sandbox.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
Albert ARIBAUD [Sat, 31 Jan 2015 23:12:44 +0000 (00:12 +0100)]
buildman: allow multiple toolchains in a single path
When buildman scans a toolchain path, it stops at the
first toolchain found. However, a single path can contains
several toolchains, each with its own prefix.
This patch lets buildman scan all toolchains in the path.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org>
Akshay Saraswat [Wed, 4 Feb 2015 10:30:05 +0000 (16:00 +0530)]
Exynos: Clock: Cleanup soc_get_periph_rate
Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specific exceptions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Wed, 4 Feb 2015 10:30:04 +0000 (16:00 +0530)]
Exynos: clock: change mask bits as per peripheral
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Wed, 4 Feb 2015 10:30:03 +0000 (16:00 +0530)]
Exynos5: Use clock_get_periph_rate generic API
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Wed, 4 Feb 2015 10:30:02 +0000 (16:00 +0530)]
Exynos5: Fix exynos5_get_periph_rate calculations
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Wed, 4 Feb 2015 10:30:01 +0000 (16:00 +0530)]
Exynos542x: Add and enable get_periph_rate support
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Wed, 4 Feb 2015 10:30:00 +0000 (16:00 +0530)]
Exynos542x: Move exynos5420_get_pll_clk up and rename
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Wed, 4 Feb 2015 10:29:59 +0000 (15:59 +0530)]
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Alexey Brodkin [Tue, 13 Jan 2015 15:35:46 +0000 (18:35 +0300)]
arc: introduce U-Boot port for ARCv2 ISA
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).
Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.
In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.
In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.
This change adds support for following cores:
* ARC EM6 (simple 32-bit microcontroller without MMU)
* ARC HS36 (advanced 32-bit microcontroller without MMU)
* ARC HS38 (advanced 32-bit microcontroller with MMU)
As a part of ARC HS38 new version of MMU (v4) was introduced.
Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.
Michal Simek [Mon, 2 Feb 2015 15:31:59 +0000 (16:31 +0100)]
dm: Add support for all targets which requires MANUAL_RELOC
Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA
relocation (mostly only GOT) where functions aray are not
updated. This patch is fixing function pointers for DM core
and serial-uclass to ensure that relocated functions are called.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
Peng Fan [Tue, 10 Feb 2015 06:46:34 +0000 (14:46 +0800)]
dm:gpio:mxc add DT support
This patch add DT support for mxc gpio driver.
There are one place using CONFIG_OF_CONTROL macro.
1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT,
platdata is alloced using calloc, so there is no need to use mxc_plat.
The following situations are tested, and all work fine:
1. with DM, without DT
2. with DM and DT
3. without DM
Since device tree has not been upstreamed, if want to test this patch.
The followings need to be done.
+ pieces of code does not gpio_request when using gpio_direction_xxx and
etc, need to request gpio.
+ move the gpio settings from board_early_init_f to board_init
+ define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
+ Add device tree file and do related configuration in
`make ARCH=arm menuconfig`
These will be done in future patches by step.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Simon Glass <sjg@chromium.org>
Peng Fan [Tue, 10 Feb 2015 06:46:33 +0000 (14:46 +0800)]
dm:gpio:mxc add a bank_index entry in platdata
Add a new entry in platdata structure and intialize
bank_index in mxc_plat array.
This new entry can avoid using `plat - mxc_plat` by using
`plat->bank_index`.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 6 Feb 2015 04:41:33 +0000 (21:41 -0700)]
dm: i2c: Make API accessible even without CONFIG_DM
Make the driver model I2C API available always, even if driver model
is not enabled. This allows for a 'soft' switch-over, where drivers can
use the new structures in code which is compiled but not yet used. This
makes migration easier in some cases.
Fix up the existing drivers which define their own 'struct i2c_msg'.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Sat, 7 Feb 2015 18:51:52 +0000 (11:51 -0700)]
powerpc: ppc4xx: Enable CONFIG_DISPLAY_BOARDINFO
This also displays the "Board:" line in the bootup text with the
generic board support code.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Sat, 7 Feb 2015 18:51:51 +0000 (11:51 -0700)]
powerpc: ppc4xx: Add defaults for DT based booting to really work
These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Sat, 7 Feb 2015 18:51:50 +0000 (11:51 -0700)]
powerpc: ppc4xx: Change from OF_SEPARATE to OF_EMBED
This is necessary, as ppc4xx has the reset vector located at the end
of the U-Boot image. This needs to be flashed to the end of the NOR
flash. Adding the dtb to the main U-Boot image will break booting
on ppc4xx. This patch now embeds the dtb in the U-Boot image instead.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
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