Kumar Gala [Tue, 10 Jun 2008 21:16:02 +0000 (16:16 -0500)]
FSL LAW: Add new interface to use the last free LAW
LAWs have the concept of priority so its useful to be able to allocate
the lowest (highest number) priority. We will end up using this with the
new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 11 Jun 2008 05:51:45 +0000 (00:51 -0500)]
85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the
system allocate which LAWs are used for what purpose. This makes life
a bit easier going forward with the new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
TQM85xx: Change memory map to support Flash memory > 128 MiB
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash
memory. The current memory map only supports up to 128 MiB Flash.
This patch adds the configuration option CONFIG_TQM_BIGFLASH. If
set, up to 1 GiB flash is supported. To achieve this, the memory
map has to be adjusted in great parts (for example the CCSRBAR is
moved from 0xE0000000 to 0xA0000000).
If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new
memory map also has to be considered in the kernel (changed
CCSRBAR address, changed PCI IO base address, ...). Please use
an appropriate Flat Device Tree blob (tqm8548.dtb).
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for NAND FLASH on the TQM8548. It is disabled by
default and can be enabled for the TQM8548 modules. It is now based on
the re-written FSL NAND UPM driver. A patch has been posted earlier today
with the subject:
"NAND FSL UPM: driver re-write using the hwcontrol callback"
Note that the R/B pin is not supported by that module requiring to use
the specified maximum delay time.
Note: With NAND support enabled the size of the U-Boot image exceeds
256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk,
doubling the image size :-(.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds basic support for the TQM8548 module from TQ-Components
(http://www.tqc.de/) including DDR2 SDRAM initialisation and support for
eTSEC 3 and 4
Furthermore Flash buffer write has been enabled to speed up output to
the Flash by approx. a factor of 10.
Signed-off-by: Thomas Waehner <thomas.waehner@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This patch adds support for Linux kernels using the Flat Device Tree.
It also re-defines the default environment settings for booting Linux
with the FDT blob.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
TQM85xx: Support for Spansion 'N' type flashes added
The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors,
than the formerly used 'M' types (S29GLxxxM series), so the flash layout
needs to be changed -> new start address of the environment. The macro
definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be
defined for boards with 'N' type flashes.
Signed-off-by: Martin Krause <martin.krause@tqs.de> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560
board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used
as serial interface anyway. Worse, on some board variants configuring the
pins for SCC1 leads to short circuits (for example on the TQM8541-BG).
Signed-off-by: Martin Krause <martin.krause@tqs.de>
NAND FSL UPM: driver re-write using the hwcontrol callback
This is a re-write of the NAND FSL UPM driver using the more universal
hwcontrol callback (instead of the cmdfunc callback). Here is a brief
list of furher modifications:
- For the time being, the UPM setup writing the UPM array has been
removed from the driver and must now be done by the board specific
code.
- The bus width definition in "struct fsl_upm_nand" is now in bits to
comply with the corresponding Linux driver and 8, 16 and 32 bit
accesses are supported.
- chip->dev_read is only set if fun->dev_ready != NULL, which is
required for boards not connecting the R/B pin.
- A few issue have been fixed with MxMR bit manipulation like in the
corresponding Linux driver.
Note: I think the "io_addr" field of "struct fsl_upm" could be removed
as well, because the address is already determined by
"nand->IO_ADDR_[RW]", but I'm not 100% sure.
This patch has been tested on a TQM8548 modules with the NAND chip
Micron MT29F8G08FABWP.
This patch is based on the following patches posted to this list a few
minutes ago:
PPC: add accessor macros to clear and set bits in one shot
83xx/85xx/86xx: add more MxMR local bus definitions
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com>
PPC: add accessor macros to clear and set bits in one shot
PPC: add accessor macros to clear and set bits in one shot
This patch adds macros from linux/include/asm-powerpc/io.h to clear and
set bits in one shot using the in_be32, out_be32, etc. accessor functions.
They are very handy to manipulate bits it I/O registers.
This patch is required for my forthcoming FSL NAND UPM driver re-write and
the support for the TQM8548 module.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
83xx/85xx/86xx: add more MxMR local bus definitions
83xx/85xx/86xx: add more MxMR local bus definitions
This patch adds more macro definitions for the UPM Machine Mode Registers
They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx
common local bus definitions into include/asm-ppc/fsl_lbc.h. They are
required for my forthcoming FSL NAND UPM driver re-write and the support
for the TQM8548 module.
This patch is based on the following two patches from Anton Vorontsov:
Kumar Gala [Tue, 10 Jun 2008 21:53:46 +0000 (16:53 -0500)]
85xx: expose cpu identification
The current cpu identification code is used just to return the name
of the processor at boot. There are some other locations that the name
is useful (device tree setup). Expose the functionality to other bits
of code.
Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out. This is mainly to allow the most flexible use
of the name. The device tree code tends to not care about the 'E' suffix.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Anton Vorontsov [Wed, 28 May 2008 14:20:15 +0000 (18:20 +0400)]
83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h
This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
use it on MPC85xx and MPC86xx processors.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Becky Bruce [Wed, 14 May 2008 18:10:04 +0000 (13:10 -0500)]
MPC85xx: Change traps.c to not reference non-addressable memory
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Stuart Wood [Fri, 30 May 2008 20:05:28 +0000 (16:05 -0400)]
env_nand.c: Added bad block management for environment variables
Modified to check for bad blocks and to skipping over them when
CFG_ENV_RANGE has been defined.
CFG_ENV_RANGE must be larger than CFG_ENV_SIZE and aligned to the NAND
flash block size.
Signed-off-by: Stuart Wood <stuart.wood@labxtechnologies.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Becky Bruce [Wed, 14 May 2008 18:09:58 +0000 (13:09 -0500)]
MPC86xx: Change traps.c to not reference non-addressable memory
Currently, END_OF_RAM is used by the trap code to determine if
we should attempt to access the stack pointer or not. However,
on systems with a lot of RAM, only a subset of the RAM is
guaranteed to be mapped in and accessible. Change END_OF_RAM
to use get_effective_memsize() instead of using the raw ram
size out of the bd to prevent us from trying to access
non-mapped memory.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
We use upper case letters for the AMCC processor defines (like
CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and
not CONFIG_440SPe. This patch fixes the last misspelled config options.
Remy Bohmer [Thu, 5 Jun 2008 11:03:36 +0000 (13:03 +0200)]
DM9000 fix status check fail 0x6d error for trizeps board
According to the Application Notes of the DM9000, only the 2 bits 0:1 of
the status byte need to be checked to identify a valid packet in the fifo
But, The several different Application Notes do not all speak the same
language on these bits. They do not disagree, but only 1 Application Note
noted explicitly that only these 2 bits need to be checked.
Even the datasheets do not mention anything about these 2 bits.
Because the old code, and the kernel check the whole byte, I left this piece
untouched.
However, I tested all board/DM9000[A|E|EP] devices with this 2 bit check, so
it should work.
Notice, that the 2nd iteration through this receive loop (when a 2nd packet is
in the fifo) is much shorter now, compared to the older U-boot driver code,
so that we can maybe run into a hardware condition now that was never seen
before, or maybe was seen very unfrequently.
Additionaly added a cleanup of a stack variable.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Remy Bohmer [Tue, 3 Jun 2008 13:48:17 +0000 (15:48 +0200)]
Get rid of annoying/superfluous bad-checksum warning message
U-boot can complain a lot about 'checksum bad' when it is attached to the network.
It is annoying for ordinary users who start to doubt the network connection
in general when they see messages like this.
This is caused by the routine NetCksumOk() which cannot handle IP-headers longer
than 20 bytes. Those packages can be ignored anyway by U-boot, so we trash them
now before checking the checksum.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Remy Bohmer [Wed, 4 Jun 2008 08:47:25 +0000 (10:47 +0200)]
Fix order for reading rx-status registers in 32bit mode of DM9000
A last minute cleanup before submitting the DM9000A patch series yesterday introduced
a bug in reading the rx-status registers in 32bit mode only.
This patch repairs this.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Remy Bohmer [Tue, 3 Jun 2008 13:26:25 +0000 (15:26 +0200)]
DM9000: Make driver work properly for DM9000A
The DM9000A network controller does not work with the U-boot DM9000x driver.
Analysis showed that many incoming packets are lost.
The DM9000A Application Notes V1.20 (section 5.6.1) recommend that the poll to
check for a valid rx packet be done on the interrupt status register, not
directly by performing the dummy read and the rx status check as is currently
the case in the u-boot driver.
When the recommended poll is done as suggested the driver starts working
correctly on 10Mbit/HD, but on 100MBit/FD packets come in faster so that there
can be more than 1 package in the fifo at the same time.
The driver must perform the rx-status check in a loop and read and handle all
packages until there is no more left _after_ the interrupt RX flag is set.
This change has been tested with DM9000A, DM9000E, DM9000EP.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Remy Bohmer [Tue, 3 Jun 2008 13:26:24 +0000 (15:26 +0200)]
DM9000: Improve eth_reset() routine
According to the application notes of the DM9000 v1.22 chapter 5.2 bullet 2, the
reset procedure must be done twice to properly reset the DM9000 by means of software.
This errata is not needed anymore for the DM9000A, but it does not bother it.
This change has been tested with DM9000A, DM9000E, DM9000EP.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Remy Bohmer [Tue, 3 Jun 2008 13:26:21 +0000 (15:26 +0200)]
DM9000: Add data bus-width auto detection.
The U-boot DM9000x driver contains a compile time bus-width definition for
the databus connected to the network controller.
This compile check makes the code unclear, inflexible and is unneccessary.
It can be asked to the network controller what its bus-width is by reading bits
6 and 7 of the interrupt status register.
The linux kernel already uses a runtime mechanism to determine this bus-width,
so the implementation below looks somewhat like that implementation.
This change has been tested with DM9000A, DM9000E, DM9000EP.
Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Peter Tyser [Thu, 22 May 2008 23:56:52 +0000 (18:56 -0500)]
Additional fix to readline_into_buffer() with CONFIG_CMDLINE_EDITING before relocating
Removed unneeded command line history initialization. Also, the original
code would access the 'initted' variable before relocation to SDRAM
which resulted in erratic behavior since the bss is not initialized when
executing from flash.
Some NOR flash chips needs support of commands with length grether than max
value size of uchar. For example all M18 family chips use 0x1ff command in
buffered write mode as value of program loops count.
Stefan Roese [Fri, 16 May 2008 09:06:06 +0000 (11:06 +0200)]
DTT: Issue one-shot command on AD7414 (LM75 code) to read temp
On AD7414 the first value upon bootup is not read correctly.
This is most likely because of the 800ms update time of the
temp register in normal update mode. To get current values
each time we issue the "dtt" command including upon powerup
we switch into one-short mode.
This patch fixes the problem on AD7414 equipped boards (Sequoia,
Canyonlands etc), that temp value printed in the bootup log was
incorrect.
Matthias Fuchs [Fri, 30 May 2008 14:55:06 +0000 (16:55 +0200)]
ppc4xx: Cleanup CPCI405 variant's config file
This patch removes some dead code from CPCI405 board's
config files. JFFS2 support is also removed. It's not used and
CPCI4052 does not build anymore without some size reduction.
This is pretty incomplete...it doesn't handle reading the environment
before relocation, it doesn't support redundant environment, and it
doesn't support embedded environment. But apart from that, it does
seem to work.
This adds a driver for the SPI controller found on most AT91 and AVR32
chips, implementing the new SPI API.
Changed in v4:
- Update to new API
- Handle zero-length transfers appropriately. The user may send a
zero-length SPI transfer with SPI_XFER_END set in order to
deactivate the chip select after a series of transfers with chip
select active. This is useful e.g. when polling the status
register of DataFlash.
This patch gets rid of the spi_chipsel table and adds a handful of new
functions that makes the SPI layer cleaner and more flexible.
Instead of the spi_chipsel table, each board that wants to use SPI
gets to implement three hooks:
* spi_cs_activate(): Activates the chipselect for a given slave
* spi_cs_deactivate(): Deactivates the chipselect for a given slave
* spi_cs_is_valid(): Determines if the given bus/chipselect
combination can be activated.
Not all drivers may need those extra functions however. If that's the
case, the board code may just leave them out (assuming they know what
the driver needs) or rely on the linker to strip them out (assuming
--gc-sections is being used.)
To set up communication parameters for a given slave, the driver needs
to call spi_setup_slave(). This returns a pointer to an opaque
spi_slave struct which must be passed as a parameter to subsequent SPI
calls. This struct can be freed by calling spi_free_slave(), but most
driver probably don't want to do this.
Before starting one or more SPI transfers, the driver must call
spi_claim_bus() to gain exclusive access to the SPI bus and initialize
the hardware. When all transfers are done, the driver must call
spi_release_bus() to make the bus available to others, and possibly
shut down the SPI controller hardware.
spi_xfer() behaves mostly the same as before, but it now takes a
spi_slave parameter instead of a spi_chipsel function pointer. It also
got a new parameter, flags, which is used to specify chip select
behaviour. This may be extended with other flags in the future.
This patch has been build-tested on all powerpc and arm boards
involved. I have not tested NIOS since I don't have a toolchain for it
installed, so I expect some breakage there even though I've tried
fixing up everything I could find by visual inspection.
I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and
DataFlash drivers posted as a follow-up. I'd like some help testing
other boards that use the existing SPI API.
But most of all, I'd like some comments on the new API. Is this stuff
usable for everyone? If not, why?
Changed in v4:
- Build fixes for various boards, drivers and commands
- Provide common struct spi_slave definition that can be extended by
drivers
- Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate
- Make default bus and mode build-time configurable
- Override default SPI bus ID and mode on mx32ads and imx31_litekit.
Changed in v3:
- Add opaque struct spi_slave for controller-specific data associated
with a slave.
- Add spi_claim_bus() and spi_release_bus()
- Add spi_free_slave()
- spi_setup() is now called spi_setup_slave() and returns a
struct spi_slave
- soft_spi now supports four SPI modes (CPOL|CPHA)
- Add bus parameter to spi_setup_slave()
- Convert the new i.MX32 SPI driver
- Convert the new MC13783 RTC driver
Changed in v2:
- Convert the mpc8xxx_spi driver and the mpc8349emds board to the
new API.
AVR32 and AT91SAM9 both have their own identical definitions of
container_of() taken from the Linux kernel. Move it to common.h so
that all architectures can use it.
container_of() is already used by some drivers, and will be used
extensively by the new and improved SPI API.
Systems that support open-drain GPIO properly are allowed provide an
empty I2C_TRISTATE define. However, this means that we need to be
careful not to drive SDA low when the slave is expected to respond.
This patch adds a missing I2C_SDA(1) to read_byte() required to
tristate the SDA line on systems that support open-drain GPIO.
Stefan Roese [Mon, 2 Jun 2008 15:37:28 +0000 (17:37 +0200)]
ppc4xx: Remove superfluous dram_init() call or replace it by initdram()
Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.
This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:
csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG
I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.
Stefan Roese [Mon, 2 Jun 2008 15:20:03 +0000 (17:20 +0200)]
ppc4xx: Fix common ECC generation code for 440GP style platforms
This patch makes the common 4xx ECC code really usable on 440GP style
platforms.
Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
we need to make some processor dependant defines used later on by the
driver.
Stefan Roese [Mon, 2 Jun 2008 15:13:55 +0000 (17:13 +0200)]
ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.
Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.
This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).
It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:
used on 405GR/CR/EP and some Xilinx Virtex boards.
Stefan Roese [Mon, 2 Jun 2008 12:35:44 +0000 (14:35 +0200)]
ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S
This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.
Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
Grant Erickson [Thu, 22 May 2008 21:44:24 +0000 (14:44 -0700)]
ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling
This patch (Part 2 of 2):
* Rolls up a suite of changes to enable correct primordial stack and
global data handling when the data cache is used for such a purpose
for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
* Related to the first, unifies DDR2 SDRAM and ECC initialization by
eliminating redundant ECC initialization implementations and moving
redundant SDRAM initialization out of board code into shared 4xx
code.
* Enables MCSR visibility on the 405EX(r).
* Enables the use of the data cache for initial RAM on
both AMCC's Kilauea and Makalu and removes a redundant
CFG_POST_MEMORY flag from each board's CONFIG_POST value.
- Removed, per Stefan Roese's request, defunct memory.c file for
Makalu and rolled sdram_init from it into makalu.c.
With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.
Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Grant Erickson [Thu, 22 May 2008 21:44:14 +0000 (14:44 -0700)]
ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling
This patch (Part 1 of 2):
* Rolls up a suite of changes to enable correct primordial stack and
global data handling when the data cache is used for such a purpose
for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
* Related to the first, unifies DDR2 SDRAM and ECC initialization by
eliminating redundant ECC initialization implementations and moving
redundant SDRAM initialization out of board code into shared 4xx
code.
* Enables MCSR visibility on the 405EX(r).
* Enables the use of the data cache for initial RAM on
both AMCC's Kilauea and Makalu and removes a redundant
CFG_POST_MEMORY flag from each board's CONFIG_POST value.
- Removed, per Stefan Roese's request, defunct memory.c file for
Makalu and rolled sdram_init from it into makalu.c.
With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.
Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Kumar Gala [Thu, 15 May 2008 20:13:08 +0000 (15:13 -0500)]
Fix warnings from gcc-4.3.0 build on a ppc host
* The cfi_flash.c memset fix actual allows the board to boot so there is
a bit more going on here than just resolving warnings associated with
uninitialized variables.
* include/asm/bitops.h:302: warning: '__swab32p' is static but used in
inline function 'ext2_find_next_zero_bit' which is not static
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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