Ioana Ciornei [Mon, 18 May 2020 11:48:36 +0000 (14:48 +0300)]
arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used.
The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS
file specifically made for the current SERDES protocol.
This patch adds the necessary DPMAC nodes (DPMAC 1-8) for
protocol 42 (0x2A) on SD#1.
Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.
Ioana Ciornei [Mon, 18 May 2020 11:48:35 +0000 (14:48 +0300)]
board: ls2080aqds: transition to DM_ETH
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
Ioana Ciornei [Fri, 15 May 2020 06:56:49 +0000 (09:56 +0300)]
board: ls1088aqds: transition to DM_ETH
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
Ioana Ciornei [Fri, 15 May 2020 06:56:48 +0000 (09:56 +0300)]
arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if
there isn't a DTS file specifically made for the current SERDES
protocol.
This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found
on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1.
On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as 2 input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.
Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one
of the 2 IO slots. As a consequence, a new node is added to
describe register 0x54 as a MDIO mux controlled with child nodes
describing all the IO slots as MDIO buses.
Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.
net: fsl-mc: fixup DPC: add /board/ports node if missing
The DPC fixup for MAC address and enet_if is not made if
/board/ports node is missing in DPC file.
Add /board/ports or /ports nodes if them are missing.
CONFIG_MTD_NOR_FLASH flag needs to be enable for all
boot sources,as all flash drivers need to compile in
TFA Boot.Probe ifc nor flash only when there is nor
flash available on board.So needs to detect ifc-nor
flash at run-time for probing.
In case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the
board_fit_config_name_match() function in order to choose the
appropriate DTS for the current SERDES protocol configuration.
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Add device trees describing possible uses of mezzanine cards depending
on the SERDES protocol employed.
This patch adds DPAA2 networking support for the following protocols on
each SERDES block:
* SD #1: 3, 7, 19, 20
* SD #2: 11
Each SERDES block has a different device tree file per protocol
supported, where the IO SLOTs used are enabled and PHYs located on the
mezzanine cards are described. Also, dpmac nodes are edited and their
associated phy-connection-type and phy-handle are added.
Top DTS files are also added for each combination of protocol on the 3
SERDES blocks.
The LX2160A processor has two external MDIO interfaces, described in the
DTS as emdio1 and emdio2.
On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as eight input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.
Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one
of the 8 IO slots. As a consequence, a new node is added to
describe register 0x54 as a MDIO mux controlled with child nodes
describing all the IO slots as MDIO buses.
Also, DPMAC 17 and 18 are updated to reference the on-board PHYs.
Laurentiu Tudor [Mon, 4 May 2020 11:47:11 +0000 (14:47 +0300)]
drivers: net: fsl-mc: fixup msi-map property
Similarly to iommu-map, the msi-map property must also be fixed up
in the device tree, in order for the icid -> streamid translation
be possible in the MSI case as well.
Kuldeep Singh [Mon, 4 May 2020 06:04:55 +0000 (11:34 +0530)]
configs: ls1012a: Unset ENV_ADDR value
LS1012A-FRWY and LS1012A-RDB crashes in flash environment when
CONFIG_ENV_ADDR value is set. Unset the config value in *_tfa_defconfig*
to resolve booting crash.
Kuldeep Singh [Sat, 14 Dec 2019 14:02:56 +0000 (19:32 +0530)]
configs: nxp: Enable CONFIG_SYS_RELOC_GD_ENV_ADDR
Commit 323d3af59fe4 ("configs: ls1012ardb: Enable
CONFIG_SYS_RELOC_GD_ENV_ADDR") enables the config only for LS1012ARDB.
Apart from LS1012A-RDB, other platforms such as LS1012A-FRWY, LS2088A
and LS1046A-RDB/FRWY also require this config to be enabled. This also
helps in resolving booting crash observed in flash environment.
configs: ls1012a: Reduce CONFIG_ENV_SIZE to 0x2000
All LS1012A board variants have same CONFIG_ENV_SECT_SIZE and
CONFIG_ENV_SIZE values. If both config values are same, flash
environment cannot be saved. Since, CONFIG_ENV_SECT_SIZE needs to be
same as that of flash sector size, this entry cannot be changed.
Reduce CONFIG_ENV_SIZE value to 0x2000. This also helps in making config
value aligned with other boards environemt size.
CONFIG_SYS_MALLOC_LEN is currently set to low value and leaves very less
space to do malloc in flash environmet. Increase the value to get more
memory and also make it align with other boards(ls1046a, ls1043a etc.)
config values.
Kuldeep Singh [Fri, 7 Feb 2020 16:45:18 +0000 (22:15 +0530)]
configs: ls2080ardb: Make BOOT command access flash memory as per spi-mem
BOOT command currently access spi-nor flash memory directly. As per spi-mem
framework, flash memory access via absolute addresses is no more possible.
Use flash APIs to access memory instead of directly using it.
Kuldeep Singh [Fri, 7 Feb 2020 16:39:09 +0000 (22:09 +0530)]
configs: ls2080ardb: Make MC_INIT access flash memory as per spi-mem
MC_INIT command currently access spi-nor flash memory directly. As per
spi-mem framework, flash memory access via absolute addresses is no more
possible. Use flash APIs to access memory instead of directly using it.
Kuldeep Singh [Tue, 12 May 2020 09:09:46 +0000 (14:39 +0530)]
configs: ls1046a: Define ENV_ADDR value
CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
The macro value is already defined in ls1046ardb_tfa_defconfig, also
define the value as 0x40300000 in qspi_defconfig.
ls1046aqds has one spansion flash "S25FL128S_64K" of size 16M with
sector size 64K. Correct ENV_ADDR and ENV_SECT_SIZE value for QSPI and
TFA defconfigs of the board.
Kuldeep Singh [Tue, 11 Feb 2020 09:26:42 +0000 (14:56 +0530)]
configs: ls2080a: Correct ENV_ADDR value
CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
QSPI region in LS2088ARDB and LS2088AQDS starts from 0x20000000 offset.
Correct the config value i.e 0x80500000 -> 0x20500000.
Also, define config value as 0x20300000 in qspi defconfig.
Kuldeep Singh [Tue, 11 Feb 2020 09:21:35 +0000 (14:51 +0530)]
configs: ls1088a: Correct ENV_ADDR value
CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
QSPI region starts from 0x20000000 offset.
Correct the config value i.e 0x80500000 -> 0x20500000.
Kuldeep Singh [Thu, 12 Dec 2019 06:19:24 +0000 (11:49 +0530)]
treewide: Update fsl qspi node dt properties as per spi-mem driver
According to new qspi driver, some properties like "bus-num, num-cs,
big-endian" are no longer used. Device endiannes can be determined from
device-type data in driver.
Now use board specific compatibles, generic node names and specific
labels to align with linux device-tree properties.
Also consolidate spi-max-frequency to 50Mhz treewide.
Kuldeep Singh [Tue, 12 May 2020 07:24:07 +0000 (12:54 +0530)]
treewide: Remove unused FSL QSPI config options for Layerscape platforms
Some of these options are not used by the driver anymore and some of
them are obsolete as the information is gathered from the dt. Also
consolidating defines in common headers.
Tom Rini [Mon, 18 May 2020 12:17:29 +0000 (08:17 -0400)]
Merge tag 'efi-2020-07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-07-rc3
A series of patches introduces the possibility to manage UEFI variables
via an OP-TEE module. CONFIG_EFI_MM_COMM_TEE enables this. If this
option is not specified the U-Boot behavior remains unchanged. A defconfig
is provided for compile testing (lx2160ardb_tfa_stmm_defconfig).
An incorrect UEFI memory allocation for fsl-layerscape is fixed
Ilias Apalodimas [Sun, 17 May 2020 19:25:48 +0000 (22:25 +0300)]
configs: lx2160a: Add default config for lx2160a using StMM in OP-TEE
Previous patches allow UEFI secure variables to be stored in an RPMB
device using OPTEE. Add a config for the lx2160a hardware so the feature
gets at least compiled.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Remove superfluous differences to lx2160ardb_tfa_defconfig. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If OP-TEE is compiled with an EDK2 application running in secure world
it can process and store UEFI variables in an RPMB.
Add documentation for the config options enabling this.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Sun, 17 May 2020 19:25:45 +0000 (22:25 +0300)]
cmd: efidebug: Add support for querying UEFI variable storage
With the previous patches that use OP-TEE and StandAloneMM for UEFI
variable storage we've added functionality for efi_query_variable_info.
So let's add the relevant command to efidebug and retrieve information
about the container used to store UEFI variables
Ilias Apalodimas [Sun, 17 May 2020 19:25:44 +0000 (22:25 +0300)]
efi_loader: Implement EFI variable handling via OP-TEE
In OP-TEE we can run EDK2's StandAloneMM on a secure partition.
StandAloneMM is responsible for the UEFI variable support. In
combination with OP-TEE and it's U-Boot supplicant, variables are
authenticated/validated in secure world and stored on an RPMB partition.
So let's add a new config option in U-Boot implementing the necessary
calls to OP-TEE for the variable management.
Sughosh Ganu [Sun, 17 May 2020 19:25:43 +0000 (22:25 +0300)]
efi_loader: Add headers for EDK2 StandAloneMM communication
In Arm devices OP-TEE has the ability to run StandAloneMM (from EDK2)
in a separate partition and handle UEFI variables.
A following patch introduces this functionality.
Add the headers needed for OP-TEE <--> StandAloneMM communication
Michael Walle [Sun, 17 May 2020 10:29:19 +0000 (12:29 +0200)]
efi_loader: round the memory area in efi_add_memory_map()
Virtually all callers of this function do the rounding on their own.
Some do it right, some don't. Instead of doing this in each caller,
do the rounding in efi_add_memory_map(). Change the size parameter
to bytes instead of pages and remove aligning and size calculation in
all callers.
There is no more need to make the original efi_add_memory_map() (which
takes pages as size) available outside the module. Thus rename it to
efi_add_memory_map_pg() and make it static to prevent further misuse
outside the module.
Signed-off-by: Michael Walle <michael@walle.cc>
Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ovidiu Panait [Wed, 6 May 2020 17:38:47 +0000 (20:38 +0300)]
qemu-x86*_defconfig: Enable CONFIG_PCI_INIT_R
Enable CONFIG_PCI_INIT_R for qemux86 and qemux86-64 pci enumeration during
boot in order to eliminate the custom preboot commands in
include/configs/qemu-x86.h.
With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they
are without that config option enabled. However, there are cases such as DM
PCI-based Ethernet devices that need the PCI bus enumerated so that they
can be discovered by their drivers.
Currently, to solve this, some boards enumerate the pci bus using
"pci enum" preboot command, while others do it manually in board files
(in board_init/board_late_init/etc. functions).
In order to possibly make the pci enumeration process uniform across all
boards, introduce CONFIG_PCI_INIT_R Kconfig option.
This change also preserves the current behavior in the !DM_PCI case
(pci_init is run unconditionally at boot).
Tom Rini [Fri, 15 May 2020 20:42:06 +0000 (16:42 -0400)]
Merge branch '2020-05-15-misc-bugfixes'
- A number of symbol name consistency updates
- JFFS2 bugfix
- Use /* fallthrough */ for now to help at least gcc know when we're
intentionally not 'break;'ing in a switch statement, we'll adopt
fallthrough; later on.
- Assorted other fixes
Jan Luebbe [Wed, 13 May 2020 10:26:24 +0000 (12:26 +0200)]
lib: rsa: avoid overriding the object name when already specified
If "object=" is specified in "keydir" when using the pkcs11 engine do
not append another "object=<key-name-hint>". This makes it possible to
use object names other than the key name hint. These two string
identifiers are not necessarily equal.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Bastian Krause <bst@pengutronix.de> Reviewed-by: George McCollister <george.mccollister@gmail.com>
Samuel Holland [Thu, 7 May 2020 23:08:10 +0000 (18:08 -0500)]
spl: Always define preloader_console_init
A large number of boards call preloader_console_init unconditionally.
Currently, they fail to build with CONFIG_SPL_SERIAL=n, because the
function is undefined in that case. To fix the build, always define
preloader_console_init, but make it no-op when CONFIG_SPL_SERIAL=n.
For the few boards that did check for CONFIG_SPL_SERIAL before calling
preloader_console_init, remove the checks, since the function can now
be called unconditionally.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Petr Borsodi [Thu, 7 May 2020 10:25:56 +0000 (12:25 +0200)]
JFFS2: Add useful fields into lists
The inode list uses version and ino, the dirent list uses version and pino.
This information is collected during scanning, reducing accesses to flash
and significantly speeding up ls and read.
Petr Borsodi [Thu, 7 May 2020 10:25:55 +0000 (12:25 +0200)]
JFFS2: Process obsolete nodes as well as accurate ones
Obsolete nodes (ie. without the JFFS2_NODE_ACCURATE flag) were ignored
because they had seemingly invalid crc. This could lead to finding
the phantom node header in obsolete node data.
Trevor Woerner [Wed, 6 May 2020 12:02:37 +0000 (08:02 -0400)]
arch/arm/Makefile: sort machine names
The comment immediately above the block of machine directory names implored
users to keep the macro names sorted, but, alas, this is no longer the case.
Put the list of machine directory names back in alphanumerical order by
CONFIG_* macro name, as the comment asks. Sort all the symbols as though they
all followed the convention of having the string "ARCH_" in the middle of
their definitions.
Trevor Woerner [Wed, 6 May 2020 12:02:36 +0000 (08:02 -0400)]
arm: lpc32xx: move SoC to mach-lpc32xx
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.
Following the checklist from
commit 01f14456306c ("ARM: prepare for moving SoC sources into mach-*"):
[1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
[2] add machine entry to arch/arm/Makefile
[3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
[4] fix the Kconfig file path in arch/arm/Kconfig
[5] (no MAINTAINERS update)
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Jonathan Gray [Fri, 15 May 2020 12:20:34 +0000 (22:20 +1000)]
rsa: don't use malloc.h in rsa-sign.c
stdlib.h is the header for malloc since at least c89/c90.
There is no system malloc.h on OpenBSD and trying to use malloc.h here
falls back to the U-Boot malloc.h breaking the build of qemu_arm64.
Fixes: 336d4615f8 ("dm: core: Create a new header file for 'compat' features") Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Simon Glass [Wed, 6 May 2020 14:03:56 +0000 (08:03 -0600)]
lib: Allow MD5 to be enabled in SPL
At present the MD5 option cannot be enabled by board configs since it has
no Kconfig name. It is generally enabled, so long as FIT support is
present. But not all boards use FIT, particularly in SPL
Fix this and add an option for SPL as well. This allows board code to call
md5() even if FIT support is not enabled.
Jan Kiszka [Mon, 4 May 2020 12:38:31 +0000 (14:38 +0200)]
kbuild: spl: Add shrunk arch-dtbs to targets list
This avoids needless rebuilding.
Fixes: 2f57c95100f2 ("spl: dm: Make it possible for the SPL to pick its own DTB from a FIT") CC: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 4 May 2020 12:38:30 +0000 (14:38 +0200)]
kbuild: spl: Fix parallel build
The dts dir must exists when running this rule.
That missing dependency broke e.g. "make -j" for the am65x targets.
Fixes: 2f57c95100f2 ("spl: dm: Make it possible for the SPL to pick its own DTB from a FIT") CC: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tom Rini [Thu, 14 May 2020 12:44:06 +0000 (08:44 -0400)]
Merge tag 'u-boot-stm32-20200514' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and before relocation
- Many improvment for AV96 board and DHCOR SoM
(add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
- clk: stm32mp1: fix CK_MPU calculation
- DT alignment of stm32mp1 device tree with Linux 5.7-rc2
Tom Rini [Thu, 14 May 2020 12:43:33 +0000 (08:43 -0400)]
Merge tag 'rpi-next-2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi
- fix phy configuration for RPi4's bcmgenet
- sync RPi4's env size with other RPi configs
- add kconfig option to reserver more pages in the EFI mem map
- add support for SDMA which is used by RPi4
- fix corner case boot bug for RPi3 32-bit
Patrick Delaunay [Thu, 30 Apr 2020 13:52:46 +0000 (15:52 +0200)]
ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2
DT alignment with Linux 5.7-rc2, including the kernel commits
431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards 79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards 877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards 7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1 d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c 1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1 bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1 b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards 8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1 fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151 c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1 9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15 82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151 8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node a7959919709e ARM: dts: stm32: Add UART8 pins A pinmux entry on stm32mp1 4d7c53a684da ARM: dts: stm32: Add USART3 pins A pinmux entry on stm32mp1 80ab128332ee ARM: dts: stm32: Add SAI2A pins B pinmux entry on stm32mp1 ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on stm32mp1
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
When the CK_MPU used PLL1_MPUDIV, the current rate is
wrong. The clock must use stm32mp1_mpu_div as a shift
value. Fix the check value used to enter PLL_MPUDIV.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 30 Apr 2020 07:52:13 +0000 (09:52 +0200)]
mmc: stm32_sdmmc2: change the displayed config name
Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to
“STM32 SD/MMC”.
This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the
displayed name "STM32 SDMMC2" is confusing for user, between the
instance of SDMMC and the device identifier of MMC.
Patrick Delaunay [Thu, 30 Apr 2020 14:30:21 +0000 (16:30 +0200)]
arm: stm32mp: activate data cache on DDR in SPL
Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START
Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 30 Apr 2020 14:30:20 +0000 (16:30 +0200)]
arm: stm32mp: activate data cache in SPL and before relocation
Activate the data cache in SPL and in U-Boot before relocation.
In arch_cpu_init(), the function early_enable_caches() sets the early
TLB, early_tlb[] located .init section, and set cacheable:
- for SPL, all the SYSRAM
- for U-Boot, all the DDR
After relocation, the function enable_caches() (called by board_r)
reconfigures the MMU with new TLB location (reserved in
board_f.c::reserve_mmu) and re-enable the data cache.
This patch allows to reduce the execution time, particularly
- for the device tree parsing in U-Boot pre-reloc stage
(dm_extended_scan_fd =>dm_scan_fdt)
- in I2C timing computation in SPL (stm32_i2c_choose_solution())
For example, the result on STM32MP157C-DK2 board is:
1,6s gain for trusted boot chain with TF-A
2,2s gain for basic boot chain with SPL
For information, as TLB is added in .data section, the binary size
increased and the SPL load time by ROM code increased (30ms on DK2).
But early malloc can't be used for TLB because arch_cpu_init()
is executed before the early poll initialization done in spl_common_init()
called by spl_early_init() So it too late for this use case.
And if I initialize the MMU and the cache after this function it is
too late, as dm_init_and_scan and fdt parsing is also called in
spl_common_init().
And .BSS can be used in board_init_f(): only stack and global can use
before BSS init done in board_init_r().
So .data is the better solution without hardcoded location but if you
have size issue for SPL you can deactivate cache for SPL only
(with CONFIG_SPL_SYS_DCACHE_OFF).
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Marek Vasut [Mon, 27 Apr 2020 10:26:42 +0000 (12:26 +0200)]
ARM: stm32: Define I2C EEPROM bus and address on DHCOM
Define I2C EEPROM bus and address, so that the 'eeprom' command uses
the correct ones and does not generate the following error:
eeprom_rw_block: Cannot find udev for a bus 0
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Marek Vasut [Wed, 29 Apr 2020 13:08:38 +0000 (15:08 +0200)]
ARM: dts: stm32: Synchronize DDR setttings on DH SoMs
Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
into use by the board file instead of the default ones. These new DRAM
settings are a better fit for the SoMs.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Marek Vasut [Mon, 27 Apr 2020 11:16:02 +0000 (13:16 +0200)]
ARM: dts: stm32: Fix AV96 and DHCOR split
The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM
and AV96 board") was not applied correctly and in full, and omitted
an important split of the SoM into 3V3 and 1V8 options. The Avenger96
board is based on the 1V8 IO option of the DHCOR SoM, however this is
an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM
regulator to cater for the 96boards 1V8 IO requirements.
Reinstate the split between the 1V8 and 3V3 IO variants.
Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Need Realtek driver to manage in RTL8211F the configuration of the LED.
Initialize LCR (LED Control Register) to configure green LED for Link,
yellow LED for Active
Patrick Delaunay [Wed, 22 Apr 2020 12:29:17 +0000 (14:29 +0200)]
gpio: stm32: support gpio ops in SPL
The GPIO support is needed in SPL to managed the SD cart detect
used on stm32mp157c-ev1 and dk2 board.
So this patch activates the associated code in stm32_gpio.c.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Wed, 22 Apr 2020 12:29:14 +0000 (14:29 +0200)]
board: stm32mp1: set environment variable fdtfile
For booting Linux in the generic distro mechanism and support of
FDTDIR in extlinux.conf , cmd/pxe.c retrieves the FDT file name
from "fdtfile" environment variable.
Dynamically build this variable with compatible of STMicroelectronics
boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
board: stm32mp1: Keep error led ON in case of low power detection
Since commit commit dd2810851eb1 ("stm32mp1: board: support of
error led on ed1/ev1 board") the attended behavior was no more
respected in case of low power source detection on DK2.
The expected behavior is either the error LED keeps blinking for ever,
or blinks 2 or 3 times and must stay ON.
projects / u-boot.git / log