Tom Rini [Wed, 20 Feb 2019 17:28:40 +0000 (12:28 -0500)]
Merge git://git.denx.de/u-boot-x86
- Add support for sound.
Albeit the big changeset, changes are pretty limited to x86 only and a
few new sound drivers used by x86 so I think it would be good to have
this in the next release.
Simon Glass [Sun, 17 Feb 2019 03:25:02 +0000 (20:25 -0700)]
x86: broadwell: Don't bother probing the PCH for pinctrl
At present the pinctrl probes the PCH but since it only uses it to obtain
a PCI address, this is no necessary. Avoiding this fixes one of the two
co-dependent loops in broadwell.
This driver really should be a proper pinctrl driver, but for now it
remains a syscon device.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:56 +0000 (20:24 -0700)]
sandbox: sound: Silence sound for testing
When testing the sound system we don't need the hear the beeps. The
testing works by checking the data that would be emitted. Add a
device-tree property to silence the sound, and enable it for testing.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:55 +0000 (20:24 -0700)]
sound: Add support for Intel HDA
The Intel High-definition Audio is a newer-generation audio system which
provides for transfer of a large number of audio stream, each containing
up to 16 channels.
Add support for HDA as a library which can be used by other drivers.
U-Boot currently uses only two channels (stereo).
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:54 +0000 (20:24 -0700)]
sound: Add uclass operations for beeping
Some audio codecs such as Intel HDA do not need to use digital data to
play sounds, but instead have a way to emit beeps. Add this interface as
an option. If the beep interface is not supported, then the sound uclass
falls back to the I2S interface.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:51 +0000 (20:24 -0700)]
pch: Add ioctl support
At present the PCH has 4 operations and these are reasonably widely used
in the drivers. But sometimes we want to add rarely used operations, and
each of these currently adds to the size of the PCH operations table.
Add an ioctl() method which can be easily expanded without any more impact
on the operations table.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:50 +0000 (20:24 -0700)]
sandbox: pch: Add a test for the PCH uclass
This uclass currently has no tests. Add a sandbox driver and some simple
tests to provide basic coverage.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Use "sandbox,pch" for the compatible string, for consistency] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:49 +0000 (20:24 -0700)]
x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:48 +0000 (20:24 -0700)]
x86: link: Increase malloc size and decrease code size
At present link does not boot since it has outgrown its pre-relocation
malloc() size and its assigned code area. Increase the former and drop
EFI loader support, which adds about 45KB!
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:45 +0000 (20:24 -0700)]
sandbox: Add a note about the growing state_info struct
This struct is getting larger and in some cases is being used for things
which would be better put into a driver. For example hwspinlock is not
used outside of sandbox_hwspinlock.c.
Add a note to encourage people to put things elsewhere.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:43 +0000 (20:24 -0700)]
gpio: Use case-insentive matching on the GPIO name
Allow the 'gpio' command to match GPIO bank names regardless of the case
of each. While these are generally in upper case, it is useful to be able
to provide lower case with the command.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:42 +0000 (20:24 -0700)]
gpio: Show inactive GPIOs when explicitly requested
At present the gpio command only shows GPIOs which are marked as in use.
This makes sense with 'gpio status' since we already have the '-a' flag
to indicate that all GPIOs should be shown. But when a particular GPIO is
requested, it seems better to always display it. At present the request is
simply ignored.
For example if GPIO a10 is not in use, then:
> gpio status a10
shows nothing, not even the function being used for that GPIO. With this
change, it shows the pin status:
> gpio status a10
a10: input: 0 [ ]
Add an extra parameter for this to avoid changing the existing flag
parameter.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the 'gpio' command in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:39 +0000 (20:24 -0700)]
i2c: designware: Add error checking on init
At present this driver does not check whether it is able to actually
communicate with the I2C controller. It prints a timeout message but still
considers the probe to be successful.
To fix this, add some checking that the init succeeds.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Simon Glass [Sun, 17 Feb 2019 03:24:38 +0000 (20:24 -0700)]
dm: syscon: Don't require a regmap for PCI devices
At present it is not possible to use the syscon devices for PCI devices
since a regmap is required. Since PCI uses a 3-cell address the conversion
of the 'reg' property to an address always fails. In any case, the regmap
is not useful with PCI since devices are accessed through the PCI bus
which regmap does not support.
Add a special case for PCI syscon devices, so that they don't set up a
regmap.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:37 +0000 (20:24 -0700)]
log: Allow #define LOG_DEBUG to enable logging in a file
At present it is possible to '#define DEBUG' at the top of a file which
causes all debug() statements in that file to become active. There is
currently no equivalent with logging, but this is a useful function.
Add a LOG_DEBUG define along with documentation.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Sat, 16 Feb 2019 21:36:29 +0000 (16:36 -0500)]
omap3_beagle: Update for DM SPL support
- Switch to using the omap3-u-boot.dtsi file for needed properties.
- Remove a few SPL features to free up more SRAM space.
- Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to
worry about X-Loader at this point anymore.
- A few related updates to SPL options as part of switching to DM SPL.
Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
Adam Ford [Sat, 16 Feb 2019 19:31:24 +0000 (13:31 -0600)]
ARM: omap3_logic: Enable SPL booting device tree
With the generic omap3-u-boot.dtsi file available, this patch
increased the memory of the various incarnations of the omap3_logic
board, and points their respective u-boot.dtsi files to the newly
created generic one, and removes the PLATDATA from the board file.
These are all done at once because the're all utilizing the same
omap3logic.c board file.
Adam Ford [Fri, 15 Feb 2019 02:13:53 +0000 (20:13 -0600)]
ARM: da8xxevm: Add NAND instructions for da850-evm to README
The README.da850 file continues information on how to burn NAND
for the LCDK, but not the DA850-EVM. This patch adds both the
commands and dip switch instructions for burning and booting
NAND.
Adam Ford [Wed, 13 Feb 2019 19:06:37 +0000 (13:06 -0600)]
ARM: da850evm: Increase Malloc Size
The SPI NOR frameware was recently updated, but they require a little
more memory that we had previosly allocated, so it stopped booting.
This patch doubles the size of CONFIG_SPL_SYS_MALLOC_F_LEN to 0x800.
Fixes: c4e8862308d4 ("mtd: spi: Switch to new SPI NOR framework") Signed-off-by: Adam Ford <aford173@gmail.com>
hikey: Allow environment to store in eMMC and increase bootdelay
Current Hikey configuration allows us to store u-boot environment on uSD
card. But this will be useless if uSD card is not inserted, hence use
the onboard eMMC memory for storing environment at Boot1 partition.
While we are at it, let's increase the boot delay to 10s also.
SPL currently does not check uImage CRCs when loading U-Boot.
This patch adds checking the uImage CRC when SPL loads U-Boot. It does
this by reusing the existing config option SPL_CRC32_SUPPORT to allow
leaving out the CRC check on boards where the additional code size or
boot time is a problem (adding the CRC check currently adds ~1.4 kByte
to flash).
The SPL_CRC32_SUPPORT config option now gets enabled by default if SPL
support for legacy images is enabled to check the CRC on all boards
that don't actively take countermeasures.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Currently there are two problems in 'bootelf -p' (load elf by segments)
command:
- bss section is not flushed, so booted elf can have non zero values
in bss;
- at least on ARM there are 'CACHE: Misaligned operation at
range...' warnings
Use p_memsz instead of p_filesz during cache flushing for elf segment.
p_filesz doesn't include zero initialized memory (e.g. bss section),
which also should be flushed.
Align these cache flushes to line boundaries.
Signed-off-by: Kurban Mallachiev <mallachiev@ispras.ru>
This commit converts the brxre1 board to DM,
for this we have todo following things:
- add a devicetree-file for this board
- drop all obsolete settings from board header-file
- use dm_i2c_xxx calls for read/write to the resetcontroller
- request gpios before operate them
Serues-cc: trini@konsulko.com Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Before the patch scsi would report the same device number for all SCSI
devices, e.g.
Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Device 0: (1:0) Vendor: ATA Prod.: Rev:
Type: Hard Disk
Capacity: not available
With the patch the same device number is reported as is used in
scsi_read():
Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Device 1: (1:0) Vendor: ATA Prod.: Rev:
Type: Hard Disk
Capacity: not available
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Peng Ma [Wed, 30 Jan 2019 11:19:40 +0000 (19:19 +0800)]
configs: ls1021a: enable sata configs for all ls1021a defconfigs
Add CONFIG_AHCI CONFIG_SATA_CEVA CONFIG_DM_SCSI for some ls1021a
defconfigs that missing one of them or more.
enable CONFIG_DM_MMC for some defconfigs to support CONFIG_BLK
Support sata for all ls1021a defconfigs
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Peng Ma [Wed, 30 Jan 2019 11:18:43 +0000 (19:18 +0800)]
configs: ls1012afrwy: enable sata configs for all ls1012afrwy defconfigs
Add CONFIG_AHCI CONFIG_SATA_CEVA CONFIG_DM_SCSI for some ls1012afrwy
and ls1012afrwy defconfigs that missing one of them or more.
Support sata for all ls1012afrwy defconfigs
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Peng Ma [Wed, 30 Jan 2019 11:17:44 +0000 (19:17 +0800)]
configs: ls208xa: enable sata configs for all ls208xa defconfigs
Add CONFIG_AHCI CONFIG_SATA_CEVA CONFIG_DM_SCSI for some ls208xardb
and ls208xaqds defconfigs that missing one of them or more.
enable CONFIG_DM_MMC for some defconfigs to support CONFIG_BLK
Support sata for all ls208xa defconfigs
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Peng Ma [Wed, 30 Jan 2019 11:16:08 +0000 (19:16 +0800)]
configs: ls1088a: enable sata configs for all ls1088a defconfigs
Add CONFIG_AHCI CONFIG_SATA_CEVA CONFIG_DM_SCSI for some ls1088ardb
and ls1088aqds defconfigs that missing one of them or more.
Support sata for all ls1088a defconfigs
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Peng Ma [Wed, 30 Jan 2019 11:14:47 +0000 (19:14 +0800)]
configs: ls1046a: enable sata configs for all ls1046a defconfigs
Add CONFIG_AHCI CONFIG_SATA_CEVA CONFIG_DM_SCSI for some ls1046ardb
and ls1046aqds defconfigs that missing one of them or more.
enable CONFIG_DM_MMC for some defconfigs to support CONFIG_BLK
Support sata for all ls1046a defconfigs
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Peng Ma [Wed, 30 Jan 2019 11:13:32 +0000 (19:13 +0800)]
configs: ls1043aqds: enable sata configs for all ls1043aqds defconfigs
Add CONFIG_AHCI CONFIG_SATA_CEVA CONFIG_DM_SCSI for some ls1043aqds
defconfigs that missing one of them or more.
Support sata for all ls1043aqds defconfigs
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Peng Ma [Wed, 30 Jan 2019 11:11:49 +0000 (19:11 +0800)]
armv8: ls1043a: move SCSI_AHCI and SCSI to arm/Kconfig
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface
support.
this changed is to fixed the ls1043ardb compile warning as fallows:
===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the
v2019.07 release. Failure to update by the deadline may
result in board removal.See doc/driver-model/MIGRATION.txt
for more info.
====================================================
Signed-off-by: Peng Ma <peng.ma@nxp.com>
[PK: reword the patch subject] Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.
Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
or not? if it is (fsl_serdes_init has already enabled the dpmac), then
don't enable it.
Priyanka Jain [Mon, 29 Oct 2018 09:37:36 +0000 (09:37 +0000)]
drivers/ddr/fsl: Update fsl_ddr_board_options as weak function
fsl_ddr_board_options is generally defined in board
board's ddr.c, but some boards like lx2160ardb board
does not need this function.
Defining fsl_ddr_board_options as weak function to
resolve compilation errors for such boards.
Ang, Chee Hong [Mon, 18 Feb 2019 04:07:50 +0000 (20:07 -0800)]
ARM: socfpga: stratix10: Return valid error code from FPGA driver
This patch prevent the Stratix 10 FPGA driver incorrectly return the
transaction ID as the mailbox error code. It should always return the
actual mailbox error code from SDM firmware.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.
This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.
Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.
To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>