Claudius Heine [Wed, 4 Mar 2020 14:23:12 +0000 (15:23 +0100)]
imx: imx8m: Don't use the addr parameter of reset_cpu
imx8m has the only implementation of `reset_cpu` which does not ignore
the addr parameter and instead gives it some meaning as the base address
of watchdog registers. This breaks convention with the rest of U-Boot
where the parameter is ignored and callers are passing in 0.
Fixes: d2041725e84b ("imx8m: restrict reset_cpu") Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
Claudius Heine [Wed, 4 Mar 2020 14:23:11 +0000 (15:23 +0100)]
imx: imx8m*: Remove do_reset from board files
Use the `do_reset` implementation of `arch/arm/lib/reset.c` in SPL
instead. It is very close to what is done here, anyway, and plays
more nicely with the rest of U-Boot than adding a custom `do_reset`
implementation into board files.
`do_reset` from `arch/arm/lib/reset.c` calls `reset_cpu` with 0 as the
addr parameter while the boards are passing WDOG1_BASE_ADDR. This is
ok because the `reset_cpu` implementation uses WDOG1_BASE_ADDR by
default if 0 is passed in.
Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.
The module also adds some commands:
- snvs_cfg: Configure the SNVS HP and LP registers
- snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
- tamper_pin_cfg: Change the configuration of the tamper pins
- snvs_clear_status: Allow to write to LPSR and LPTDSR to clear
status bits
Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 14 Nov 2019 05:20:43 +0000 (21:20 -0800)]
imx8: Update SCFW API to version 1.5
Sync the latest SCFW API with below commit 6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add
interfaces for PM resource reset and read/write SNVS security
violation and tamper DGO registers.
Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 9 Dec 2019 08:47:18 +0000 (00:47 -0800)]
imx8m: Enable WDOG_B for timeout
When doing reset_cpu, in normal case the WDOG_B outputs immediately
after we clean WDA bit. But on mscale, the WDOG_B may be later than
internal reset, and cause PMIC not reset. As we enabled the SD3.0
support, the PMIC must be reset to reset SD card.
Change the reset_cpu to enable the WDOG_B for timeout as well, and set
WDOG timeout to 1s.
Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 24 Mar 2020 02:54:29 +0000 (19:54 -0700)]
imx8mm: clock: fix fracpll decode issue
The fracpll decoding is using the bit definitions for int pll. Most of
them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK
for fracpll and correct all bit definitions in fracpll decoding.
Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Fri, 25 Oct 2019 08:28:48 +0000 (01:28 -0700)]
imx8mq: Enable eMMC HS400 and SD UHS mode on EVK
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.
The change also needs to set usdhc clock to 400Mhz, and add the
off-on-delay-us to SD reset pin, otherwise some SD cards will
fail to select UHS mode in re-initialization.
Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 12 Dec 2018 10:47:58 +0000 (02:47 -0800)]
imx8mn: Update speed grade
imx8mn speed grade fuse uses new definitions as below. So have
to update get_cpu_speed_grade_hz function to match it.
SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz
xx 0000 2300
xx 0001 2200
xx 0010 2100
xx 0011 2000
xx 0100 1900
xx 0101 1800
xx 0110 1700
xx 0111 1600
xx 1000 1500
xx 1001 1400
xx 1010 1300
xx 1011 1200
xx 1100 1100
xx 1101 1000
xx 1110 900
xx 1111 800
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Ye Li [Wed, 17 Oct 2018 06:12:37 +0000 (23:12 -0700)]
imx8mm: Update CPU speed grading
According to iMX8MM datasheet (IMX8MMIEC_Rev_D and IMX8MMCEC_Rev_D),
the speed grading for imx8mm is 800Mhz, 1.2Ghz, 1.6Ghz and 1.8Ghz.
Update them to get_cpu_speed_grade_hz function.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Fri, 24 Apr 2020 19:37:26 +0000 (21:37 +0200)]
ARM: imx: imx8mm: Add missing clock entries for FEC clock
All the FEC ethernet clock entries for iMX8MM are missing, while they
are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC
ethernet gets bogus clock information otherwise which makes ethernet
inoperable.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
platforms.
Simon Glass [Sun, 26 Apr 2020 15:12:58 +0000 (09:12 -0600)]
x86: Move coreboot-table detection into common code
To support detecting booting from coreboot, move the code which locates
the coreboot tables into a common place. Adjust the algorithm slightly to
use a word comparison instead of string, since it is faster.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:56 +0000 (09:12 -0600)]
pci: Avoid auto-config when chain loading
When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:55 +0000 (09:12 -0600)]
x86: cpu: Skip init code when chain loading
When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:53 +0000 (09:12 -0600)]
x86: fsp: Allow skipping init code when chain loading
It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.
When U-Boot is not the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.
Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:19:51 +0000 (09:19 -0600)]
acpi: Put table-setup code in its own function
We always write three basic tables to ACPI at the start. Move this into
its own function, along with acpi_fill_header(), so we can write a test
for this code.
Simon Glass [Sun, 26 Apr 2020 15:19:50 +0000 (09:19 -0600)]
acpi: Move acpi_add_table() to generic code
Move this code to a generic location so that we can test it with sandbox.
This requires adding a few new fields to acpi_ctx, so drop the local
variables used in the original code.
Also use mapmem to avoid pointer-to-address casts which don't work on
sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:47 +0000 (09:19 -0600)]
acpi: Convert part of acpi_table to use acpi_ctx
The current code uses an address but a pointer would result in fewer
casts. Also it repeats the alignment code in a lot of places so this would
be better done in a helper function.
Update write_acpi_tables() to make use of the new acpi_ctx structure,
adding a few helpers to clean things up.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:45 +0000 (09:19 -0600)]
acpi: Add a binding for ACPI settings in the device tree
Devices need to report various identifiers in the ACPI tables. Rather than
hard-coding these in drivers it is typically better to put them in the
device tree.
* don't copy GUIDs for no reason
* shorten print format strings by using variable names
* don't use the run-time table to access exported functions
* check the result of malloc() (fixes Coverity CID 300331)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Do not recreate a variable name that we already have as u16 string.
* Check the return value of malloc()
* EFI_NOT_FOUND cannot occur for a variable name returned by
GetNextVariableName(). Remove a print statement.
* Don't copy a GUID for no reason.
* Don't use the run-time service table to call exported functions.
* Don't pass NULL to show_efi_boot_opt_data() (fixes Coverity CID 300338).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
if either the partition was an EFI system partition or the bootable flag
was set.
Turn info field 'bootable' into a bit mask with separate bits for bootable
and EFI system partition.
This will allow us to identify the EFI system partition in the UEFI
sub-system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
If udisksctl is present
test/py/tests/test_efi_secboot/conftest.py
fails because the disk image is never mounted.
Normal users can only mount fuse file systems. Unfortunately fusefat is
still in an experimental state and seems not to work here correctly.
So as we have to be root or use the sudo command anyway delete all coding
referring to udisksctl.
--
We should not use mount point /mnt as this directory or one of its
sub-directories might already be in use as active mount points. Instead
create a new directory in the build root as mount point.
--
Remove debug print statements that have been commented out. print without
parentheses is anyway invalid in Python 3. And pytest anyway filters out
the output if there is no exception reported.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Probe the FMan MACs based on the device tree while
retaining the legacy code/functionality.
One notable change introduced here is that, for DM_ETH,
the name of the interfaces is corrected to the fmX-macY
format, that avoids the referral to the MAC block names
which were incorrect for FMan v3 devices (i.e. DTSEC,
TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1).
The legacy code is left unchanged in this respect.
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
LS1046A SoC. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
LS1043A SoC. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Add the QorIQ DPAA Frame Manager v3 device tree nodes description.
The device tree fragments are copied over with little modification
from the Linux kernel source code.
Biwen Li [Fri, 17 Apr 2020 09:37:01 +0000 (17:37 +0800)]
configs: ls1012afrwy: drop env qspi_bootcmd
Drop useless environment variable installer and qspi_bootcmd
for ls1012afrwy.
Only 2 MB nor flash in ls1012afrwy. So cannot get kernel(30 MB) from
the nor flash, then drop it.
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Yuantian Tang [Thu, 19 Mar 2020 08:48:25 +0000 (16:48 +0800)]
armv8: ls1028aqds: add lpuart dts support
Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that
it can be used as common device tree for lpuart and duart.
Add lpuart device tree and duart device tree respectively
for qds which are used with duart and lpuart console.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:46 +0000 (16:47 +0200)]
arm: dts: ls1088ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the external MDIO nodes and describe the PHYs (8 x
VSC8514, AQR105). Also, add phy-handles for the dpmacs to their
associated PHY.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:45 +0000 (16:47 +0200)]
arm: dts: ls2088ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the external MDIO nodes and describe the PHYs (4 x AQR405
and 4 x CS4340). Also, add phy-handles for the dpmacs to their
associated PHY.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:44 +0000 (16:47 +0200)]
arm: dts: lx2160ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.
Also, annotate the EMDIO1 node and describe the 2 AR8035 RGMII PHYs and
the 2 AQR107 PHYs. Also, add phy-handles for the dpmacs to their
associated PHY.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:40 +0000 (16:47 +0200)]
board: ls2088ardb: transition to DM_ETH
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for
DPAA2 Ethernet devices. Compile out any unnecessary setup when
CONFIG_DM_ETH is activated.
Also, force the PCI devices to be enumerated at probe time.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:39 +0000 (16:47 +0200)]
board: ls1088ardb: transition to DM_ETH
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for
DPAA2 Ethernet devices. Compile out any unnecessary setup when
CONFIG_DM_ETH is activated.
Also, force the PCI devices to be enumerated at probe time.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:38 +0000 (16:47 +0200)]
drivers: net: fsl-mc: add support for CONFIG_DM_ETH
Make any adjustments necessary in order to support DPAA2 devices probed
using CONFIG_DM_ETH. While at it, fixup some styling issues aroung the
switch-case statement.
Ioana Ciornei [Wed, 18 Mar 2020 14:47:37 +0000 (16:47 +0200)]
drivers: net: ldpaa: add DTS based probing support
When CONFIG_DM_ETH is enabled DPAA2 network interfaces will now probe
based on DTS nodes with the "fsl,qoriq-mc-dpmac" compatible.
In this case, transform the ldpaa_eth driver into a UCLASS_ETH driver
and reuse the _open()/_tx()/_stop() functions already inplemented.
For the moment, the ldpaa_eth driver will support both configurations:
with or without CONFIG_DM_ETH enabled. Any 'struct eth_device' occurrence
now has a matching 'struct udevice' made mutually exclusive based on the
state of CONFIG_DM_ETH.
Marek Vasut [Sun, 5 Apr 2020 16:08:58 +0000 (18:08 +0200)]
ARM: dts: rmobile: Scrub unused DT nodes
Remove DT nodes which are not used by U-Boot, like audio and video in/out
nodes. This saves about 35 kiB on the resulting U-Boot binary without any
impact on functionality.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
projects / u-boot.git / log