Tom Rini [Mon, 29 Jan 2024 19:49:25 +0000 (14:49 -0500)]
Merge patch series "Move framebuffer reservation for SPL to RAM end"
Devarsh Thakkar <devarsht@ti.com> says:
Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.
Also catch the bloblist before starting reservations to avoid the same
problem.
While at it, also fill missing fields in video handoff struct before
passing it to next stage.
This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:21 +0000 (21:25 +0530)]
video: Fill video handoff in video post probe
Fill video handoff fields in video_post_probe as at this point we have
full framebuffer-related information.
Also fill all the fields available in video hand-off struct as those
were missing earlier and U-boot framework expects them to be filled for
some of the functionalities.
While filling framebuffer size in video hand-off structure use the
actual framebuffer region size as derived from gd->video_top and
gd->video_bottom instead of directly using the size populated in
video_uc_plat as it contains unaligned size.
Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:20 +0000 (21:25 +0530)]
video: Skip framebuffer reservation if already reserved
Skip framebufer reservation if it was already reserved from previous
stage and whose information was passed using a bloblist.
Return error in case framebuffer information received from bloblist is
invalid i.e NULL or empty.
While at it, improve the debug message to make it more clear that
address in discussion is of framebuffer and not bloblist and also match
it with printing scheme followed in video_reserve function.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:19 +0000 (21:25 +0530)]
common/board_f: Catch bloblist before starting reservations
Start reservations needed for init sequence only after catching
bloblists from previous stage.
This is to avoid catching bloblists in the middle causing gaps while
u-boot is reserving.
Adjust the relocaddr as per video hand-off information received from
previous stage so that further reservations start only after regions
reserved for previous stages
Skip reservation for video memory if it was already filled by a
bloblist.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:18 +0000 (21:25 +0530)]
board: ti: am62x: evm: Remove video_setup from spl_board_init
Remove video_setup from evm_init sequence since video memory is getting
called at an earlier place to make sure video memory is reserved at
the end of RAM.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:17 +0000 (21:25 +0530)]
arm: mach-k3: common: Reserve video memory from end of the RAM
Setup video memory before page table reservation using
"spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
reserved from the end of RAM.
This is done to enable the next stage to directly skip the
pre-reserved area from previous stage right from the end of RAM without
having to make any gaps/holes to accommodate those regions which was the
case before as previous stage reserved region not from the end of RAM.
Use gd->ram_top instead of local ram_top and update gd->reloc_addr after
each reservation to ensure further regions are reserved properly.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Devarsh Thakkar [Tue, 5 Dec 2023 15:55:16 +0000 (21:25 +0530)]
spl: Enforce framebuffer reservation from end of RAM
Add an API which enforces framebuffer reservation from end of RAM.
This is done so that next stage can directly skip this region before
carrying out further reservations.
Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 29 Jan 2024 15:57:42 +0000 (10:57 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Some cleanups in header files: those do not affect the generated
binaries at all.
- The usual update of DT files from the kernel repo, mostly adding new
board files this time. On the wake of this there is one defconfig to
enable a new board, some H618 TV box branded as "Transpeed".
- Samuel's series to support SPL FIT image loading for 32-bit SoCs as
well, so far this was restricted to ARM64 boards. I refrained from
automatically enabling this everywhere, instead this requires user
intervention during board configuration. This allows to ship the
"crust" management processor firmware on H3 boards, which enables
better power saving.
- One defconfig for an older H3 board. There was a close-by defconfig
for a related board, but there are some differences which deserve a
separate file.
- Support for the EMAC driver to work with fixed-link PHYs, which allows
to directly wire the MAC to a switch IC.
Love Kumar [Fri, 19 Jan 2024 14:37:13 +0000 (20:07 +0530)]
test/py: scsi: Add test for scsi commands
Add a following test cases for scsi commands:
scsi_reset - To reset SCSI controller
scsi_info - To show available SCSI devices
scsi_scan - To (re-)scan SCSI bus
scsi_device - To show or set surrent device
scsi_part - To print partition table of selected SCSI device
Love Kumar [Fri, 19 Jan 2024 14:26:02 +0000 (19:56 +0530)]
test/py: usb: Add tests for USB device
Add the test cases for usb commands to test its various functionality
such as start, stop, reset, info, tree, storage, dev, part, ls, load,
and save. It also adds different file systems cases such as fat32, ext2
and ext4.
Love Kumar [Fri, 19 Jan 2024 14:25:50 +0000 (19:55 +0530)]
test/py: mmc: Add tests for MMC device
Add the test cases for mmc commands to test its various functionality
such as mmc list, dev, info, rescan, part, ls, load, and save. It also
adds different file systems cases such as fat32, ext2 and ext4.
Love Kumar [Fri, 19 Jan 2024 10:01:29 +0000 (15:31 +0530)]
test/py: secure: Add secure tests for Zynq & ZynqMP
Add test cases to verify the different type of secure boot images loaded
at DDR location for AMD's ZynqMP SoC. It also adds tests authentication
and decryption functionality using AES and RSA features for Zynq.
Love Kumar [Fri, 19 Jan 2024 05:38:34 +0000 (11:08 +0530)]
test/py: gpio: Add gpio pins generic test
Add gpio pins generic test for the set of gpio pin list to test various
gpio related functionality, such as the input, set, clear, and toggle,
it also tests the input and output functionality for shorted gpio pins.
This test depends on boardenv* configuration to define gpio pins names.
Caleb Connolly [Tue, 2 Jan 2024 11:55:30 +0000 (11:55 +0000)]
pytest: update requirements.txt
Update pygit2 and py to their latest versions. Even in the venv pygit2
still links against the system libgit2 library which is failing on
latest Arch Linux.
The py library also needs updating to fix a KeyNotFound exception during
test initialisation.
Samuel Holland [Tue, 31 Oct 2023 05:17:41 +0000 (00:17 -0500)]
sunxi: Consider SPL size limitations for FIT loading
Now that 32-bit SoCs can load U-Boot proper (and possibly other firmware)
from a FIT, people can use that by enabling CONFIG_SPL_LOAD_FIT.
However SPL_FIT_IMAGE_TINY is required to stay within the 24 or 32 KiB
SPL size limit on early SoCs; for consistency, enable it everywhere.
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: drop unconditional FIT image enablement for all SoCs] Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Tue, 31 Oct 2023 05:17:40 +0000 (00:17 -0500)]
sunxi: binman: Support FIT generation for 32-bit SoCs
Some 32-bit SoCs can use SCP firmware to implement additional PSCI
functionality, such as system suspend. In order to load this firmware
from SPL, we need to generate and use a FIT instead of a legacy image.
Adjust the binman FIT definition so it does not rely on TF-A BL31, as
this is not used on 32-bit SoCs. Instead, after loading the firmware,
U-Boot proper is executed directly. This requires to provide an
entry point property for the U-Boot image node, which confuses some
loaders like sunxi-fel, so protect that to only be used if we have no
BL31.
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: filter U-Boot entry point property] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Samuel Holland [Tue, 31 Oct 2023 05:17:39 +0000 (00:17 -0500)]
sunxi: binman: Move BL31 and SCP firmware addresses to Kconfig
This is easier to read than the #ifdef staircase, provides better
visibility into the memory map (alongside the other Kconfig
definitions), and allows these addresses to be reused from code.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Tue, 31 Oct 2023 05:17:38 +0000 (00:17 -0500)]
sunxi: spl: Disable padding from SPL_PAD_TO
Starting with H6, Allwinner removed the artificial 32 KiB SPL size limit
from the boot ROM. Now SPL size is only limited by the available SRAM.
This limit ranges from 152 KiB on H6 to a whopping 2052 KiB on R329. To
take advantage of this additional space, we must increase SPL_MAX_SIZE.
Since we do not want to unnecessarily pad SPL out to these giant sizes,
we must set SPL_PAD_TO to zero. This causes no problems because binman
already takes care of appending the SPL payload at the right offset.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Chuanhong Guo [Thu, 28 Dec 2023 05:29:15 +0000 (13:29 +0800)]
sunxi: add defconfig for nanopi_duo2
FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and
Ampak AP6212 WiFi module. The device-tree for it is already
available in u-boot source tree. Add a default config for it.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[Andre: enable USB gadgets] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Maksim Kiselev [Sat, 20 Jan 2024 16:26:24 +0000 (19:26 +0300)]
net: sun8i-emac: Add support for fixed-link phy
Make the "phy-handle" property optional, which allows support
for a fixed-link phy configuration.
Thus if the "phy-handle" is present in a DT, then driver will work as
before. Otherwise, phyaddr initialization will not be necessary,
as it is not needed in case of a fixed-link config.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 21 Jan 2024 00:06:00 +0000 (00:06 +0000)]
sunxi: dts: update devicetree files from Linux-v6.8-rc1
Sync the devicetree files from the official Linux kernel tree, v6.8-rc1.
This time only small changes in the existing files, but five new boards
got added, which opens the door for their respective defconfig files.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:06 +0000 (14:46 +0900)]
mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID
Infineon(Cypress) S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with
Octal interface. It is a dual-die package parts and has same features
with existing S28 series.
Enabling Octal DTR mode in multi-die package parts requires reister setup
for each die. That can be done by simple for-loop. write_enable() takes
effect to all die at once so we can call it before the loop. Besides we
can replace spi_mem_exec_op() calls with spansion_read/write_any_reg().
And finally, we must mask CFR2V[7:4] when changing dummy cycles, as
CFR2V[7] indicates current addressing mode and that should be 1 (4-byte
address mode) for multi-die package parts.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:04 +0000 (14:46 +0900)]
mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 and S28
s28hx_t_post_bfpt_fixup() fixes erase opcode, erase size, and page size.
s25_post_bfpt_fixup() is doing same thing including multi-die support.
We can consolidate s28hx_t_post_bfpt_fixup() and s25_post_bfpt_fixup()
into one named s25_s28_post_bfpt_fixup().
In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to
be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing
but it works actually (confirmed).
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:03 +0000 (14:46 +0900)]
mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28
s28hx_t_setup() only checks sector layout setting. To support multi-die
package parts like S28HS02GT, it needs to check device size and assign
ready() hook for multi-die package parts. These are covered in s25_setup()
so we can consolidate s28hx_t_setup() and s25_setup() into one named
s25_s28_setup().
spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be
removed since there is no op that makes device busy state before setup.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:02 +0000 (14:46 +0900)]
mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR mode
s25_mdp_ready() handles status polling for multi-die package parts that
requires to read and check status register for each die. To support
S28HS02GT(dual-die package with Octal DTR support), rename function and
use nor->rdsr_dummy in octal DTR mode.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:01 +0000 (14:46 +0900)]
mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28
Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode.
Instead, it supports CLPEF(0x82) which has the same functionality as CLSR.
spansion_sr_ready() is for multi-die package parts including S28HS02GT, so
we need to use CLPEF instead of CLSR.
This change does not affect to S25x02GT which uses spansion_sr_ready() as
S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30).
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:46:00 +0000 (14:46 +0900)]
mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode
In Infineon multi-die package parts, we need to use Read Any Register op
to read status register in 2nd or further die. Infineon S28HS02GT is
dual-die package and supports Octal DTR interface. To support this,
spansion_read_any_reg() needs to be reworked. Implementation is similar
to existing read_sr() that already supports Octal DTR mode.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:45:59 +0000 (14:45 +0900)]
mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28
s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector
layout (32 x 4KB sectors overlaid at bottom address) and doing same thing.
Consolidate them into single helper named s25_s28_erase_non_uniform().
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Takahiro Kuwano [Fri, 22 Dec 2023 05:45:58 +0000 (14:45 +0900)]
mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28
Some macro definitions used in Infineon(Cypress) S25 and S28 series are
redundant and some have inconsistent prefix. This patch removes
redundant ones and renames some to have same prefix as others.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Kankan Sun <ssunkkan@gmail.com>
[jagan: update the commit message] Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tejas Bhumkar [Sun, 28 Jan 2024 06:37:46 +0000 (12:07 +0530)]
spi: cadence_qspi: Address the comparison failure for 0-8 bytes of data
The current implementation encounters issues when testing data ranging
from 0 to 8 bytes. This was confirmed through testing with both ISSI
(IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.
Upon investigation, it was observed that utilizing the
"SPI_NOR_OCTAL_READ" flag and attempting to read less than 8 bytes in
STIG mode results in a read failure, leading to a compare test failure.
To resolve this issue, the CMD_4BYTE_FAST_READ opcode is now utilized
instead of CMD_4BYTE_OCTAL_READ, specifically in SDR mode.
This is based on patch series:
https://lore.kernel.org/all/cover.1701853668.git.tejas.arvind.bhumkar@amd.com/
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tejas Bhumkar [Wed, 27 Dec 2023 16:28:39 +0000 (21:58 +0530)]
mtd: spi-nor-ids: Add is25lx512 chip
Added support for the ISSI OSPI flash part IS25LX512M.
Initial testing was performed on the Tenzing-se1 board using
SDR mode, covering basic erase, write, and readback operations.
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Maksim Kiselev [Thu, 21 Dec 2023 10:13:30 +0000 (13:13 +0300)]
spi: dw: add check for Rx FIFO overflow
If even one byte is lost due to Rx FIFO overflow then we will never
exit the read loop. Because the (priv->rx != priv->rx_end) condition will
be always true.
Let's check if Rx FIFO overflow occurred and exit the read loop
in this case.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:27 +0000 (00:12 +0000)]
sunxi: simplify U-Boot proper only builds
At the moment every Allwinner board builds and requires an SPL, even
though we select this individually in each _defconfig file.
For experiments and for early bringup of new SoCs it would be beneficial
to only build U-Boot proper, for instance to postpone a tedious SPL port
(including DRAM support) in the initial phase.
Protect some SPL related symbols that we unconditionally select at the
moment with "if SPL", to avoid Kconfig conflicts when CONFIG_SPL is
disabled.
This alone does not cleanly build U-Boot proper only yet, but gets it
far enough so that the binary can be harvested.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:26 +0000 (00:12 +0000)]
sunxi: remove common.h inclusion
The usage of the common.h include file is deprecated, and has already
been removed from several files.
Get rid of all inclusions in the arch/arm/mach-sunxi directory. Most
files actually don't need the header at all, for the few others just
include the headers that we actually require.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:24 +0000 (00:12 +0000)]
sunxi: sun9i: remove unneeded base addresses from header
The cpu_sun9i.h header file defined the base addresses for quite some
peripherals of the Allwinner A80 CPU, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:23 +0000 (00:12 +0000)]
sunxi: sun4i: remove unneeded base addresses from header
The cpu_sun4i.h header file defined the base addresses for quite some
peripherals of earlier Allwinner CPUs, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:22 +0000 (00:12 +0000)]
sunxi: sun50i-h6: remove unneeded base addresses from header
The cpu_sun50i_h6.h header file defined the base addresses for quite some
peripherals of the Allwinner H6 and related CPUs, even though we now only
use a fraction of that.
Most of the addresses are now either read from the DT, or were never used
in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 3 Jan 2024 00:12:21 +0000 (00:12 +0000)]
sunxi: cleanup sunxi-common.h
The sunxi-common.h configs header used to contain a lot of random
Allwinner platform related constants, but over the years we moved a lot
of those definitions out there.
Clean up the file to remove outdated comments which are leftovers from
the olden days. Also remove the definition of LOW_LEVEL_SRAM_STACK,
which is actually used nowhere in the whole source tree.
This also uses the opportunity to add some section comments that helps
structuring the header file and improving readability.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Marek Vasut [Sun, 21 Jan 2024 17:31:23 +0000 (18:31 +0100)]
ARM: renesas: Drop include common.h
The header file is not necessary in either of those files,
remove it as common.h is going away.
Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c
to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk
and r8a77970_v3msk .
Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure
due to missing definition of struct bd_info . Include errno.h in grpeach.c
to fix build error due to missing definition of EINVAL.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tom Rini [Sat, 27 Jan 2024 12:53:29 +0000 (07:53 -0500)]
Merge tag 'smbios-2024-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request smbios-2024-04-rc1-2
* Add missing field to SMBIOS type 2 structure definition
* Provide smbios command to display smbios table
* Enable the command on sandbox and qemu_arm64_defconfig
* Provide a python test for the smbios command
* Fix copying SMBIOS 2.1 table from QEMU
* Correct EFI TCG measurement to assume SMBIOS 3 table
Masahisa Kojima [Thu, 25 Jan 2024 01:11:28 +0000 (10:11 +0900)]
smbios: use struct_table_length to get SMBIOS 2.1 total table length
The current code convert the SMBIOS 2.1 entry point structure to
SMBIOS 3.0 entry point structure. The max_struct_size member in
SMBIOS 2.1 entry point structure indicates
"Size of the largest SMBIOS structure, in bytes".
We need to use struct_table_length instead.
Fixes: 1c5aab803c0b ("smbios: copy QEMU tables") Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Masahisa Kojima [Fri, 26 Jan 2024 00:53:42 +0000 (09:53 +0900)]
efi_loader: migrate SMBIOS 3.0 entry point structure for measurement
Current U-Boot only supports the SMBIOS 3.0 entry point structure.
TCG2 measurement code should migrate to SMBIOS 3.0 entry
point structure.
efi_selftest tcg2 test also needs to be updated, and expected
PCR[1] result is changed since guid for SMBIOS EFI system table
uses different guid SMBIOS3_TABLE_GUID instead of SMBIOS_TABLE_GUID.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
cmd: provide command to display SMBIOS information
U-Boot can either generated an SMBIOS table or copy it from a prior boot
stage, e.g. QEMU.
Provide a command to display the SMBIOS information.
Currently only type 1 and 2 are translated to human readable text.
Other types may be added later. Currently only a hexdump and the list of
strings is provided for these.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Patrice Chotard [Wed, 17 Jan 2024 12:37:13 +0000 (13:37 +0100)]
common: console: Fix print complete stdio device list
In case CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV are on and
stdin or stdout or stderr are missing in environment, as fallback, get
these either from stdio_devices[std] or stdio_devices[std]->name.
Fixes: 6b343ab38d ("console: Print out complete stdio device list") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Svyatoslav Ryhel [Wed, 17 Jan 2024 10:55:46 +0000 (12:55 +0200)]
cmd: bootmenu: rename U-Boot console to Exit
It seems that the U-Boot console entry of the bootmenu has lost
its original meaning. Now, even if it is chosen, the probability
that you will enter the actual U-Boot console is quite low.
Boot env, bootflow, bootcommand script may appear, but not the
actual console. Hence, let's remove ambiguity and name this
entry by what it actually does: 'Exit' the bootmenu.
Max Krummenacher [Wed, 17 Jan 2024 10:16:49 +0000 (11:16 +0100)]
board: verdin-am62: set cpu core voltage depending on speed grade
Speed grade T requires the VDD_CORE voltage to be 0.85V if using
the maximum core frequency.
Speed grades G, K, S allow the VDD_CORE voltage to be 0.75V up to the
maximum core frequency but allow to run at 0.85V.
For efficiency in manufacturing and code maintenance we use 0.85V for
the PMIC defaults and device tree settings and dynamically adjust the
voltage in the PMIC and device tree to 0.75V for lower speed SKU to
gain more than 100mW power consumption reduction.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Max Krummenacher [Wed, 17 Jan 2024 10:16:47 +0000 (11:16 +0100)]
arm: mach-k3: am62: move device identification accessor functions to header
mach-k3/am625_fdt.c does fdt fixup depending on fields in the device
identification register. Move the accessors to the device identification
register as inline functions into the am62_hardware.h header, so that
they can be used for other functionality.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
In the #else path ENOSYS is used, however linux/errno.h is not included.
If errno.h has not been included already the compiler errors out even
if the inline function is not referenced.
Make those headers self contained.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Tom Rini <trini@konsulko.com>
The value of CONFIG SYS_MAXARGS limits the usability of the 'for' command.
The current default of 16 is too low for some use case. Cf.
https://bugs.launchpad.net/snap-core18/+bug/1910094
Increase the default to 64.
Reported-by: Dave Jones <dave.jones@canonical.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
board: ti: common: board_detect: Fix EEPROM offset read for 1-byte
EEPROM detection logic in ti_i2c_eeprom_get() involves reading
the total size and the 1-byte size with an offset 1. The commit 9f393a2d7af8 ("board: ti: common: board_detect: Fix EEPROM read
quirk for 2-byte") that attempts to fix this uses a wrong pointer to
compare.
The value with one offset is read into offset_test, but the pointer
used to match was still ep, resulting in an invalid comparison of the
values. The intent is to identify bad 2-byte addressing eeproms that
get stuck on the successive reads.
Fixes: 9f393a2d7af8 (board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte) Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Tested-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tom Rini [Mon, 22 Jan 2024 18:30:23 +0000 (13:30 -0500)]
Merge patch series "omap3: Make SPL_OMAP3_ID_NAND depend on NAND_OMAP_GPMC"
This series results in making it such that with CONFIG_MTD disabled we
then do not prompt the user for a number of memory technology device
related options and so clean up our configuration menu / display.
Tom Rini [Wed, 10 Jan 2024 18:46:10 +0000 (13:46 -0500)]
mtd: Make CONFIG_MTD be the gate symbol for the menu
The help for CONFIG_MTD explains that it needs to be enabled for various
things like NAND, etc to be available. It however then doesn't enforce
this dependency and so if you have none of these systems present you
still need to disable a number of options. Fix this by making places
that select/imply one type of flash, but did not do the same, also do
this for "MTD". Make boards which hadn't been enabling MTD already but
need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it
wasn't previously enabled but was now being implied.
Tom Rini [Wed, 10 Jan 2024 18:46:09 +0000 (13:46 -0500)]
cmd/flash: Make this default y for CFI and NOR only
This command is only useful on CFI and NOR type flashes and not others.
Update the dependency so that it's not enabled by default in other
cases. This will lead to a number of platforms no longer building this
command, where it was not useful.
Tom Rini [Wed, 10 Jan 2024 18:46:08 +0000 (13:46 -0500)]
env: Make ENV_IS_IN_SPI_FLASH depend on SPI flash being present
In order for our environment to be present on SPI flash we need to
depend not on the symbol for a SPI controller but rather that SPI flash
of some sort is present. Update the dependencies.
Tom Rini [Wed, 10 Jan 2024 18:46:06 +0000 (13:46 -0500)]
omap3: Make SPL_OMAP3_ID_NAND depend on NAND_OMAP_GPMC
This specific bit logic is used to determine what NAND chip is present
on a board in order to then know what revision of the board we have and
so what DDR chips are present. We can only do this if we have a NAND
chip, and so we will have NAND_OMAP_GPMC enabled.
Shantur Rathore [Sat, 9 Dec 2023 18:10:56 +0000 (18:10 +0000)]
common: usb-hub: Reset hub port before scanning
Currently when a hub is turned on, all the ports are powered on.
This works well for hubs which have individual power control.
For the hubs without individual power control this has no effect.
Mostly in these scenarios the hub port is powered before the USB
controller is enabled, this can lead to some devices in unexpected
state.
With this patch, we explicitly reset the port while powering up hub
This resets the port for hubs without port power control and has
no effect on hubs with port power control as the port is still off.
Before this patch AMicro AM8180 based NVME to USB adapter won't be
detected as a USB3.0 Mass Storage device but with this it works as
expected.
Tested working after this patch:
1. AMicro AM8180 based NVME to USB Adapter
2. Kingston DataTraveler 3.0
3. GenesysLogic USB3.0 Hub
The drives were tested while connected directly and via the hub.
Signed-off-by: Shantur Rathore <i@shantur.com> Reviewed-by: Marek Vasut <marex@denx.de>
Tom Rini [Mon, 22 Jan 2024 14:47:52 +0000 (09:47 -0500)]
Merge tag 'u-boot-imx-master-20240122' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Allow i.MX8M Plus DHCOM to operate in overdrive mode.
- Allow i.MX8M Plus eDM SBC to operate in overdrive mode.
- Enable the 'kaslrseed' command on DH i.MX8M Plus DHCOM.
- Select LTO by default on i.MX8M.
- Convert pico-dwarf/hobbit-imx6ul to CONFIG_DM_SERIAL.
- Fix 'reset' command on wandboard.
Clearfog GTR has an assembly option for a SATA connector, CON18.
It shares the serdes with mini-pcie connector CON3.
Add new kconfig option to select betweenata and pci, defaulting to pci
as it was previously configured in board-file.
Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.
Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps network link on
Clearfog GTR.
Marek Vasut [Sat, 20 Jan 2024 00:35:58 +0000 (01:35 +0100)]
ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM and inserted into the /chosen node 'kaslr-seed' property of
Linux kernel DT before boot, thus letting KASLR work properly.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Marek Vasut [Fri, 19 Jan 2024 16:08:32 +0000 (17:08 +0100)]
ARM: imx: Configure GIC clock parent on Data Modul i.MX8M Plus eDM SBC
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT
and fill in the GIC clock configuration code.
Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Marek Vasut [Fri, 19 Jan 2024 16:07:54 +0000 (17:07 +0100)]
ARM: imx: Enable SPL_BOARD_INIT on DH i.MX8M Plus DHCOM
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT .
Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
Fabio Estevam [Thu, 18 Jan 2024 15:06:39 +0000 (12:06 -0300)]
imx8m: Enable LTO by default
In an attempt to select ARMV8_SPL_EXCEPTION_VECTORS, the SPL size
could not fit into the internal SRAM of some imx8m targets:
aarch64: + imx8mm_phg
+aarch64-linux-ld.bfd: u-boot-spl section `__u_boot_list' will not fit in region `.sram'
+aarch64-linux-ld.bfd: region `.sram' overflowed by 1824 bytes
Select LTO to prevent that.
Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
Dinesh Maniyam [Fri, 15 Dec 2023 07:21:51 +0000 (15:21 +0800)]
arm: dts: agilex: Increase reserved memory size to 32MB
The reserved space is extended to 32MB in Linux kernel because
additional space is needed for authorization execution of JIC/RBF file.
U-Boot required to align with Linux.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Dinesh Maniyam [Fri, 15 Dec 2023 07:15:19 +0000 (15:15 +0800)]
clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)
MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Dinesh Maniyam [Thu, 7 Dec 2023 07:46:02 +0000 (15:46 +0800)]
arm: socfpga: stratix10: SPI clock support
This patch is to add SPI clock support for stratix10. Get clock rate
function always returning 0 because the DW-SPI driver get the rate
from clock node in dts but Stratix10 does not support device tree
clock node.To overcome this spi will get the clock_rate directly
from spi clock controller override the weaker function.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tom Rini [Sun, 21 Jan 2024 14:11:33 +0000 (09:11 -0500)]
Merge tag 'efi-2024-04-rc1-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2024-04-rc1-3
Documentation:
* correct documentation of part_get_bootable()
* remove duplicate word "has" in UEFI documentation
UEFI:
* rename check_disk_has_default_file function
* auto-generate boot option for each blkio device
* auto-generate removable media boot option first
* avoid pointer access after calling efi_delete_handle
* create common function to free struct efi_disk_obj
* return immediately in UCLASS_EFI_LOADER removal
Masahisa Kojima [Fri, 19 Jan 2024 00:45:45 +0000 (09:45 +0900)]
efi_loader: create common function to free struct efi_disk_obj
Current error handling of creating raw disk/partition has
following issues.
- duplicate free for EFI handle, EFI handle is already freed
in efi_delete_handle()
- missing free for struct efi_device_path and
struct efi_simple_file_system_protocol in some error paths
To address those issues, this commit creates the common function
to free the struct efi_disk_obj resources and calls it in case
of error.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
projects / u-boot.git / log