Tom Rini [Fri, 12 Apr 2019 16:34:44 +0000 (12:34 -0400)]
Merge git://git.denx.de/u-boot-marvell
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
board support (Chris)
Tom Rini [Fri, 12 Apr 2019 16:22:43 +0000 (12:22 -0400)]
Merge branch '2019-04-11-ti-master-imports'
- Improve Keystone 3 SoC support (DMA, TI SCI)
- Improve Keystone 2 SoC support (PHY fixes on various platforms)
- Improve am335x families (new platforms, more boot mode options in SPL
via DM).
- General DaVinci, OMAP5 fixes.
Faiz Abbas [Fri, 5 Apr 2019 08:48:46 +0000 (14:18 +0530)]
mmc: omap_hsmmc: Set 3.3V for IO voltage
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Tom Rini [Tue, 19 Mar 2019 11:14:37 +0000 (07:14 -0400)]
ti: keystone2: Move CONFIG_ISW_ENTRY_ADDR to a common place
The ISW_ENTRY_ADDR Kconfig option under mach-omap2 isn't a SoC specific
notion but rather "where is our previous stage loaded in memory?"
option. Make use of this on ARCH_KEYSTONE rather than SPL_TEXT_BASE for
our HS builds that are not using SPL anyhow.
Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Andrew F. Davis <afd@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com?
Faiz Abbas [Mon, 18 Mar 2019 08:24:34 +0000 (13:54 +0530)]
net: ti: cpsw-common: Isolate getting syscon address from assigning macid
ti_cm_get_macid() is used to get a syscon node from the dt, read the
efuse address and then assign the macid read from the address. Divide
these two steps into separate functions one of which can be called from
ofdata_to_platdata() while the other can be called from _probe(). This
ensures that platdata can be assigned statically in a board file when
OF_CONTROL is not enabled. Also add a macid_sel_compat in private data
to get information about the macid byte placement.
Faiz Abbas [Mon, 18 Mar 2019 08:24:33 +0000 (13:54 +0530)]
net: ti: cpsw: Convert cpsw_platform_data to a pointer in cpsw_priv
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it
dynamically and assign it as a part of eth_pdata. This helps in
isolating platform data handling and implementing platdata for SPL
in a board file.
Faiz Abbas [Mon, 18 Mar 2019 08:24:32 +0000 (13:54 +0530)]
net: ti: cpsw: Move cpsw_phy_sel() to _probe()
cpsw_phy_sel() is a configuration step that should not be in
ofdata_to_platdata(). Add phy_sel_compat to the cpsw_platform_data
structure so that it is accessible in _probe. Then move the call of
cpsw_phy_sel() to _probe.
armv7R: K3: am654: Trigger panic on DDR init failures
When initializing DDR from R5 SPL trigger U-Boot's panic facility
rather than simply returning from the board init function as there
is little point continuing code execution. Further, as panic implies
a board reset, so using it might potentially allow to recover from
this error in certain cases such as when the init failure was caused
by a temporary glitch of some sorts.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Fri, 8 Mar 2019 06:17:35 +0000 (11:47 +0530)]
board: ti: am65x: Enable fixing up msmc sram node
Create a ft_board_setup() api that gets called as part of
DT fixup before jumping to kernel. In this ft_board_setup()
call fdt_fixup_msmc_ram that update msmc sram node.
Lokesh Vutla [Fri, 8 Mar 2019 06:17:34 +0000 (11:47 +0530)]
arm: k3: Add support for updating msmc dt node
Certain parts of msmc sram can be used by DMSC or can be
marked as L3 cache. Since the available size can vary, changing
DT every time the size varies might be painful. So, query this
information using TISCI cmd and fixup the DT for kernel.
Fixing up DT does the following:
- Create a sram node if not available
- update the reg property with available size
- update ranges property
- loop through available sub nodes and delete it if:
- mentioned size is out if available range
- subnode represents l3 cache or dmsc usage.
Lokesh Vutla [Fri, 8 Mar 2019 06:17:32 +0000 (11:47 +0530)]
firmware: Add support for querying msmc memory
DMSC can use certain amount of msmc memory available in the
system. Also certain part of msmc memory can be marked as L3
cache using board config. But users might not know what size
is being used and the remaining available msmc memory. In order
to fix this TISCI protocol provides a messages that can query
the available msmc memory in the system. Add support for this
message.
board: ti: dra71: Add pinmux settings for NAND on DRA71x EVM
By default VOUT3 occupies the pins required for NAND. Therefore, create
a seperate entry that can be use to reconfigure these pins to work for
NAND.
On the EVM SWITCH 8 pins 0 and 1 will be used to determine if NAND is
enabled or not. For NAND to be selected pin 0 should be on and pin 1
should be off. Any other combination will assume NAND shouldn't be
enabled.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Adam Ford [Tue, 26 Feb 2019 03:53:47 +0000 (21:53 -0600)]
ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATA
With the memory mapping giving us some more avialable RAM, this
updates the da850-evm-u-boot.dtsi to include the serial port, SPI
and Flash nodes along with some dependent nodes in the SPL dtb.
This also removes the platform data initialization code for the
serial port and SPI Flash.
Adam Ford [Tue, 26 Feb 2019 03:53:46 +0000 (21:53 -0600)]
davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit
larger. This patch relocates BSS to SDRAM instead of SRAM which
is similar to how ARMv7 boards (like OMAP2+) do it.
This means two new variables are required:
CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE
CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte
before the location where U-Boot will load.
Martyn Welch [Mon, 25 Feb 2019 15:32:59 +0000 (15:32 +0000)]
env: Don't check CONFIG_ENV_OFFSET_REDUND for SPL build
When booting using an SPL on am335x, if we want to support booting with
the boot ROM loader via USB (which uses RNDIS, making bootp and tftp
calls) we need to enable gadget eth in the SPL to load the main U-Boot
image. To enable CONFIG_SPL_ETH_SUPPORT, we must enable
CONFIG_SPL_ENV_SUPPORT as the environment is used by the eth support, but
we don't actually need to have environment variables saved in the SPL
environment. We do however have environment variables saved in the main
U-Boot image and enable CONFIG_ENV_OFFSET_REDUND (we are storing in raw
NAND). In such instances, even with the build config enabling both
CONFIG_CMD_SAVEENV and CONFIG_CMD_NAND, these options aren't set when
building the SPL, but CONFIG_ENV_OFFSET_REDUND still is.
Don't check this configuration option for SPL builds to enable the above
configuration.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:07 +0000 (12:02 -0500)]
ARM: dts: k2g-ice: add dt node for netcp
This patch adds dt node for DP83867 phy used on K2G ICE board and
also enable netcp device nodes for the board.
EVM hardware spec recommends to add 0.25 nsec delay in the tx
direction and 2.25 nsec delay in the rx direction for internal
delay in the clock path to be on the safer side.
The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode
1. Unfortunately, the phy data manual disallows this. Add
ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to
enable workaround suggested for this incorrect strap setting. This
ensures proper operation of this PHY.
The dts bindings are kept in sync with that from 4.14.y linux
kernel. This required the pinmux device related bindings to be
commented out to allow for compilation.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:05 +0000 (12:02 -0500)]
ARM: dts: k2g-evm: remove unused phy-mode property from phy node
This patch removes the unused phy-mode property from the phy dt node. On
K2G, currently link-interface determines if phy is used or not and is
already set to use rgmii. So this is not needed. Besides phy-mode should
be added to slave interface configuration of the cpsw driver, not in the
phy node.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:04 +0000 (12:02 -0500)]
ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:01 +0000 (12:02 -0500)]
ARM: k2g-ice: Add pinmux support for rgmii interface
This add pinmux configuration for rgmii interface so that network
driver can be supported on K2G ICE boards. The pinmux configurations
for this are generated using the pinmux tool at
https://dev.ti.com/pinmux/app.html#/default
As this required some BUFFER_CLASS definitions, same is re-used
from the linux defnitions in include/dt-bindings/pinctrl/keystone.h
Chris Packham [Thu, 11 Apr 2019 20:47:04 +0000 (08:47 +1200)]
ARM: mvebu: rename armada-385-amc.dts to armada-385-db-88f6820-amc.dts
This board was added to u-boot first but the Linux maintainers requested
a more descriptive name. Rename the file to match the Linux usage and
update the board defconfig.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Leigh Brown [Tue, 19 Mar 2019 14:50:09 +0000 (14:50 +0000)]
ARM: kirkwood: remove obsolete call to icache_enable
Commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache routines to
common file") changed cache setup for Kirkwood such that icache_enable()
is now called from enable_caches() which is called from initr_caches()
which is in the list of functions in init_sequence_r[] prior to
arch_misc_init(). This means the call to icache_enable() in
arch_misc_init() is no longer required, so remove it.
Signed-off-by: Leigh Brown <leigh@solinno.co.uk> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 11 Apr 2019 10:22:53 +0000 (22:22 +1200)]
arm: mvebu: Add DB-XC3-24G4XG board
The DB-XC3-24G4XG is a switch development board from Marvell. It can
either use and external CPU card such as the db-88f6820-amc or the
internal CPU that is integrated into the switch.
Add support for running U-Boot on the internal CPU and enable the USB,
SPI and NAND peripherals. For now this needs the bin_hdr from the
Marvell U-Boot for this board.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 11 Apr 2019 10:22:51 +0000 (22:22 +1200)]
arm: mvebu: NAND clock support for MSYS devices
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 11 Apr 2019 10:22:50 +0000 (22:22 +1200)]
arm: mvebu: Add Marvell's integrated CPUs
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Mon, 8 Apr 2019 12:51:49 +0000 (14:51 +0200)]
arm: mvebu: AXP: Enhance PCIe port capability configuration
This patch enables the PCIe port specific link capabilities configuration
for Armada XP. The weak function board_sat_r_get() was used to return
a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This
is now changed with this patch to return a bit per PCIe port (4 bits
in this case, bit 0 for PCIe port 0, etc).
The theadorable board uses this new feature to configure PCIe port 0
as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards
using this function are not changed in the configuration and still
configure all ports as PCIe Gen2.
This patch also removes the parameter "pex_mode" from
board_serdes_cfg_get() as this parameter was not used in any of the
implementations.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc>
Michael Walle [Sat, 6 Apr 2019 00:24:02 +0000 (02:24 +0200)]
cmd: add wdt command
Add a command to control the watchdog devices. This is useful if the
watchdog is rather long running (eg. seconds) and it should be
controlled by scripts. It is also handy during debugging.
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Stefan Roese <sr@denx.de>
Michael Walle [Wed, 3 Apr 2019 21:28:30 +0000 (23:28 +0200)]
sata: sata_mv: add orion-sata compatible string
The kirkwood devices are compatible with this driver.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Michael Walle [Wed, 3 Apr 2019 21:28:28 +0000 (23:28 +0200)]
sata: sata_mv: use correct format specifier in debug()
This fixes a compile error on kirkwood.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Wed, 27 Mar 2019 13:31:36 +0000 (14:31 +0100)]
arm: mvebu: ds412: Enable CONFIG_BLK
This patch enables CONFIG_BLK for the ds414 Armada XP based platform.
This removes this build warning:
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Please note that I don't have this board and can't test this change.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc>
Baruch Siach [Wed, 27 Mar 2019 06:01:26 +0000 (08:01 +0200)]
mvebu: drop dangling SPI flash comments and #ifdefs
Following commits abe66b1b5dec ("Convert CONFIG_ENV_SPI_* to Kconfig")
and 14453fbfadc2f ("Convert CONFIG_SF_DEFAULT_* to Kconfig") remove
dandling comment lines and empty #ifdef sections.
Cc: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Wed, 13 Mar 2019 07:47:10 +0000 (20:47 +1300)]
ARM: kirkwood: enable CONFIG_DM_USB for lschlv2 and lsxhl
Enable CONFIG_DM_USB and CONFIG_BLK.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Wed, 13 Mar 2019 07:47:06 +0000 (20:47 +1300)]
ARM: kirkwood: enable CONFIG_DM_USB for {dream, guru, sheeva}plug
Enable CONFIG_DM_USB and where possible CONFIG_BLK.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Leigh Brown <leigh@solinno.co.uk> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Wed, 13 Mar 2019 07:47:03 +0000 (20:47 +1300)]
ARM: kirkwood: switch to using mvebu mbus
The mvebu mbus code already had most of the support required for
kirkwood. The only difference is that unlike the other mvebu targets
kirkwood doesn't have a bridge control block so the code related to
managing that needs to be compiled out.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Wed, 13 Mar 2019 07:47:02 +0000 (20:47 +1300)]
ARM: kirkwood: remove KW_DEFADR_PCI_IO_REMAP
KW_DEFADR_PCI_IO_REMAP has the same value as KW_DEFADR_PCI_IO and is
only used to set up a 1:1 mapping. Remove it and update the mapping to
use KW_DEFADR_PCI_IO.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Tue, 12 Mar 2019 06:46:35 +0000 (07:46 +0100)]
Makefile: Correct logic for DM_SCSI + unconverted drivers check
When checking for boards that are enabling a SATA driver that isn't
converted to DM yet we need to be sure to not also trip over boards that
do set CONFIG_AHCI & CONFIG_BLK by itself, as that is not a bug.
This was detected when converting the Armada XP SATA driver sata_mv.c
to DM with AHCI & BLK support. This warning is still printed without
this patch applied here.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Stefan Roese [Mon, 11 Mar 2019 12:56:14 +0000 (13:56 +0100)]
arm: mvebu: theadorable: Add test for ctrl-c in PCIe PEX switch test
The check for the missing PEX switch can lead to an infinite loop, when
the PCIe device is not found. It is helpful to enable the user to break
out of this boot-loop, to enable booting to the prompt for test cases.
This patch adds a 3 second delay in the error case before rebooting.
The user can press Ctrl-C in this time to abort the boot-loop.
This patch also calls bootcount_inc() before rebooting in the error
case. This is needed to increment the bootcounter, since this function
is called earlier than the main bootcounter increment. Otherwise the
bootcounter will not be incremented in the error case at all.
Stefan Roese [Mon, 11 Mar 2019 12:29:20 +0000 (13:29 +0100)]
sata: sata_mv: Add DM support to enable CONFIG_BLK usage
This patch adds DM support to the Armada XP SATA driver. This is needed
to enable CONFIG_BLK on this platform. It adds the SATA controller as
AHCI device, which is strictly speaking not correct, as the controller
is not AHCI compatible. But the U-Boot AHCI uclass interface enables
the usage of this DM driver and the creation of the corresponding BLK
devices.
This conversion is done to get rid of the compile warning: Reviewed-by: Chris Packham <judge.packham@gmail.com>
===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
Chris Packham [Tue, 19 Feb 2019 07:28:44 +0000 (20:28 +1300)]
tools: kwbimage: don't adjust for image_header for Armada MSYS
For the time being the Armada MSYS SoCs need to use the bin_hdr from the
Marvell U-Boot. Because of this the binary.0 does not contain the image
header that a proper u-boot SPL would so the adjustment introduced by
commit 94084eea3bd3 ("tools: kwbimage: Fix dest addr") does not apply.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Sun, 17 Feb 2019 21:30:54 +0000 (10:30 +1300)]
arm: mvebu: x530: Enable watchdog in SPL and U-Boot
Enable the hardware watchdog to guard against system lock ups when
running in the SPL or U-Boot. Stop the watchdog just before booting so
that the OS can re-enable it if needed.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Sun, 17 Feb 2019 21:30:53 +0000 (10:30 +1300)]
watchdog: orion_wdt: take timeout value in ms
The generic wdt_start API expects to be called with the timeout in
milliseconds. Update the orion_wdt driver to accept a timeout in
milliseconds and use the clock rate specified in the dts to convert the
timeout to an appropriate value for the timer reload register.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Sun, 17 Feb 2019 21:30:52 +0000 (10:30 +1300)]
watchdog: orion_wdt: support SPL usage
When run from the SPL the mvebu targets are using the hardware default
offset for the SoC peripherals. devfdt_get_addr_size_index() understands
how to deal with this via dm_get_translation_offset() so use this
instead of fdtdec_get_addr_size_auto_noparent().
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Vignesh R [Tue, 5 Feb 2019 12:01:24 +0000 (17:31 +0530)]
dma: ti: add driver to K3 UDMA
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
channels. Channels in the UDMA-P can be configured to be either Packet-Based or
Third-Party channels on a channel by channel basis.
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.
Supported ring modes:
- Ring Mode
- Messaging Mode
- Credentials Mode
- Queue Manager Mode
TI-SCI integration:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.
The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while TI-SCI Message
Protocol supports only one combined operation (allocate+configure).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
firmware: ti_sci: Add support for NAVSS resource management
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.
This patch adds support for requesting and configuring such resources
from TI-SCI firmware.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
Tom Rini [Tue, 9 Apr 2019 20:08:52 +0000 (16:08 -0400)]
test.py: Disable fsck for FAT tests for now
Currently enabling fsck on FAT16/FAT32 exposes that we have problems
with:
TestFsBasic.test_fs13[fat16]
TestFsBasic.test_fs11[fat32]
TestFsBasic.test_fs12[fat32]
TestFsBasic.test_fs13[fat32]
TestFsExt.test_fs_ext1[fat32]
TestFsExt.test_fs_ext2[fat32]
TestFsExt.test_fs_ext3[fat32]
TestFsExt.test_fs_ext4[fat32]
TestFsExt.test_fs_ext5[fat32]
TestFsExt.test_fs_ext6[fat32]
TestFsExt.test_fs_ext7[fat32]
TestFsExt.test_fs_ext8[fat32]
TestFsExt.test_fs_ext9[fat32]
TestMkdir.test_mkdir6[fat16]
TestMkdir.test_mkdir1[fat32]
TestMkdir.test_mkdir2[fat32]
TestMkdir.test_mkdir3[fat32]
TestMkdir.test_mkdir4[fat32]
TestMkdir.test_mkdir5[fat32]
TestMkdir.test_mkdir6[fat32]
TestUnlink.test_unlink1[fat16]
TestUnlink.test_unlink2[fat16]
TestUnlink.test_unlink3[fat16]
TestUnlink.test_unlink4[fat16]
TestUnlink.test_unlink5[fat16]
TestUnlink.test_unlink6[fat16]
TestUnlink.test_unlink7[fat16]
TestUnlink.test_unlink1[fat32]
TestUnlink.test_unlink2[fat32]
TestUnlink.test_unlink3[fat32]
TestUnlink.test_unlink4[fat32]
TestUnlink.test_unlink5[fat32]
TestUnlink.test_unlink6[fat32]
TestUnlink.test_unlink7[fat32]
This is because we don't update the "information sector" on FAT32.
While in the future we should resolve this problem and include that
feature, we should enable fsck for ext4 to ensure that things remain in
good shape there.
Benjamin Lim [Fri, 29 Mar 2019 11:29:45 +0000 (07:29 -0400)]
Fix ext4 block group descriptor sizing
Ext4 allows for arbitrarily sized block group descriptors when 64-bit
addressing is enabled, which was previously not properly supported. This
patch dynamically allocates a chunk of memory of the correct size.
Marek Vasut [Wed, 13 Mar 2019 16:49:29 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc read' performance check
Add option to the mmc rd test to check the duration of the
execution of the mmc read command. This allows intercepting
read performance regressions.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:28 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc info' test
Add test for 'mmc info' subcommand. This tests whether the card
information is obtained correctly and verifies the device, bus
speed, bus mode and bus width.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:27 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc rescan' test
Add test for 'mmc rescan' subcommand. This tests whether the
system can switch to a specific card and then rescan the card.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:26 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc dev' test
Add separate test for 'mmc dev' subcommand. This tests whether
the system can switch to a specific card.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:25 +0000 (17:49 +0100)]
test/py: mmc: Factor out device selection
Factor out the 'mmc dev' call so it can be recycled by other tests.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
A FAT12/FAT16 root directory location is specified by a sector offset and
it might not start at a cluster boundary. It also resides before the
data area (before cluster 2).
However, the current code assumes that the root directory is located at
a beginning of a cluster, causing no files to be found if that is not
the case.
Since the FAT12/FAT16 root directory is located before the data area
and is not aligned to clusters, using unsigned cluster numbers to refer
to the root directory does not work well (the "cluster number" may be
negative, and even allowing it be signed would not make it properly
aligned).
Modify the code to not use the normal cluster numbering when referring to
the root directory of FAT12/FAT16 and instead use a cluster-sized
offsets counted from the root directory start sector.
This is a relatively common case as at least the filesystem formatter on
Win7 seems to create such filesystems by default on 2GB USB sticks when
"FAT" is selected (cluster size 64 sectors, rootdir size 32 sectors,
rootdir starts at half a cluster before cluster 2).
dosfstools mkfs.vfat does not seem to create affected filesystems.
Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi> Reviewed-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Tested-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Gero Schumacher [Tue, 26 Feb 2019 15:45:22 +0000 (15:45 +0000)]
fs: ext4: Problem with ext4load and sparse files
Hi,
when I try to load a sparse file via ext4load, I am getting the error message
'invalid extent'
After a deeper look in the code, it seems to be an issue in the function ext4fs_get_extent_block in fs/ext4/ext4_common.c:
The file starts with 1k of zeros. The blocksize is 1024. So the first extend block contains the following information:
eh_entries: 1
eh_depth: 1
ei_block 1
When the upper layer (ext4fs_read_file) asks for fileblock 0, we are running in the 'invalid extent' error message.
For me it seems, that the code is not prepared for handling a sparse block at the beginning of the file. The following change, solved my problem:
I am really not an expert in ext4 filesystems. Can somebody please have a look at this issue and give me a feedback, if I am totally wrong or not?
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