Ken Ma [Mon, 26 Mar 2018 07:56:02 +0000 (15:56 +0800)]
arm64: a37xx: pinctrl: Fix gpio pin offset in register
For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Mon, 26 Mar 2018 07:56:01 +0000 (15:56 +0800)]
arm64: a37xx: pinctrl: Fix the pin 23 on south bridge
Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.
Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.
The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43284 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Mon, 26 Mar 2018 07:56:00 +0000 (15:56 +0800)]
arm64: a37xx: dts: Fix the number of GPIO on south bridge
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43286 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Mon, 26 Mar 2018 07:55:59 +0000 (15:55 +0800)]
arm64: a37xx: pinctrl: Fix number of pin in south bridge
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).
Reviewed-on: http://vgitil04.il.marvell.com:8080/43285 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Add mmc pins, pcie pins and sdio pins definition and do these pins'
configuration for DB board and espressobin board;
Add uart2 pins configuration for DB board.
Reviewed-on: http://vgitil04.il.marvell.com:8080/40914 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Mon, 26 Mar 2018 07:55:57 +0000 (15:55 +0800)]
arm64: a37xx: dts: Add pinctrl configuration for ESPRESSOBin board
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Mon, 26 Mar 2018 07:55:56 +0000 (15:55 +0800)]
arm64: a37xx: defconfig: Enable PINCTRL and GPIO support for ESPRESSOBin board
This patch enable the PINCTRL and GPIO support, including the GPIO
command on the Armada 3720 espressobin board.
Reviewed-on: http://vgitil04.il.marvell.com:8080/40746 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Mark Kettenis [Sat, 17 Mar 2018 08:34:27 +0000 (09:34 +0100)]
arm64: mvebu: a8k: Add distro boot support
The various load address values are taken from the a37xx configuration
and match the dowstream 'u-boot-2017.03-armada-17.10' release where
appropriate.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Stefan Roese <sr@denx.de>
Alexander Graf [Thu, 15 Mar 2018 10:14:19 +0000 (11:14 +0100)]
kwbimage: Fix out of bounds access
The kwbimage format is reading beyond its header structure if it
misdetects a Xilinx Zynq image and tries to read it. Fix it by
sanity checking that the header we want to read fits inside our
file size.
Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Tom Rini [Sun, 25 Mar 2018 16:00:00 +0000 (12:00 -0400)]
Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.05
- Fix mkimage recognition
- Update all my fragments
ZynqMP:
- Use clk driver
- Support loading elfs in el1
- Various DTS and defconfig changes
- Enable newer pmufw versions
- Support more clocks
- Remove ep108
- Secure image support
- Fix memtest setup
Zynq:
- Enabling watchdog driver
- Support more clocks
- defconfig changes
Petr Vorel [Sat, 24 Mar 2018 00:49:23 +0000 (01:49 +0100)]
Convert CONFIG_UBIFS_SILENCE_MSG to Kconfig
Introduce another difference from upstream (kernel) source in
fs/ubifs/super.c: adding preprocessor condition as y variable in
mount_ubifs() depends on CONFIG_UBIFS_SILENCE_MSG:
fs/ubifs/super.c:1337:15: error: variable ?y? set but not used [-Werror=unused-but-set-variable]
long long x, y;
Not setting CONFIG_UBIFS_SILENCE_MSG in am335x_igep003x_defconfig and
igep0032_defconfig. Although it was defined in their config headers, it
depends on CMD_UBIFS which is not set for them.
Signed-off-by: Petr Vorel <petr.vorel@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Heiko Schocher <hs@denx.de>
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Jagan Teki <jagan@openedev.com>
Tom Rini [Fri, 23 Mar 2018 13:31:24 +0000 (09:31 -0400)]
Merge git://git.denx.de/u-boot-arc
Alexey:
1. Significantly rework cache-related functionality.
In particular that fixes coherency problems in some corner-cases,
allows us to enable and disable caches in run-time and still
have properly running system, finally support execution from
real flash (before we used to run from DDR from the very beginning).
2. Remove string routines implemented in assembly.
That allows us to build and run U-Boot on wide range of ARC cores
with different configurations. I.e. whatever tuning is used on GCC's
command-line we'll get code for desired flavor of ARC.
Otherwise for each and every corner-case we would need to add ifdefs
in assembly code to accommodate missing instructions etc.
3. Get use of GCC's garbage collector which helps to slim-down resulting image
quite a bit.
4. Also now we may disable U-Boot self-relocation for ARC if needed either
by platform or for debugging purposes.
Michal Simek [Tue, 13 Mar 2018 10:07:25 +0000 (11:07 +0100)]
MAINTAINERS: Fix Zynq/ZynqMP and Microblaze fragments
Fix my fragments to list all files in the repo.
Also fix path to for Xilinx Zynq SoC (mach-zynq)
It should be the part of
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc)
And cover dts files in board MAINTAINERS files.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 14 Mar 2018 10:02:24 +0000 (11:02 +0100)]
tools: xilinx: Fix zynq/zynqmp image recognition
There is an issue to recognize zynq or zynqmp image because header
checking is just the same. That's why zynqmp images are recognized as
zynq one.
Check unused fields which are initialized to zero in zynq format
(__reserved1 0x38 and __reserved2 0x44) which are initialized for
zynqmp. This should ensure that images are properly recognized by:
./tools/mkimage -l spl/boot.bin
Also show image type as ZynqMP instead of Zynq which is confusing.
Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Alexander Graf <agraf@suse.de>
arm64: zynqmp: Add support for verifying secure images
This patch adds new command "zynqmp" to handle zynqmp
specific commands like "zynqmp secure". This secure command is
used for verifying zynqmp specific secure images. The secure
image can either be authenticated or encrypted or both encrypted
and authenticated. The secure image is prepared using bootgen
and will be in xilinx specific BOOT.BIN format. The optional
key can be used for decryption of encrypted image if user
key was specified while creation BOOT.BIN.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Mon, 5 Mar 2018 09:54:59 +0000 (15:24 +0530)]
arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more
NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Thu, 15 Feb 2018 05:54:41 +0000 (11:24 +0530)]
arm64: zynqmp: Changed scratch address used by the alternate memory test
This patch changed CONFIG_SYS_MEMTEST_SCRATCH address to the
accessible DDR address used by alternate memory test.
Before this, 0xfffc0000 address was used, which is the OCM
address and not enabled in MMU table. So, whenever trying
to access 0xfffc0000 address, got Synchronous Abort exception.
After changing CONFIG_SYS_MEMTEST_SCRATCH address, alternate
memory test is working fine.
net: zynq_gem: Dont run any phy detection logic for GMII case
This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Fri, 26 Jan 2018 12:17:04 +0000 (13:17 +0100)]
fpga: Simplify error path in fpga_add
Check !desc earlier to simplify code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Lokesh Vutla [Fri, 16 Mar 2018 08:52:12 +0000 (14:22 +0530)]
davinci: Enable DDR_INIT for DA8XX
Commit 6aa4ad8e3820 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for
SOC_DA8XX, which broke OMAPL138 to boot.
Commit 2e87980580d0 ("davinci: Fix omapl138_lcdk builds") disabled
DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot
as ddr is not being initialized.
Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138
will have ddr initialized
Fixes: 2e87980580d0 ("davinci: Fix omapl138_lcdk builds") Fixes: 6aa4ad8e3820 ("Convert CONFIG_SOC_DA8XX et al to Kconfig") Reported-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: David Lechner <david@lechnology.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Luca Ceresoli [Thu, 15 Mar 2018 10:08:56 +0000 (11:08 +0100)]
scripts/check-config.sh: fix "command not found" error handling
scripts/check-config.sh exits successfully and silently without doing
any checks when the 'comm' command is not found.
The problem triggers from the command around line 39:
comm -23 ${suspects} ${ok} >${new_adhoc}
This statement fails when 'comm' is not in $PATH, creating an empty
${new_adhoc} file. But the script continues and the following line,
which is supposed to detect an error:
if [ -s ${new_adhoc} ]; then
will always be false since the file is empty, and the script will exit
successfully as if everything were OK.
The case where 'comm' in not in $PATH is not theoretical. It used to
happen on yocto until a recent fix [0], and still happens on the
current stable branch (rocko).
Fix by setting the errexit flag to exit with error when a statement
fails, so that at least the problem is noticed.
For additional safety also set the nounset flag to detect expansion
errors.
David Lechner [Thu, 15 Mar 2018 01:36:30 +0000 (20:36 -0500)]
davinci: omapl138_lcdk: fix PLL0 frequency
commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT must be 600MHz max). It also uses a PLLM value outside of
the range given in the TRM (it says PLLM must in the range 0 to 0x1f).
Alexander Graf [Thu, 15 Mar 2018 14:10:20 +0000 (15:10 +0100)]
lan7xxx: Require phylib
The lan75xx and lan78xx drivers need to drive their phy via the generic
phylib framework. Let's reflect that dependency in Kconfig, so that we
don't get build errors when phylib does not get selected.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alexander Graf [Thu, 15 Mar 2018 14:07:09 +0000 (15:07 +0100)]
net: Only access network devices after init
In the efi_loader main loop we call eth_rx() occasionally. This rx function
might end up calling into devices that haven't been initialized yet,
potentially resulting in a lot of transfer timeouts.
Instead, let's make sure the ethernet device is actually initialized before
reading from or writing to it.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The "net_try_count" counter starts from "1".
And the "retrycnt" contains requested amount of retries.
With current logic, that means that the actual retry amount
will be one time less then what we set in "netretry" env.
For example setting "netretry" to "once" will make "retrycnt"
equal "1", so no retries will be triggered at all.
Fix the logic by changing the statement of "if" condition.
Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Priyanka Jain [Tue, 30 Jan 2018 06:41:08 +0000 (12:11 +0530)]
net/phy/cortina: Add No firmware upload option
Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.
But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.
Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.
This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different bus.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Calvin Johnson [Thu, 8 Mar 2018 10:00:33 +0000 (15:30 +0530)]
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Calvin Johnson [Thu, 8 Mar 2018 10:00:26 +0000 (15:30 +0530)]
drivers: net: pfe_eth: provide pfe commands
pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Calvin Johnson [Thu, 8 Mar 2018 10:00:23 +0000 (15:30 +0530)]
drivers: net: phy: Fix aquantia compilation with DM
With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.
drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
phydev->dev->name);
^~
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: phy: Add PHY_RTL8211E_PINE64_GIGABIT_FIX for realtek phys
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off
on the PHY, as well as flipping some magical undocumented bits. The
magic number comes from the Pine64 engineering team, presumably as a
proxy from Realtek. This configuration fixes the throughput on some
Pine64 models. Packet loss of up to 60-70% has been observed without
this.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Eugeniy Paltsev [Thu, 22 Mar 2018 10:50:47 +0000 (13:50 +0300)]
DW SPI: use 32 bit access instead of 16 and 32 bit mix
Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Eugeniy Paltsev [Thu, 22 Mar 2018 10:50:46 +0000 (13:50 +0300)]
DW SPI: add option to use external gpio for chip select
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.
So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Eugeniy Paltsev [Thu, 22 Mar 2018 10:50:45 +0000 (13:50 +0300)]
DW SPI: refactor poll_transfer functions
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.
With these changes we're getting closer to Linux DW SPI driver.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Eugeniy Paltsev [Thu, 22 Mar 2018 10:50:44 +0000 (13:50 +0300)]
DW SPI: fix transmit only mode
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.
Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Eugeniy Paltsev [Thu, 22 Mar 2018 10:50:43 +0000 (13:50 +0300)]
DW SPI: fix tx data loss on FIFO flush
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Tuomas Tynkkynen [Tue, 13 Mar 2018 13:23:04 +0000 (15:23 +0200)]
tools: Make kwboot build if HOST_TOOLS_ALL=y
The kwboot tool for Marvell devices isn't currently being built even if
HOST_TOOLS_ALL is set. It doesn't appear to depend on any CONFIG_
options, so it seems appropriate to enable building it here.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
projects / u-boot.git / log