Tom Rini [Thu, 9 Jul 2020 12:22:44 +0000 (08:22 -0400)]
Merge tag 'for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for v2020.10
- Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
- Add I2C controller support for Cortina Access CAxxxx SoCs
- new rtc methods, rtc command, and tests
- imx_lpi2c: Improve the codes to use private data
- stm32f7_i2c.c: Add new compatible "st,stm32mp15-i2c"
- stm32f7_i2c.c: Add Fast Mode Plus support
- pwm: Add PWM driver for SiFive SoC
Simon Guinot [Sun, 28 Jun 2020 17:00:27 +0000 (19:00 +0200)]
arm: kirkwood: add DT spi0 alias to LaCie boards
The spi0 alias is needed by the environment code to retrieve the SPI
flash. This patch adds some -u-boot.dtsi files, providing the spi0
aliases, for all the following Kirkwood-based LaCie boards:
- d2 Network v2
- Internet Space v2
- 2Big Network v2
- Network Space v2
- Network Space Lite v2
- Network Space Max v2
- Network Space Mini v2
Note that this -u-boot.dtsi files will be removed as soon as the spi0
aliases will be available in the upstream Linux dtsi files.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Dennis Gilmore [Sat, 27 Jun 2020 20:00:16 +0000 (15:00 -0500)]
arm: mvebu: helios4: sync helios4 config to clearfog and dts to kernel
The helios4 is built on the same microsom as the clearfog, by syncing the config
we enable the same featureset that exists in the som on the helios4. The current
config does not boot as some of the clearfog changes needed to be made on the
helios4 also, generally speaking most changes for the clearfog should also be
made on the helios4.
Signed-off-by: Dennis Gilmore <dennis@ausil.us> Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 25 Jun 2020 00:48:51 +0000 (12:48 +1200)]
arm: mvebu: a38x: Adjust UTMI PHY parameters
When running USB compliance tests on our Armada-385 hardware platforms
we have seen some eye mask violations. Marvell's internal documentation
says: Based on silicon test results, it is recommended to change the
impedance calibration threshold setting to 0x6 prior to calibration.
Port changes from Marvell's u-boot fork[1] to address this.
Chris Packham [Wed, 27 May 2020 01:31:29 +0000 (13:31 +1200)]
mv_ddr: ddr3: Use correct bitmask for read sample delay
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample
delay fields are 5 bits wide. Use the correct bitmask of 0x1f when
extracting the value.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
i2c: stm32f7: SYSCFG Fast Mode Plus support for I2C STM32F7
Read SYSCFG bindings to set Fast Mode Plus bits if Fast Mode Plus
speed is selected.
Handle the stm32mp15 specific compatible to handle FastMode+
registers handling which is different on the stm32mp15 compared
to the stm32f7 or stm32h7.
Indeed, on the stm32mp15, the FastMode+ set and clear registers
are separated while on the other platforms (F7 or H7) the control
is done in a unique register.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
test: dm: rtc: add test of dm_rtc_read, dm_rtc_write
Define a few aux registers and check that they can be read/written
individually. Also check that one can access the time-keeping
registers directly and get the expected results.
The problem is that after each register write,
sandbox_i2c_rtc_complete_write() gets called and sets the internal
time from the current set of registers. However, when we get to
writing 31 to mday, the registers are in an inconsistent state (mon is
still 4), so the mktime machinery ends up translating April 31st to
May 1st. Upon the next register write, the registers are populated by
sandbox_i2c_rtc_prepare_read(), so the 31 we just wrote to mday gets
overwritten by a 1.
Fix it by writing all registers at once, and for consistency, update
the get method to retrieve them all with one "i2c transfer".
Mostly as an aid for debugging RTC drivers, provide a command that can
be used to read/write arbitrary registers (assuming the driver
provides the read/write methods or their single-register-at-a-time
variants).
This simply consists of renaming the existing pcf2127_read_reg()
helper to follow the naming of the other
methods (i.e. pcf2127_rtc_<method name>) and changing the type of its
"len" parameter.
rtc: fall back to ->{read, write} if ->{read, write}8 are not provided
Similar to how the dm_rtc_{read,write} functions fall back to using
the {read,write}8 methods, do the opposite in the rtc_{read,write}8
functions.
This way, each driver only needs to provide either ->read8 or ->read
to make both rtc_read8() and dm_rtc_read() work - without this, a
driver that provides ->read() would most likely just duplicate the
logic here for implementing a ->read8() method in term of its ->read()
method. The same remarks of course apply to the write case.
Similar to dm_rtc_read(), introduce a helper that allows the caller to
write multiple consecutive 8-bit registers with one call. If the
driver provides the ->write method, use that, otherwise loop using
->write8.
Some users may want to read multiple consecutive 8-bit
registers. Instead of each caller having to implement the loop,
provide a dm_rtc_read() helper. Also, allow a driver to provide a
->read method, which can be more efficient than reading one register
at a time.
Ye Li [Wed, 10 Jun 2020 03:29:50 +0000 (20:29 -0700)]
i2c: imx_lpi2c: Improve the codes to use private data
Current driver calls the devfdt_get_addr to get the base address
of lpi2c controller in each sub-functions. Since the devfdt_get_addr
accesses the DTB and translate the address, it introduces much
overhead.
Improve the codes to use private variable which has recorded the
base address from probe.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Heiko Stuebner [Fri, 22 May 2020 14:20:33 +0000 (16:20 +0200)]
lib: rsa: function to verify a signature against a hash
rsa_verify() expects a memory region and wants to do the hashing itself,
but there may be cases where the hashing is done via other means,
like hashing a squashfs rootfs.
So add rsa_verify_hash() to allow verifiying a signature against
an existing hash. As this entails the same verification routines
we can just move the relevant code over from rsa_verify() and also
call rsa_verify_hash() from there.
Simon Glass [Wed, 3 Jun 2020 01:26:49 +0000 (19:26 -0600)]
cmd: Add a memory-search command
It is useful to be able to find hex values and strings in a memory range.
Add a command to support this.
cmd: Fix 'md' and add a memory-search command
At present 'md.q' is broken. This series provides a fix for this. It also
implements a new memory-search command called 'ms'. It allows searching
memory for hex and string data.
END
Simon Glass [Wed, 3 Jun 2020 01:26:48 +0000 (19:26 -0600)]
command: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
This is defined only when __lp64__ is defined. That means that ulong is
64 bits long. Therefore we don't need to use a separate u64 type on those
architectures.
Fix up the code to take advantage of that, removing the preprocessor
conditions.
Also include the header file that defines MEM_SUPPORT_64BIT_DATA. It is
included by env.h in this file, but that might not last forever.
Simon Glass [Wed, 3 Jun 2020 01:26:47 +0000 (19:26 -0600)]
display_options: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
This is defined only when __lp64__ is defined. That means that ulong is
64 bits long. Therefore we don't need to use a separate u64 type on those
architectures.
Fix up the code to take advantage of that, removing the preprocessor
conditions.
Also include the missing header file that defines MEM_SUPPORT_64BIT_DATA
Fixes: 09140113108 ("command: Remove the cmd_tbl_t typedef") Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 3 Jun 2020 01:26:46 +0000 (19:26 -0600)]
cmd: mem: Drop #ifdef for MEM_SUPPORT_64BIT_DATA
This is defined only when __lp64__ is defined. That means that ulong is
64 bits long. Therefore we don't need to use a separate u64 type on those
architectures.
Fix up the code to take advantage of that, removing the preprocessor
conditions.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Replacing the ret variable with err and handling first the error
condition about the value returned by the spl_nand_fit_read routine,
improves the code readability.
Furthermore, the 'else' int the 'else return ret' instruction was
useless.
cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dariobin@libero.it>
Dario Binacchi [Wed, 27 May 2020 11:56:20 +0000 (13:56 +0200)]
spl: fit: nand: fix fit loading in case of bad blocks
The offset at which the image to be loaded from NAND is located is
retrieved from the itb header. The presence of bad blocks in the area
of the NAND where the itb image is located could invalidate the offset
which must therefore be adjusted taking into account the state of the
sectors concerned.
cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Dario Binacchi [Wed, 27 May 2020 11:56:19 +0000 (13:56 +0200)]
spl: fit: fail fit loading in case of FDT appending error
If uboot does not embed its device tree and the FIT loading function
returns error in case of failure in the FDT append, the redundant itb
image could be loaded.
cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stuebner [Thu, 18 Jun 2020 14:23:28 +0000 (16:23 +0200)]
spl: fit: select SPL_CRYPTO_SUPPORT for SPL_FIT_SIGNATURE
Verifying FIT images obviously needs the rsa parts of crypto
support and while main uboot always compiles crypto support,
it's optional for SPL and we should thus select the necessary
option to not end up in compile errors like:
u-boot/lib/rsa/rsa-verify.c:328: undefined reference to `rsa_mod_exp'
So select SPL_CRYPTO_SUPPORT in SPL_FIT_SIGNATURE.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stuebner [Thu, 18 Jun 2020 14:23:27 +0000 (16:23 +0200)]
spl: fit: select SPL_HASH_SUPPORT for SPL_FIT_SIGNATURE
rsa-checsum needs support for hash functions or else will run into
compile errors like:
u-boot/lib/rsa/rsa-checksum.c:28: undefined reference to `hash_progressive_lookup_algo'
So similar to the main FIT_SIGNATURE entry selects HASH,
select SPL_HASH_SUPPORT for SPL_FIT_SIGNATURE.
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stuebner [Thu, 18 Jun 2020 14:23:26 +0000 (16:23 +0200)]
lib: rsa: add documentation to padding_pss_verify to document limitations
padding_pss_verify only works with the default pss salt setting of -2
(length to be automatically determined based on the PSS block structure)
not -1 (salt length set to the maximum permissible value), which makes
verifications of signatures with that saltlen fail.
Until this gets implemented at least document this behaviour.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stuebner [Thu, 18 Jun 2020 14:23:25 +0000 (16:23 +0200)]
lib: rsa: free local arrays after use in rsa_gen_key_prop()
n, rr and rrtmp are used for internal calculations, but in the end
the results are copied into separately allocated elements of the
actual key_prop, so the n, rr and rrtmp elements are not used anymore
when returning from the function and should of course be freed.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
lib: rsa: fix allocated size for rr and rrtmp in rsa_gen_key_prop()
When calculating rrtmp/rr rsa_gen_key_prop() tries to make
(((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
(((rlen + 7) >> 3) + 1) / 4 steps in uint32_t rrtmp[]
with rlen being num_bits * 2
On a 4096bit key this comes down to to 257 uint32_t elements
in rr and 256 elements in rrtmp but with the current allocation
rr and rrtmp only have 129 uint32_t elements.
On 2048bit keys this works by chance as the defined max_rsa_size=4096
allocates a suitable number of elements, but with an actual 4096bit key
this results in other memory parts getting overwritten.
So as suggested by Heinrich Schuchardt just use the actual bit-size
of the key as base for the size calculation, in turn making the code
compatible to any future keysizes.
Heiko Stuebner [Thu, 18 Jun 2020 14:23:23 +0000 (16:23 +0200)]
lib: rsa: bring exp_len in line when generating a key_prop
The exponent field of struct key_prop gets allocated an uint64_t,
and the contents are positioned from the back, so an exponent of
"0x01 0x00 0x01" becomes 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1"
Right now rsa_gen_key_prop() allocates a uint64_t but sets exp_len
to the size returned from the parser, while on the other hand the
when getting the key from the devicetree exp_len always gets set to
sizeof(uint64_t).
So bring that in line with the established code.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stuebner [Thu, 18 Jun 2020 14:23:21 +0000 (16:23 +0200)]
lib: rsa: distinguish between tpl and spl for CONFIG_RSA_VERIFY
While the SPL may want to do signature checking this won't be
the case for TPL in all cases, as TPL is mostly used when the
amount of initial memory is not enough for a full SPL.
So on a system where SPL uses DM but TPL does not we currently
end up with a TPL compile error of:
lib/rsa/rsa-verify.c:48:25: error: dereferencing pointer to incomplete type ‘struct checksum_algo’
To prevent that change the $(SPL_) to $(SPL_TPL_) to distinguish
between both. If someone really needs FIT signature checking in
TPL as well, a new TPL_RSA_VERIFY config symbol needs to be added.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stuebner [Mon, 29 Jun 2020 23:05:45 +0000 (01:05 +0200)]
cmd: add a panic command
Even in boot scripts it may be needed to "panic" when all options
are exhausted and the device specification specifies hanging
instead of resetting the board.
So add a new panic command that just wraps around the core panic
call in U-Boot and can take an optional message.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Stefan Roese [Fri, 15 May 2020 05:09:03 +0000 (07:09 +0200)]
debug_uart: Add CR before and after announce string
Add linefeeds before and after the announce string. This makes the
output easier to read, especially if some text follows the announce
message without a specific additional CR.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Johannes Holland [Mon, 11 May 2020 13:22:25 +0000 (15:22 +0200)]
tpm: add #ifndef to fix redeclaration build errors
tpm_tis_spi.c directly includes tpm_tis.h and tpm-v2.h which both
define the same enums (see e.g. TPM_ACCESS_VALID). Add an #ifndef to
prevent redeclaration errors.
Signed-off-by: Johannes Holland <johannes.holland@infineon.com>
Bruno Thomsen [Fri, 12 Jun 2020 15:17:33 +0000 (17:17 +0200)]
tpm2: tis_spi: add linux compatible fallback string
This solves a compatibility issue with Linux device trees
that contain TPMv2.x hardware. So it's easier to import DTS
from upstream kernel when migrating board init from C code
to DTS.
The issue is that fallback binding is different between Linux
and u-Boot.
Linux: "tcg,tpm_tis-spi"
U-Boot: "tis,tpm2-spi"
As there are currently no in-tree users of the U-Boot binding,
it makes sense to use Linux fallback binding.
Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
The PHY needs a reset in order to be functionnal for U-Boot, add the old
PHY reset bindings for dwmac until we support the new bindings in the PHY node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
Andre Przywara [Thu, 11 Jun 2020 11:03:20 +0000 (12:03 +0100)]
arm: juno: Enable PCI
The ARM Juno boards in their -r1 and -r2 variants sport a PCIe
controller, which we configure already in board specific code to be ECAM
compliant. Hence we can just enable the generic ECAM driver to let
U-Boot use PCIe devices.
Add the respective options to the Juno defconfig to enable the PCI
framework and the generic ECAM driver, and initialise the driver upon
loading U-Boot.
Make some functions in the Juno PCIe init code static on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Thu, 11 Jun 2020 11:03:18 +0000 (12:03 +0100)]
arm: juno: Enable DM_ETH
The smc911X driver is now DM enabled, so we can switch the Juno board
over to use DM_ETH for the on-board Fast Ethernet device.
Works out of the box by using the DT.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Thu, 11 Jun 2020 11:03:17 +0000 (12:03 +0100)]
net: smc911x: Properly handle EEPROM MAC address
When compiled as a DM_ETH driver, the scm911x driver was reading the MAC
address from the optional EEPROM storage, but failed to copy this to the
platdata struct. Since it was also missing a definition of the
read_rom_hwaddr() function, the generic Ethernet code was dismissing
this MAC address, falling back to a random address or denying to start
at all.
Add an implementation of .read_rom_hwaddr, and refactor the function
reading the ROM address to be called by all interested parties.
This fixes MAC address issues when using the driver in DM_ETH "mode".
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Thu, 11 Jun 2020 11:03:16 +0000 (12:03 +0100)]
net: dm: Remove warning about EEPROM provided MAC address
Similar to patch 821fec0ceb3e ("net: remove scary warning about EEPROM
provided MAC address") this removes the somewhat awkward "warning" on
boards using DM_ETH:
In many parts of the computing world having a unique MAC address
sitting in some on-NIC storage is considered the normal case.
If there is a properly provided MAC address (either from ROM or from DT),
remove the warning to not scare the user unnecessarily.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Thu, 11 Jun 2020 11:03:15 +0000 (12:03 +0100)]
arm: vexpress64: Fix counter frequency
The arch timer on 64-bit Arm Ltd. platforms is driven by a 24 MHz
crystal oscillator, so the frequency is not 25165824 MHz, as the current
code suggests.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
On ARM systems gd is stored in register r9 or x18. When compiling with
clang gd is defined as a macro calling function gd_ptr(). So we can not
make assignments to gd.
Use function set_gd() for setting the register on ARM.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Schocher [Fri, 22 May 2020 09:08:59 +0000 (11:08 +0200)]
gpio: search for gpio label if gpio is not found through bank name
dm_gpio_lookup_name() searches for a gpio through
the bank name. But we have also gpio labels, and it
makes sense to search for a gpio also in the labels
we have defined, if no gpio is found through the
bank name definition.
This is useful for example if you have a wp pin on
different gpios on different board versions.
If dm_gpio_lookup_name() searches also for the gpio labels,
you can give the gpio an unique label name and search
for this label, and do not need to differ between
board revisions.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Don't enable by default] Signed-off-by: Tom Rini <trini@konsulko.com>
net: phy: realtek: Introduce PHY_RTL8201F_S700_RMII_TIMINGS to adjust rx/tx timings
RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have
specific Rx/Tx interface timings requirement for proper PHY operations.
These timing values are not documented anywhere and picked from vendor
code.
This commits lets proper packets to be transmitted over the network.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
net: phy: realtek: Add support for RTL8201F PHY module.
This patch adds support for Realtek PHY RTL8201F 10/100Mbs
(with variants: RTL8201FN and RTL8201FL) PHYceiver. It is
present on Actions Semi Cubieboard7 board.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Calculate the SDRAM size from DDR capacity register registers instead
of using hard-coded value. This is quite useful to get correct size
on differnt boards based on Actions OWL family of SoCs (S700 and S900).
There is no documentation available that talks about DDR registers, and
this is very much taken from vendor source.
This commit lets Linux boot on Cubieboard7-lite(based on S700).
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Niel Fourie [Mon, 30 Mar 2020 15:22:58 +0000 (17:22 +0200)]
cmd: blkls: Add blkls command
Add a command to print a list of available block device drivers,
and for each, the list of known block devices.
Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Renamed dm "drivers" subcommand to "compat" (as it listed
compatibility strings) and prevent it from segfaulting when
drivers have no of_match populated.
Added a new "drivers" subcommand to dump a list of all known DM
drivers and for each, their uclass id, uclass driver and names of
attached devices.
Added a new "static" subcommand to dump a list of DM drivers with
statically defined platform data.
Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Niel Fourie [Tue, 24 Mar 2020 15:17:04 +0000 (16:17 +0100)]
cmd: fs: Add command to list supported fs types
Added command "fstypes" to list supported/included filesystems.
Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Limit to sandbox] Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 7 Jul 2020 18:00:44 +0000 (14:00 -0400)]
Merge tag 'u-boot-stm32-20200707' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- arch and board update for stm32mp15:
- use OPP information in device tree for 800MHz/650MHz support
- ram: inprovments of test command
- solve boot on closed chip when access to DBGMCU_IDC is protected
- stm32prog command: Add "device anme" during USB enumeration
- update configs: activate WATCHDOG and 'env erase' command,
increase teed partition, support SD card after NOR boot by default and
use env info in env_check
- some sboard cleanups: gpio hog in dh board, specific driver for
type-c stusb1600 controller code in a driver move part of code in spl.c
and in common directory
- fix STM32 compatible for dwc_eth_qos driver
- support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
drivers
- vrefbuf: fix a possible overshoot when re-enabling
ARM Architecture reference manual clearly states that PE pipeline
should be flushed after changes to some system registers. Refer to
paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture
Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI
0487B.a).
Failing to issue instruction synchronization barrier can lead to
spurious errors, like synchronous exception when accessing FPU
registers. This is very prominent on CPUs with long instruction
pipeline, like ARM Cortex A72.
projects / u-boot.git / log