From: Pali Rohár <pali@kernel.org>
Date: Fri, 8 Apr 2022 12:39:57 +0000 (+0200)
Subject: powerpc: dts: p2020: Define L2 cache node
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=fd3dc72945474ca3665cd76c96350f7c0e7d95cf;p=u-boot.git

powerpc: dts: p2020: Define L2 cache node

Copy definition of L2 cache node from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 0a296cffe5..1c3f78798e 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -56,6 +56,14 @@
 /include/ "pq3-duart-0.dtsi"
 /include/ "pq3-gpio-0.dtsi"
 
+	L2: l2-cache-controller@20000 {
+		compatible = "fsl,p2020-l2-cache-controller";
+		reg = <0x20000 0x1000>;
+		cache-line-size = <32>; /* 32 bytes */
+		cache-size = <0x80000>; /* L2,512K */
+		interrupts = <16 2 0 0>;
+	};
+
 /include/ "pq3-etsec1-0.dtsi"
 /include/ "pq3-etsec1-timer-0.dtsi"
 
diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi
index 7c4c2061d4..7fdcb85c80 100644
--- a/arch/powerpc/dts/p2020.dtsi
+++ b/arch/powerpc/dts/p2020.dtsi
@@ -22,10 +22,12 @@
 		cpu0: PowerPC,P2020@0 {
 			device_type = "cpu";
 			reg = <0>;
+			next-level-cache = <&L2>;
 		};
 		cpu1: PowerPC,P2020@1 {
 			device_type = "cpu";
 			reg = <1>;
+			next-level-cache = <&L2>;
 		};
 	};
 };