From: Ramon Fried <ramon.fried@gmail.com>
Date: Sat, 12 Jan 2019 09:47:28 +0000 (+0200)
Subject: dts: 820c: Add pinctrl node and uart mux
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=fbf4152ba65045f8832a95ed2c31bd10805480bd;p=u-boot.git

dts: 820c: Add pinctrl node and uart mux

* Add pinctrl node for TLMM and add mux request for uart node.
* Rename uart to the actual board uart port.
* Fix indentendation of sdhc2 node.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---

diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi
index d60aa04494..8610d7ec37 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -13,14 +13,22 @@
 	soc {
 		u-boot,dm-pre-reloc;
 
+		qcom,tlmm@1010000 {
+			u-boot,dm-pre-reloc;
+
+			uart {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
 		clock-controller@300000 {
 			u-boot,dm-pre-reloc;
 		};
 
 		serial@75b0000 {
 			u-boot,dm-pre-reloc;
-			};
 		};
+	};
 };
 
 &pm8994_pon {
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index ffad8e0e0a..1114ddd7d3 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. DB820c";
@@ -16,7 +17,7 @@
 	#size-cells = <2>;
 
 	aliases {
-		serial0 = &blsp2_uart1;
+		serial0 = &blsp2_uart2;
 	};
 
 	chosen {
@@ -63,18 +64,32 @@
 			reg = <0x300000 0x90000>;
 		};
 
-		blsp2_uart1: serial@75b0000 {
+		pinctrl: qcom,tlmm@1010000 {
+			compatible = "qcom,tlmm-apq8096";
+			reg = <0x1010000 0x400000>;
+
+			blsp8_uart: uart {
+				function = "blsp_uart8";
+				pins = "GPIO_4", "GPIO_5";
+				drive-strength = <DRIVE_STRENGTH_8MA>;
+				bias-disable;
+			};
+		};
+
+		blsp2_uart2: serial@75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
 			clock = <&gcc 4>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp8_uart>;
 		};
 
 		sdhc2: sdhci@74a4900 {
-			 compatible = "qcom,sdhci-msm-v4";
-			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
-			 index = <0x0>;
-			 bus-width = <4>;
-			 clock = <&gcc 0>;
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+			index = <0x0>;
+			bus-width = <4>;
+			clock = <&gcc 0>;
 			clock-frequency = <200000000>;
 		 };