From: Philipp Tomsich Date: Wed, 31 May 2017 16:16:34 +0000 (+0200) Subject: rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=fbecb94e4b06a385adc860870ebd64e57f521b9f;p=u-boot.git rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock Revise the loop watching for a timeout on obtaining a DRAM PHY lock to clearly state a timeout in milliseconds and use get_timer (based on the ARMv8 architected timer) to detect a timeout. Signed-off-by: Philipp Tomsich Reviewed-by: Kever Yang Reviewed-by: Simon Glass --- diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index a3ae8bd4f0..1989578a30 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -5,6 +5,7 @@ * * Adapted from coreboot. */ + #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; struct chan_info { @@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret; + const ulong timeout_ms = 200; /* * work around controller bug: @@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); /* Wating for PHY and DRAM init complete */ - tmp = 0; - while (!(readl(&denali_ctl[203]) & (1 << 3))) { - mdelay(10); - tmp++; - if (tmp > 10) + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("DRAM (%s): phy failed to lock within %ld ms\n", + __func__, timeout_ms); return -ETIME; - } + } + } while (!(readl(&denali_ctl[203]) & (1 << 3))); + debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit);